radeon.h (1614f8b17b8cc3ad143541d41569623d30dbc9ec) radeon.h (4c7886791264f03428d5424befb1b96f08fc90f4)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31#include "radeon_object.h"
32
33/* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
36 * related to surface
37 * - WB : write back stuff (do it bit like scratch reg things)
38 * - Vblank : look at Jesse's rework and what we should do
39 * - r600/r700: gart & cp
40 * - cs : clean cs ioctl use bitmap & things like that.

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62 * are considered as fatal)
63 */
64
65#include <asm/atomic.h>
66#include <linux/wait.h>
67#include <linux/list.h>
68#include <linux/kref.h>
69
31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.

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60 * are considered as fatal)
61 */
62
63#include <asm/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
72
70#include "radeon_family.h"
71#include "radeon_mode.h"
72#include "radeon_reg.h"
73
74/*
75 * Modules parameters.
76 */
77extern int radeon_no_wb;

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181int radeon_fence_wait_last(struct radeon_device *rdev);
182struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
183void radeon_fence_unref(struct radeon_fence **fence);
184
185/*
186 * Tiling registers
187 */
188struct radeon_surface_reg {
73#include "radeon_family.h"
74#include "radeon_mode.h"
75#include "radeon_reg.h"
76
77/*
78 * Modules parameters.
79 */
80extern int radeon_no_wb;

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184int radeon_fence_wait_last(struct radeon_device *rdev);
185struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
186void radeon_fence_unref(struct radeon_fence **fence);
187
188/*
189 * Tiling registers
190 */
191struct radeon_surface_reg {
189 struct radeon_object *robj;
192 struct radeon_bo *bo;
190};
191
192#define RADEON_GEM_MAX_SURFACES 8
193
194/*
193};
194
195#define RADEON_GEM_MAX_SURFACES 8
196
197/*
195 * Radeon buffer.
198 * TTM.
196 */
199 */
197struct radeon_object;
200struct radeon_mman {
201 struct ttm_bo_global_ref bo_global_ref;
202 struct ttm_global_reference mem_global_ref;
203 bool mem_global_referenced;
204 struct ttm_bo_device bdev;
205};
198
206
199struct radeon_object_list {
207struct radeon_bo {
208 /* Protected by gem.mutex */
209 struct list_head list;
210 /* Protected by tbo.reserved */
211 struct ttm_buffer_object tbo;
212 struct ttm_bo_kmap_obj kmap;
213 unsigned pin_count;
214 void *kptr;
215 u32 tiling_flags;
216 u32 pitch;
217 int surface_reg;
218 /* Constant after initialization */
219 struct radeon_device *rdev;
220 struct drm_gem_object *gobj;
221};
222
223struct radeon_bo_list {
200 struct list_head list;
224 struct list_head list;
201 struct radeon_object *robj;
225 struct radeon_bo *bo;
202 uint64_t gpu_offset;
203 unsigned rdomain;
204 unsigned wdomain;
226 uint64_t gpu_offset;
227 unsigned rdomain;
228 unsigned wdomain;
205 uint32_t tiling_flags;
229 u32 tiling_flags;
206};
207
230};
231
208int radeon_object_init(struct radeon_device *rdev);
209void radeon_object_fini(struct radeon_device *rdev);
210int radeon_object_create(struct radeon_device *rdev,
211 struct drm_gem_object *gobj,
212 unsigned long size,
213 bool kernel,
214 uint32_t domain,
215 bool interruptible,
216 struct radeon_object **robj_ptr);
217int radeon_object_kmap(struct radeon_object *robj, void **ptr);
218void radeon_object_kunmap(struct radeon_object *robj);
219void radeon_object_unref(struct radeon_object **robj);
220int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
221 uint64_t *gpu_addr);
222void radeon_object_unpin(struct radeon_object *robj);
223int radeon_object_wait(struct radeon_object *robj);
224int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
225int radeon_object_evict_vram(struct radeon_device *rdev);
226int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
227void radeon_object_force_delete(struct radeon_device *rdev);
228void radeon_object_list_add_object(struct radeon_object_list *lobj,
229 struct list_head *head);
230int radeon_object_list_validate(struct list_head *head, void *fence);
231void radeon_object_list_unvalidate(struct list_head *head);
232void radeon_object_list_clean(struct list_head *head);
233int radeon_object_fbdev_mmap(struct radeon_object *robj,
234 struct vm_area_struct *vma);
235unsigned long radeon_object_size(struct radeon_object *robj);
236void radeon_object_clear_surface_reg(struct radeon_object *robj);
237int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
238 bool force_drop);
239void radeon_object_set_tiling_flags(struct radeon_object *robj,
240 uint32_t tiling_flags, uint32_t pitch);
241void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
242void radeon_bo_move_notify(struct ttm_buffer_object *bo,
243 struct ttm_mem_reg *mem);
244void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
245/*
246 * GEM objects.
247 */
248struct radeon_gem {
232/*
233 * GEM objects.
234 */
235struct radeon_gem {
236 struct mutex mutex;
249 struct list_head objects;
250};
251
252int radeon_gem_init(struct radeon_device *rdev);
253void radeon_gem_fini(struct radeon_device *rdev);
254int radeon_gem_object_create(struct radeon_device *rdev, int size,
237 struct list_head objects;
238};
239
240int radeon_gem_init(struct radeon_device *rdev);
241void radeon_gem_fini(struct radeon_device *rdev);
242int radeon_gem_object_create(struct radeon_device *rdev, int size,
255 int alignment, int initial_domain,
256 bool discardable, bool kernel,
257 bool interruptible,
258 struct drm_gem_object **obj);
243 int alignment, int initial_domain,
244 bool discardable, bool kernel,
245 struct drm_gem_object **obj);
259int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
260 uint64_t *gpu_addr);
261void radeon_gem_object_unpin(struct drm_gem_object *obj);
262
263
264/*
265 * GART structures, functions & helpers
266 */
267struct radeon_mc;
268
269struct radeon_gart_table_ram {
270 volatile uint32_t *ptr;
271};
272
273struct radeon_gart_table_vram {
246int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
247 uint64_t *gpu_addr);
248void radeon_gem_object_unpin(struct drm_gem_object *obj);
249
250
251/*
252 * GART structures, functions & helpers
253 */
254struct radeon_mc;
255
256struct radeon_gart_table_ram {
257 volatile uint32_t *ptr;
258};
259
260struct radeon_gart_table_vram {
274 struct radeon_object *robj;
261 struct radeon_bo *robj;
275 volatile uint32_t *ptr;
276};
277
278union radeon_gart_table {
279 struct radeon_gart_table_ram ram;
280 struct radeon_gart_table_vram vram;
281};
282

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374};
375
376/*
377 * locking -
378 * mutex protects scheduled_ibs, ready, alloc_bm
379 */
380struct radeon_ib_pool {
381 struct mutex mutex;
262 volatile uint32_t *ptr;
263};
264
265union radeon_gart_table {
266 struct radeon_gart_table_ram ram;
267 struct radeon_gart_table_vram vram;
268};
269

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361};
362
363/*
364 * locking -
365 * mutex protects scheduled_ibs, ready, alloc_bm
366 */
367struct radeon_ib_pool {
368 struct mutex mutex;
382 struct radeon_object *robj;
369 struct radeon_bo *robj;
383 struct list_head scheduled_ibs;
384 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
385 bool ready;
386 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
387};
388
389struct radeon_cp {
370 struct list_head scheduled_ibs;
371 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
372 bool ready;
373 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
374};
375
376struct radeon_cp {
390 struct radeon_object *ring_obj;
377 struct radeon_bo *ring_obj;
391 volatile uint32_t *ring;
392 unsigned rptr;
393 unsigned wptr;
394 unsigned wptr_old;
395 unsigned ring_size;
396 unsigned ring_free_dw;
397 int count_dw;
398 uint64_t gpu_addr;
399 uint32_t align_mask;
400 uint32_t ptr_mask;
401 struct mutex mutex;
402 bool ready;
403};
404
405/*
406 * R6xx+ IH ring
407 */
408struct r600_ih {
378 volatile uint32_t *ring;
379 unsigned rptr;
380 unsigned wptr;
381 unsigned wptr_old;
382 unsigned ring_size;
383 unsigned ring_free_dw;
384 int count_dw;
385 uint64_t gpu_addr;
386 uint32_t align_mask;
387 uint32_t ptr_mask;
388 struct mutex mutex;
389 bool ready;
390};
391
392/*
393 * R6xx+ IH ring
394 */
395struct r600_ih {
409 struct radeon_object *ring_obj;
396 struct radeon_bo *ring_obj;
410 volatile uint32_t *ring;
411 unsigned rptr;
412 unsigned wptr;
413 unsigned wptr_old;
414 unsigned ring_size;
415 uint64_t gpu_addr;
416 uint32_t align_mask;
417 uint32_t ptr_mask;
418 spinlock_t lock;
419 bool enabled;
420};
421
422struct r600_blit {
397 volatile uint32_t *ring;
398 unsigned rptr;
399 unsigned wptr;
400 unsigned wptr_old;
401 unsigned ring_size;
402 uint64_t gpu_addr;
403 uint32_t align_mask;
404 uint32_t ptr_mask;
405 spinlock_t lock;
406 bool enabled;
407};
408
409struct r600_blit {
423 struct radeon_object *shader_obj;
410 struct radeon_bo *shader_obj;
424 u64 shader_gpu_addr;
425 u32 vs_offset, ps_offset;
426 u32 state_offset;
427 u32 state_len;
428 u32 vb_used, vb_total;
429 struct radeon_ib *vb_ib;
430};
431

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445void radeon_ring_fini(struct radeon_device *rdev);
446
447
448/*
449 * CS.
450 */
451struct radeon_cs_reloc {
452 struct drm_gem_object *gobj;
411 u64 shader_gpu_addr;
412 u32 vs_offset, ps_offset;
413 u32 state_offset;
414 u32 state_len;
415 u32 vb_used, vb_total;
416 struct radeon_ib *vb_ib;
417};
418

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432void radeon_ring_fini(struct radeon_device *rdev);
433
434
435/*
436 * CS.
437 */
438struct radeon_cs_reloc {
439 struct drm_gem_object *gobj;
453 struct radeon_object *robj;
454 struct radeon_object_list lobj;
440 struct radeon_bo *robj;
441 struct radeon_bo_list lobj;
455 uint32_t handle;
456 uint32_t flags;
457};
458
459struct radeon_cs_chunk {
460 uint32_t chunk_id;
461 uint32_t length_dw;
462 int kpage_idx[2];

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542void radeon_agp_resume(struct radeon_device *rdev);
543void radeon_agp_fini(struct radeon_device *rdev);
544
545
546/*
547 * Writeback
548 */
549struct radeon_wb {
442 uint32_t handle;
443 uint32_t flags;
444};
445
446struct radeon_cs_chunk {
447 uint32_t chunk_id;
448 uint32_t length_dw;
449 int kpage_idx[2];

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529void radeon_agp_resume(struct radeon_device *rdev);
530void radeon_agp_fini(struct radeon_device *rdev);
531
532
533/*
534 * Writeback
535 */
536struct radeon_wb {
550 struct radeon_object *wb_obj;
537 struct radeon_bo *wb_obj;
551 volatile uint32_t *wb;
552 uint64_t gpu_addr;
553};
554
555/**
556 * struct radeon_pm - power management datas
557 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
558 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)

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767 enum radeon_pll_errata pll_errata;
768 int num_gb_pipes;
769 int num_z_pipes;
770 int disp_priority;
771 /* BIOS */
772 uint8_t *bios;
773 bool is_atom_bios;
774 uint16_t bios_header_start;
538 volatile uint32_t *wb;
539 uint64_t gpu_addr;
540};
541
542/**
543 * struct radeon_pm - power management datas
544 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
545 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)

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754 enum radeon_pll_errata pll_errata;
755 int num_gb_pipes;
756 int num_z_pipes;
757 int disp_priority;
758 /* BIOS */
759 uint8_t *bios;
760 bool is_atom_bios;
761 uint16_t bios_header_start;
775 struct radeon_object *stollen_vga_memory;
762 struct radeon_bo *stollen_vga_memory;
776 struct fb_info *fbdev_info;
763 struct fb_info *fbdev_info;
777 struct radeon_object *fbdev_robj;
764 struct radeon_bo *fbdev_rbo;
778 struct radeon_framebuffer *fbdev_rfb;
779 /* Register mmio */
780 resource_size_t rmmio_base;
781 resource_size_t rmmio_size;
782 void *rmmio;
783 radeon_rreg_t mc_rreg;
784 radeon_wreg_t mc_wreg;
785 radeon_rreg_t pll_rreg;

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847 if (reg < 0x10000)
848 writel(v, ((void __iomem *)rdev->rmmio) + reg);
849 else {
850 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
851 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
852 }
853}
854
765 struct radeon_framebuffer *fbdev_rfb;
766 /* Register mmio */
767 resource_size_t rmmio_base;
768 resource_size_t rmmio_size;
769 void *rmmio;
770 radeon_rreg_t mc_rreg;
771 radeon_wreg_t mc_wreg;
772 radeon_rreg_t pll_rreg;

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834 if (reg < 0x10000)
835 writel(v, ((void __iomem *)rdev->rmmio) + reg);
836 else {
837 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
838 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
839 }
840}
841
842/*
843 * Cast helper
844 */
845#define to_radeon_fence(p) ((struct radeon_fence *)(p))
855
856/*
857 * Registers read & write functions.
858 */
859#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
860#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
861#define RREG32(reg) r100_mm_rreg(rdev, (reg))
862#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))

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1041extern void r100_wb_fini(struct radeon_device *rdev);
1042extern int r100_wb_init(struct radeon_device *rdev);
1043extern void r100_hdp_reset(struct radeon_device *rdev);
1044extern int r100_rb2d_reset(struct radeon_device *rdev);
1045extern int r100_cp_reset(struct radeon_device *rdev);
1046extern void r100_vga_render_disable(struct radeon_device *rdev);
1047extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1048 struct radeon_cs_packet *pkt,
846
847/*
848 * Registers read & write functions.
849 */
850#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
851#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
852#define RREG32(reg) r100_mm_rreg(rdev, (reg))
853#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))

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1032extern void r100_wb_fini(struct radeon_device *rdev);
1033extern int r100_wb_init(struct radeon_device *rdev);
1034extern void r100_hdp_reset(struct radeon_device *rdev);
1035extern int r100_rb2d_reset(struct radeon_device *rdev);
1036extern int r100_cp_reset(struct radeon_device *rdev);
1037extern void r100_vga_render_disable(struct radeon_device *rdev);
1038extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1039 struct radeon_cs_packet *pkt,
1049 struct radeon_object *robj);
1040 struct radeon_bo *robj);
1050extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1051 struct radeon_cs_packet *pkt,
1052 const unsigned *auth, unsigned n,
1053 radeon_packet0_check_t check);
1054extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1055 struct radeon_cs_packet *pkt,
1056 unsigned idx);
1057extern void r100_enable_bm(struct radeon_device *rdev);

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1133extern int r600_init_microcode(struct radeon_device *rdev);
1134extern int r600_gpu_reset(struct radeon_device *rdev);
1135/* r600 irq */
1136extern int r600_irq_init(struct radeon_device *rdev);
1137extern void r600_irq_fini(struct radeon_device *rdev);
1138extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1139extern int r600_irq_set(struct radeon_device *rdev);
1140
1041extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1042 struct radeon_cs_packet *pkt,
1043 const unsigned *auth, unsigned n,
1044 radeon_packet0_check_t check);
1045extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1046 struct radeon_cs_packet *pkt,
1047 unsigned idx);
1048extern void r100_enable_bm(struct radeon_device *rdev);

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1124extern int r600_init_microcode(struct radeon_device *rdev);
1125extern int r600_gpu_reset(struct radeon_device *rdev);
1126/* r600 irq */
1127extern int r600_irq_init(struct radeon_device *rdev);
1128extern void r600_irq_fini(struct radeon_device *rdev);
1129extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1130extern int r600_irq_set(struct radeon_device *rdev);
1131
1132#include "radeon_object.h"
1133
1141#endif
1134#endif