r600.c (1614f8b17b8cc3ad143541d41569623d30dbc9ec) r600.c (4c7886791264f03428d5424befb1b96f08fc90f4)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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179 r600_pcie_gart_tlb_flush(rdev);
180 rdev->gart.ready = true;
181 return 0;
182}
183
184void r600_pcie_gart_disable(struct radeon_device *rdev)
185{
186 u32 tmp;
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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179 r600_pcie_gart_tlb_flush(rdev);
180 rdev->gart.ready = true;
181 return 0;
182}
183
184void r600_pcie_gart_disable(struct radeon_device *rdev)
185{
186 u32 tmp;
187 int i;
187 int i, r;
188
189 /* Disable all tables */
190 for (i = 0; i < 7; i++)
191 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
192
193 /* Disable L2 cache */
194 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
195 EFFECTIVE_L2_QUEUE_SIZE(7));

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207 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
208 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
209 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
210 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
211 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
212 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
213 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
214 if (rdev->gart.table.vram.robj) {
188
189 /* Disable all tables */
190 for (i = 0; i < 7; i++)
191 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
192
193 /* Disable L2 cache */
194 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
195 EFFECTIVE_L2_QUEUE_SIZE(7));

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207 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
208 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
209 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
210 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
211 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
212 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
213 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
214 if (rdev->gart.table.vram.robj) {
215 radeon_object_kunmap(rdev->gart.table.vram.robj);
216 radeon_object_unpin(rdev->gart.table.vram.robj);
215 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
216 if (likely(r == 0)) {
217 radeon_bo_kunmap(rdev->gart.table.vram.robj);
218 radeon_bo_unpin(rdev->gart.table.vram.robj);
219 radeon_bo_unreserve(rdev->gart.table.vram.robj);
220 }
217 }
218}
219
220void r600_pcie_gart_fini(struct radeon_device *rdev)
221{
222 r600_pcie_gart_disable(rdev);
223 radeon_gart_table_vram_free(rdev);
224 radeon_gart_fini(rdev);

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1431 r = -EINVAL;
1432 }
1433 radeon_scratch_free(rdev, scratch);
1434 return r;
1435}
1436
1437void r600_wb_disable(struct radeon_device *rdev)
1438{
221 }
222}
223
224void r600_pcie_gart_fini(struct radeon_device *rdev)
225{
226 r600_pcie_gart_disable(rdev);
227 radeon_gart_table_vram_free(rdev);
228 radeon_gart_fini(rdev);

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1435 r = -EINVAL;
1436 }
1437 radeon_scratch_free(rdev, scratch);
1438 return r;
1439}
1440
1441void r600_wb_disable(struct radeon_device *rdev)
1442{
1443 int r;
1444
1439 WREG32(SCRATCH_UMSK, 0);
1440 if (rdev->wb.wb_obj) {
1445 WREG32(SCRATCH_UMSK, 0);
1446 if (rdev->wb.wb_obj) {
1441 radeon_object_kunmap(rdev->wb.wb_obj);
1442 radeon_object_unpin(rdev->wb.wb_obj);
1447 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1448 if (unlikely(r != 0))
1449 return;
1450 radeon_bo_kunmap(rdev->wb.wb_obj);
1451 radeon_bo_unpin(rdev->wb.wb_obj);
1452 radeon_bo_unreserve(rdev->wb.wb_obj);
1443 }
1444}
1445
1446void r600_wb_fini(struct radeon_device *rdev)
1447{
1448 r600_wb_disable(rdev);
1449 if (rdev->wb.wb_obj) {
1453 }
1454}
1455
1456void r600_wb_fini(struct radeon_device *rdev)
1457{
1458 r600_wb_disable(rdev);
1459 if (rdev->wb.wb_obj) {
1450 radeon_object_unref(&rdev->wb.wb_obj);
1460 radeon_bo_unref(&rdev->wb.wb_obj);
1451 rdev->wb.wb = NULL;
1452 rdev->wb.wb_obj = NULL;
1453 }
1454}
1455
1456int r600_wb_enable(struct radeon_device *rdev)
1457{
1458 int r;
1459
1460 if (rdev->wb.wb_obj == NULL) {
1461 rdev->wb.wb = NULL;
1462 rdev->wb.wb_obj = NULL;
1463 }
1464}
1465
1466int r600_wb_enable(struct radeon_device *rdev)
1467{
1468 int r;
1469
1470 if (rdev->wb.wb_obj == NULL) {
1461 r = radeon_object_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1462 RADEON_GEM_DOMAIN_GTT, false, &rdev->wb.wb_obj);
1471 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1472 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
1463 if (r) {
1473 if (r) {
1464 dev_warn(rdev->dev, "failed to create WB buffer (%d).\n", r);
1474 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
1465 return r;
1466 }
1475 return r;
1476 }
1467 r = radeon_object_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1477 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1478 if (unlikely(r != 0)) {
1479 r600_wb_fini(rdev);
1480 return r;
1481 }
1482 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1468 &rdev->wb.gpu_addr);
1469 if (r) {
1483 &rdev->wb.gpu_addr);
1484 if (r) {
1470 dev_warn(rdev->dev, "failed to pin WB buffer (%d).\n", r);
1485 radeon_bo_unreserve(rdev->wb.wb_obj);
1486 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
1471 r600_wb_fini(rdev);
1472 return r;
1473 }
1487 r600_wb_fini(rdev);
1488 return r;
1489 }
1474 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1490 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1491 radeon_bo_unreserve(rdev->wb.wb_obj);
1475 if (r) {
1492 if (r) {
1476 dev_warn(rdev->dev, "failed to map WB buffer (%d).\n", r);
1493 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
1477 r600_wb_fini(rdev);
1478 return r;
1479 }
1480 }
1481 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1482 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1483 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1484 WREG32(SCRATCH_UMSK, 0xff);

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1558 r600_agp_enable(rdev);
1559 } else {
1560 r = r600_pcie_gart_enable(rdev);
1561 if (r)
1562 return r;
1563 }
1564 r600_gpu_init(rdev);
1565
1494 r600_wb_fini(rdev);
1495 return r;
1496 }
1497 }
1498 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1499 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1500 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1501 WREG32(SCRATCH_UMSK, 0xff);

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1575 r600_agp_enable(rdev);
1576 } else {
1577 r = r600_pcie_gart_enable(rdev);
1578 if (r)
1579 return r;
1580 }
1581 r600_gpu_init(rdev);
1582
1566 r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1567 &rdev->r600_blit.shader_gpu_addr);
1583 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1584 if (unlikely(r != 0))
1585 return r;
1586 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1587 &rdev->r600_blit.shader_gpu_addr);
1588 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1568 if (r) {
1589 if (r) {
1569 DRM_ERROR("failed to pin blit object %d\n", r);
1590 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
1570 return r;
1571 }
1572
1573 /* Enable IRQ */
1574 r = r600_irq_init(rdev);
1575 if (r) {
1576 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1577 radeon_irq_kms_fini(rdev);

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1634 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1635 return r;
1636 }
1637 return r;
1638}
1639
1640int r600_suspend(struct radeon_device *rdev)
1641{
1591 return r;
1592 }
1593
1594 /* Enable IRQ */
1595 r = r600_irq_init(rdev);
1596 if (r) {
1597 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1598 radeon_irq_kms_fini(rdev);

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1655 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1656 return r;
1657 }
1658 return r;
1659}
1660
1661int r600_suspend(struct radeon_device *rdev)
1662{
1663 int r;
1664
1642 /* FIXME: we should wait for ring to be empty */
1643 r600_cp_stop(rdev);
1644 rdev->cp.ready = false;
1645 r600_wb_disable(rdev);
1646 r600_pcie_gart_disable(rdev);
1647 /* unpin shaders bo */
1665 /* FIXME: we should wait for ring to be empty */
1666 r600_cp_stop(rdev);
1667 rdev->cp.ready = false;
1668 r600_wb_disable(rdev);
1669 r600_pcie_gart_disable(rdev);
1670 /* unpin shaders bo */
1648 radeon_object_unpin(rdev->r600_blit.shader_obj);
1671 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1672 if (unlikely(r != 0))
1673 return r;
1674 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1675 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1649 return 0;
1650}
1651
1652/* Plan is to move initialization in that function and use
1653 * helper function so that radeon_device_init pretty much
1654 * do nothing more than calling asic specific function. This
1655 * should also allow to remove a bunch of callback function
1656 * like vram_info.

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1705 /* Fence driver */
1706 r = radeon_fence_driver_init(rdev);
1707 if (r)
1708 return r;
1709 r = r600_mc_init(rdev);
1710 if (r)
1711 return r;
1712 /* Memory manager */
1676 return 0;
1677}
1678
1679/* Plan is to move initialization in that function and use
1680 * helper function so that radeon_device_init pretty much
1681 * do nothing more than calling asic specific function. This
1682 * should also allow to remove a bunch of callback function
1683 * like vram_info.

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1732 /* Fence driver */
1733 r = radeon_fence_driver_init(rdev);
1734 if (r)
1735 return r;
1736 r = r600_mc_init(rdev);
1737 if (r)
1738 return r;
1739 /* Memory manager */
1713 r = radeon_object_init(rdev);
1740 r = radeon_bo_init(rdev);
1714 if (r)
1715 return r;
1716
1717 r = radeon_irq_kms_init(rdev);
1718 if (r)
1719 return r;
1720
1721 rdev->cp.ring_obj = NULL;

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1777 radeon_ring_fini(rdev);
1778 r600_wb_fini(rdev);
1779 r600_pcie_gart_fini(rdev);
1780 radeon_gem_fini(rdev);
1781 radeon_fence_driver_fini(rdev);
1782 radeon_clocks_fini(rdev);
1783 if (rdev->flags & RADEON_IS_AGP)
1784 radeon_agp_fini(rdev);
1741 if (r)
1742 return r;
1743
1744 r = radeon_irq_kms_init(rdev);
1745 if (r)
1746 return r;
1747
1748 rdev->cp.ring_obj = NULL;

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1804 radeon_ring_fini(rdev);
1805 r600_wb_fini(rdev);
1806 r600_pcie_gart_fini(rdev);
1807 radeon_gem_fini(rdev);
1808 radeon_fence_driver_fini(rdev);
1809 radeon_clocks_fini(rdev);
1810 if (rdev->flags & RADEON_IS_AGP)
1811 radeon_agp_fini(rdev);
1785 radeon_object_fini(rdev);
1812 radeon_bo_fini(rdev);
1786 radeon_atombios_fini(rdev);
1787 kfree(rdev->bios);
1788 rdev->bios = NULL;
1789 radeon_dummy_page_fini(rdev);
1790}
1791
1792
1793/*

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1892
1893static int r600_ih_ring_alloc(struct radeon_device *rdev, unsigned ring_size)
1894{
1895 int r;
1896
1897 rdev->ih.ring_size = ring_size;
1898 /* Allocate ring buffer */
1899 if (rdev->ih.ring_obj == NULL) {
1813 radeon_atombios_fini(rdev);
1814 kfree(rdev->bios);
1815 rdev->bios = NULL;
1816 radeon_dummy_page_fini(rdev);
1817}
1818
1819
1820/*

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1919
1920static int r600_ih_ring_alloc(struct radeon_device *rdev, unsigned ring_size)
1921{
1922 int r;
1923
1924 rdev->ih.ring_size = ring_size;
1925 /* Allocate ring buffer */
1926 if (rdev->ih.ring_obj == NULL) {
1900 r = radeon_object_create(rdev, NULL, rdev->ih.ring_size,
1901 true,
1902 RADEON_GEM_DOMAIN_GTT,
1903 false,
1904 &rdev->ih.ring_obj);
1927 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
1928 true,
1929 RADEON_GEM_DOMAIN_GTT,
1930 &rdev->ih.ring_obj);
1905 if (r) {
1906 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
1907 return r;
1908 }
1931 if (r) {
1932 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
1933 return r;
1934 }
1909 r = radeon_object_pin(rdev->ih.ring_obj,
1910 RADEON_GEM_DOMAIN_GTT,
1911 &rdev->ih.gpu_addr);
1935 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
1936 if (unlikely(r != 0))
1937 return r;
1938 r = radeon_bo_pin(rdev->ih.ring_obj,
1939 RADEON_GEM_DOMAIN_GTT,
1940 &rdev->ih.gpu_addr);
1912 if (r) {
1941 if (r) {
1942 radeon_bo_unreserve(rdev->ih.ring_obj);
1913 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
1914 return r;
1915 }
1943 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
1944 return r;
1945 }
1916 r = radeon_object_kmap(rdev->ih.ring_obj,
1917 (void **)&rdev->ih.ring);
1946 r = radeon_bo_kmap(rdev->ih.ring_obj,
1947 (void **)&rdev->ih.ring);
1948 radeon_bo_unreserve(rdev->ih.ring_obj);
1918 if (r) {
1919 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
1920 return r;
1921 }
1922 }
1923 rdev->ih.ptr_mask = (rdev->cp.ring_size / 4) - 1;
1924 rdev->ih.rptr = 0;
1925
1926 return 0;
1927}
1928
1929static void r600_ih_ring_fini(struct radeon_device *rdev)
1930{
1949 if (r) {
1950 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
1951 return r;
1952 }
1953 }
1954 rdev->ih.ptr_mask = (rdev->cp.ring_size / 4) - 1;
1955 rdev->ih.rptr = 0;
1956
1957 return 0;
1958}
1959
1960static void r600_ih_ring_fini(struct radeon_device *rdev)
1961{
1962 int r;
1931 if (rdev->ih.ring_obj) {
1963 if (rdev->ih.ring_obj) {
1932 radeon_object_kunmap(rdev->ih.ring_obj);
1933 radeon_object_unpin(rdev->ih.ring_obj);
1934 radeon_object_unref(&rdev->ih.ring_obj);
1964 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
1965 if (likely(r == 0)) {
1966 radeon_bo_kunmap(rdev->ih.ring_obj);
1967 radeon_bo_unpin(rdev->ih.ring_obj);
1968 radeon_bo_unreserve(rdev->ih.ring_obj);
1969 }
1970 radeon_bo_unref(&rdev->ih.ring_obj);
1935 rdev->ih.ring = NULL;
1936 rdev->ih.ring_obj = NULL;
1937 }
1938}
1939
1940static void r600_rlc_stop(struct radeon_device *rdev)
1941{
1942

--- 429 unchanged lines hidden --- 		1971 rdev->ih.ring = NULL;
1972 rdev->ih.ring_obj = NULL;
1973 }
1974}
1975
1976static void r600_rlc_stop(struct radeon_device *rdev)
1977{
1978

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