r300.c (a2d07b7438f015a0349bc9af3c96a8164549bbc5) r300.c (90aca4d2740255bd130ea71a91530b9920c70abe)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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146 return 0;
147}
148
149void rv370_pcie_gart_disable(struct radeon_device *rdev)
150{
151 u32 tmp;
152 int r;
153
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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146 return 0;
147}
148
149void rv370_pcie_gart_disable(struct radeon_device *rdev)
150{
151 u32 tmp;
152 int r;
153
154 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
155 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
156 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
157 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
154 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
155 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
156 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
157 if (rdev->gart.table.vram.robj) {
158 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
159 if (likely(r == 0)) {
160 radeon_bo_kunmap(rdev->gart.table.vram.robj);
161 radeon_bo_unpin(rdev->gart.table.vram.robj);

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318 }
319 return -1;
320}
321
322void r300_gpu_init(struct radeon_device *rdev)
323{
324 uint32_t gb_tile_config, tmp;
325
158 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
159 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
160 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
161 if (rdev->gart.table.vram.robj) {
162 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
163 if (likely(r == 0)) {
164 radeon_bo_kunmap(rdev->gart.table.vram.robj);
165 radeon_bo_unpin(rdev->gart.table.vram.robj);

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322 }
323 return -1;
324}
325
326void r300_gpu_init(struct radeon_device *rdev)
327{
328 uint32_t gb_tile_config, tmp;
329
326 r100_hdp_reset(rdev);
327 /* FIXME: rv380 one pipes ? */
328 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
329 (rdev->family == CHIP_R350)) {
330 /* r300,r350 */
331 rdev->num_gb_pipes = 2;
332 } else {
333 /* rv350,rv370,rv380,r300 AD */
334 rdev->num_gb_pipes = 1;

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371 if (r300_mc_wait_for_idle(rdev)) {
372 printk(KERN_WARNING "Failed to wait MC idle while "
373 "programming pipes. Bad things might happen.\n");
374 }
375 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
376 rdev->num_gb_pipes, rdev->num_z_pipes);
377}
378
330 /* FIXME: rv380 one pipes ? */
331 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
332 (rdev->family == CHIP_R350)) {
333 /* r300,r350 */
334 rdev->num_gb_pipes = 2;
335 } else {
336 /* rv350,rv370,rv380,r300 AD */
337 rdev->num_gb_pipes = 1;

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374 if (r300_mc_wait_for_idle(rdev)) {
375 printk(KERN_WARNING "Failed to wait MC idle while "
376 "programming pipes. Bad things might happen.\n");
377 }
378 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
379 rdev->num_gb_pipes, rdev->num_z_pipes);
380}
381
379int r300_ga_reset(struct radeon_device *rdev)
380{
381 uint32_t tmp;
382 bool reinit_cp;
383 int i;
384
385 reinit_cp = rdev->cp.ready;
386 rdev->cp.ready = false;
387 for (i = 0; i < rdev->usec_timeout; i++) {
388 WREG32(RADEON_CP_CSQ_MODE, 0);
389 WREG32(RADEON_CP_CSQ_CNTL, 0);
390 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
391 (void)RREG32(RADEON_RBBM_SOFT_RESET);
392 udelay(200);
393 WREG32(RADEON_RBBM_SOFT_RESET, 0);
394 /* Wait to prevent race in RBBM_STATUS */
395 mdelay(1);
396 tmp = RREG32(RADEON_RBBM_STATUS);
397 if (tmp & ((1 << 20) | (1 << 26))) {
398 DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
399 /* GA still busy soft reset it */
400 WREG32(0x429C, 0x200);
401 WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
402 WREG32(R300_RE_SCISSORS_TL, 0);
403 WREG32(R300_RE_SCISSORS_BR, 0);
404 WREG32(0x24AC, 0);
405 }
406 /* Wait to prevent race in RBBM_STATUS */
407 mdelay(1);
408 tmp = RREG32(RADEON_RBBM_STATUS);
409 if (!(tmp & ((1 << 20) | (1 << 26)))) {
410 break;
411 }
412 }
413 for (i = 0; i < rdev->usec_timeout; i++) {
414 tmp = RREG32(RADEON_RBBM_STATUS);
415 if (!(tmp & ((1 << 20) | (1 << 26)))) {
416 DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
417 tmp);
418 if (reinit_cp) {
419 return r100_cp_init(rdev, rdev->cp.ring_size);
420 }
421 return 0;
422 }
423 DRM_UDELAY(1);
424 }
425 tmp = RREG32(RADEON_RBBM_STATUS);
426 DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
427 return -1;
428}
429
430bool r300_gpu_is_lockup(struct radeon_device *rdev)
431{
432 u32 rbbm_status;
433 int r;
434
435 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
436 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
437 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);

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446 radeon_ring_unlock_commit(rdev);
447 }
448 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
449 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
450}
451
452int r300_asic_reset(struct radeon_device *rdev)
453{
382bool r300_gpu_is_lockup(struct radeon_device *rdev)
383{
384 u32 rbbm_status;
385 int r;
386
387 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
388 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
389 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);

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398 radeon_ring_unlock_commit(rdev);
399 }
400 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
401 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
402}
403
404int r300_asic_reset(struct radeon_device *rdev)
405{
454 uint32_t status;
406 struct r100_mc_save save;
407 u32 status, tmp;
455
408
456 /* reset order likely matter */
457 status = RREG32(RADEON_RBBM_STATUS);
458 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
459 /* reset HDP */
460 r100_hdp_reset(rdev);
461 /* reset rb2d */
462 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
463 r100_rb2d_reset(rdev);
409 r100_mc_stop(rdev, &save);
410 status = RREG32(R_000E40_RBBM_STATUS);
411 if (!G_000E40_GUI_ACTIVE(status)) {
412 return 0;
464 }
413 }
465 /* reset GA */
466 if (status & ((1 << 20) | (1 << 26))) {
467 r300_ga_reset(rdev);
468 }
469 /* reset CP */
470 status = RREG32(RADEON_RBBM_STATUS);
471 if (status & (1 << 16)) {
472 r100_cp_reset(rdev);
473 }
414 status = RREG32(R_000E40_RBBM_STATUS);
415 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
416 /* stop CP */
417 WREG32(RADEON_CP_CSQ_CNTL, 0);
418 tmp = RREG32(RADEON_CP_RB_CNTL);
419 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
420 WREG32(RADEON_CP_RB_RPTR_WR, 0);
421 WREG32(RADEON_CP_RB_WPTR, 0);
422 WREG32(RADEON_CP_RB_CNTL, tmp);
423 /* save PCI state */
424 pci_save_state(rdev->pdev);
425 /* disable bus mastering */
426 r100_bm_disable(rdev);
427 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
428 S_0000F0_SOFT_RESET_GA(1));
429 RREG32(R_0000F0_RBBM_SOFT_RESET);
430 mdelay(500);
431 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
432 mdelay(1);
433 status = RREG32(R_000E40_RBBM_STATUS);
434 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
435 /* resetting the CP seems to be problematic sometimes it end up
436 * hard locking the computer, but it's necessary for successfull
437 * reset more test & playing is needed on R3XX/R4XX to find a
438 * reliable (if any solution)
439 */
440 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
441 RREG32(R_0000F0_RBBM_SOFT_RESET);
442 mdelay(500);
443 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
444 mdelay(1);
445 status = RREG32(R_000E40_RBBM_STATUS);
446 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
447 /* reset MC */
448 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
449 RREG32(R_0000F0_RBBM_SOFT_RESET);
450 mdelay(500);
451 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
452 mdelay(1);
453 status = RREG32(R_000E40_RBBM_STATUS);
454 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
455 /* restore PCI & busmastering */
456 pci_restore_state(rdev->pdev);
457 r100_enable_bm(rdev);
474 /* Check if GPU is idle */
458 /* Check if GPU is idle */
475 status = RREG32(RADEON_RBBM_STATUS);
476 if (status & RADEON_RBBM_ACTIVE) {
477 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
459 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
460 dev_err(rdev->dev, "failed to reset GPU\n");
461 rdev->gpu_lockup = true;
478 return -1;
479 }
462 return -1;
463 }
480 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
464 r100_mc_resume(rdev, &save);
465 dev_info(rdev->dev, "GPU reset succeed\n");
481 return 0;
482}
483
466 return 0;
467}
468
484
485/*
486 * r300,r350,rv350,rv380 VRAM info
487 */
488void r300_mc_init(struct radeon_device *rdev)
489{
490 u64 base;
491 u32 tmp;
492

--- 978 unchanged lines hidden --- 		469/*
470 * r300,r350,rv350,rv380 VRAM info
471 */
472void r300_mc_init(struct radeon_device *rdev)
473{
474 u64 base;
475 u32 tmp;
476

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