r300.c (50f153036c9d9e4ae1768d5ca9c2ad4184f7a0b7) r300.c (f779b3e513478218cbaaaa0a506d7801cab6fd14)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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28#include <linux/seq_file.h>
29#include "drmP.h"
30#include "drm.h"
31#include "radeon_reg.h"
32#include "radeon.h"
33#include "radeon_drm.h"
34#include "radeon_share.h"
35
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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28#include <linux/seq_file.h>
29#include "drmP.h"
30#include "drm.h"
31#include "radeon_reg.h"
32#include "radeon.h"
33#include "radeon_drm.h"
34#include "radeon_share.h"
35
36#include "r300_reg_safe.h"
37
38/* r300,r350,rv350,rv370,rv380 depends on : */
39void r100_hdp_reset(struct radeon_device *rdev);
40int r100_cp_reset(struct radeon_device *rdev);
41int r100_rb2d_reset(struct radeon_device *rdev);
42int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
43int r100_pci_gart_enable(struct radeon_device *rdev);
44void r100_pci_gart_disable(struct radeon_device *rdev);
45void r100_mc_setup(struct radeon_device *rdev);

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445 /* FIXME: rv380 one pipes ? */
446 if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
447 /* r300,r350 */
448 rdev->num_gb_pipes = 2;
449 } else {
450 /* rv350,rv370,rv380 */
451 rdev->num_gb_pipes = 1;
452 }
36/* r300,r350,rv350,rv370,rv380 depends on : */
37void r100_hdp_reset(struct radeon_device *rdev);
38int r100_cp_reset(struct radeon_device *rdev);
39int r100_rb2d_reset(struct radeon_device *rdev);
40int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
41int r100_pci_gart_enable(struct radeon_device *rdev);
42void r100_pci_gart_disable(struct radeon_device *rdev);
43void r100_mc_setup(struct radeon_device *rdev);

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443 /* FIXME: rv380 one pipes ? */
444 if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
445 /* r300,r350 */
446 rdev->num_gb_pipes = 2;
447 } else {
448 /* rv350,rv370,rv380 */
449 rdev->num_gb_pipes = 1;
450 }
451 rdev->num_z_pipes = 1;
453 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
454 switch (rdev->num_gb_pipes) {
455 case 2:
456 gb_tile_config |= R300_PIPE_COUNT_R300;
457 break;
458 case 3:
459 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
460 break;

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483 if (r100_gui_wait_for_idle(rdev)) {
484 printk(KERN_WARNING "Failed to wait GUI idle while "
485 "programming pipes. Bad things might happen.\n");
486 }
487 if (r300_mc_wait_for_idle(rdev)) {
488 printk(KERN_WARNING "Failed to wait MC idle while "
489 "programming pipes. Bad things might happen.\n");
490 }
452 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
453 switch (rdev->num_gb_pipes) {
454 case 2:
455 gb_tile_config |= R300_PIPE_COUNT_R300;
456 break;
457 case 3:
458 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
459 break;

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482 if (r100_gui_wait_for_idle(rdev)) {
483 printk(KERN_WARNING "Failed to wait GUI idle while "
484 "programming pipes. Bad things might happen.\n");
485 }
486 if (r300_mc_wait_for_idle(rdev)) {
487 printk(KERN_WARNING "Failed to wait MC idle while "
488 "programming pipes. Bad things might happen.\n");
489 }
491 DRM_INFO("radeon: %d pipes initialized.\n", rdev->num_gb_pipes);
490 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
491 rdev->num_gb_pipes, rdev->num_z_pipes);
492}
493
494int r300_ga_reset(struct radeon_device *rdev)
495{
496 uint32_t tmp;
497 bool reinit_cp;
498 int i;
499

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950 track->textures[i].robj = NULL;
951 /* CS IB emission code makes sure texture unit are disabled */
952 track->textures[i].enabled = false;
953 track->textures[i].roundup_w = true;
954 track->textures[i].roundup_h = true;
955 }
956}
957
492}
493
494int r300_ga_reset(struct radeon_device *rdev)
495{
496 uint32_t tmp;
497 bool reinit_cp;
498 int i;
499

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950 track->textures[i].robj = NULL;
951 /* CS IB emission code makes sure texture unit are disabled */
952 track->textures[i].enabled = false;
953 track->textures[i].roundup_w = true;
954 track->textures[i].roundup_h = true;
955 }
956}
957
958static const unsigned r300_reg_safe_bm[159] = {
959 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
960 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
961 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
962 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
963 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
964 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
965 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
966 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
967 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
968 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
969 0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF,
970 0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF,
971 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
972 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
973 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F,
974 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
975 0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000,
976 0xF0000078, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF,
977 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
978 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
979 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
980 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
981 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
982 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
983 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
984 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
985 0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
986 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
987 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
988 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
989 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
990 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
991 0xFFFFFC78, 0xFFFFFFFF, 0xFFFFFFFE, 0xFFFFFFFF,
992 0x38FF8F50, 0xFFF88082, 0xF000000C, 0xFAE009FF,
993 0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
994 0x00000000, 0x0000C100, 0x00000000, 0x00000000,
995 0x00000000, 0x00000000, 0x00000000, 0x00000000,
996 0x00000000, 0xFFFF0000, 0xFFFFFFFF, 0xFF80FFFF,
997 0x00000000, 0x00000000, 0x00000000, 0x00000000,
998 0x0003FC01, 0xFFFFFFF8, 0xFE800B19,
999};
1000
958static int r300_packet0_check(struct radeon_cs_parser *p,
959 struct radeon_cs_packet *pkt,
960 unsigned idx, unsigned reg)
961{
962 struct radeon_cs_chunk *ib_chunk;
963 struct radeon_cs_reloc *reloc;
964 struct r300_cs_track *track;
965 volatile uint32_t *ib;

--- 582 unchanged lines hidden --- 		1001static int r300_packet0_check(struct radeon_cs_parser *p,
1002 struct radeon_cs_packet *pkt,
1003 unsigned idx, unsigned reg)
1004{
1005 struct radeon_cs_chunk *ib_chunk;
1006 struct radeon_cs_reloc *reloc;
1007 struct r300_cs_track *track;
1008 volatile uint32_t *ib;

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