r200.c (8b3f6af86378d0a10ca2f1ded1da124aef13b62c) r200.c (513bcb4655e68706594e45dfa1d4b181500110ba)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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91 }
92 return vtx_size;
93}
94
95int r200_packet0_check(struct radeon_cs_parser *p,
96 struct radeon_cs_packet *pkt,
97 unsigned idx, unsigned reg)
98{
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 82 unchanged lines hidden (view full) ---

91 }
92 return vtx_size;
93}
94
95int r200_packet0_check(struct radeon_cs_parser *p,
96 struct radeon_cs_packet *pkt,
97 unsigned idx, unsigned reg)
98{
99 struct radeon_cs_chunk *ib_chunk;
100 struct radeon_cs_reloc *reloc;
101 struct r100_cs_track *track;
102 volatile uint32_t *ib;
103 uint32_t tmp;
104 int r;
105 int i;
106 int face;
107 u32 tile_flags = 0;
99 struct radeon_cs_reloc *reloc;
100 struct r100_cs_track *track;
101 volatile uint32_t *ib;
102 uint32_t tmp;
103 int r;
104 int i;
105 int face;
106 u32 tile_flags = 0;
107 u32 idx_value;
108
109 ib = p->ib->ptr;
108
109 ib = p->ib->ptr;
110 ib_chunk = &p->chunks[p->chunk_ib_idx];
111 track = (struct r100_cs_track *)p->track;
110 track = (struct r100_cs_track *)p->track;
112
111 idx_value = radeon_get_ib_value(p, idx);
113 switch (reg) {
114 case RADEON_CRTC_GUI_TRIG_VLINE:
115 r = r100_cs_packet_parse_vline(p);
116 if (r) {
117 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
118 idx, reg);
119 r100_cs_dump_packet(p, pkt);
120 return r;

--- 11 unchanged lines hidden (view full) ---

132 r = r100_cs_packet_next_reloc(p, &reloc);
133 if (r) {
134 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
135 idx, reg);
136 r100_cs_dump_packet(p, pkt);
137 return r;
138 }
139 track->zb.robj = reloc->robj;
112 switch (reg) {
113 case RADEON_CRTC_GUI_TRIG_VLINE:
114 r = r100_cs_packet_parse_vline(p);
115 if (r) {
116 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
117 idx, reg);
118 r100_cs_dump_packet(p, pkt);
119 return r;

--- 11 unchanged lines hidden (view full) ---

131 r = r100_cs_packet_next_reloc(p, &reloc);
132 if (r) {
133 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
134 idx, reg);
135 r100_cs_dump_packet(p, pkt);
136 return r;
137 }
138 track->zb.robj = reloc->robj;
140 track->zb.offset = ib_chunk->kdata[idx];
141 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
139 track->zb.offset = idx_value;
140 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
142 break;
143 case RADEON_RB3D_COLOROFFSET:
144 r = r100_cs_packet_next_reloc(p, &reloc);
145 if (r) {
146 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
147 idx, reg);
148 r100_cs_dump_packet(p, pkt);
149 return r;
150 }
151 track->cb[0].robj = reloc->robj;
141 break;
142 case RADEON_RB3D_COLOROFFSET:
143 r = r100_cs_packet_next_reloc(p, &reloc);
144 if (r) {
145 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
146 idx, reg);
147 r100_cs_dump_packet(p, pkt);
148 return r;
149 }
150 track->cb[0].robj = reloc->robj;
152 track->cb[0].offset = ib_chunk->kdata[idx];
153 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
151 track->cb[0].offset = idx_value;
152 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
154 break;
155 case R200_PP_TXOFFSET_0:
156 case R200_PP_TXOFFSET_1:
157 case R200_PP_TXOFFSET_2:
158 case R200_PP_TXOFFSET_3:
159 case R200_PP_TXOFFSET_4:
160 case R200_PP_TXOFFSET_5:
161 i = (reg - R200_PP_TXOFFSET_0) / 24;
162 r = r100_cs_packet_next_reloc(p, &reloc);
163 if (r) {
164 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
165 idx, reg);
166 r100_cs_dump_packet(p, pkt);
167 return r;
168 }
153 break;
154 case R200_PP_TXOFFSET_0:
155 case R200_PP_TXOFFSET_1:
156 case R200_PP_TXOFFSET_2:
157 case R200_PP_TXOFFSET_3:
158 case R200_PP_TXOFFSET_4:
159 case R200_PP_TXOFFSET_5:
160 i = (reg - R200_PP_TXOFFSET_0) / 24;
161 r = r100_cs_packet_next_reloc(p, &reloc);
162 if (r) {
163 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
164 idx, reg);
165 r100_cs_dump_packet(p, pkt);
166 return r;
167 }
169 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
168 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
170 track->textures[i].robj = reloc->robj;
171 break;
172 case R200_PP_CUBIC_OFFSET_F1_0:
173 case R200_PP_CUBIC_OFFSET_F2_0:
174 case R200_PP_CUBIC_OFFSET_F3_0:
175 case R200_PP_CUBIC_OFFSET_F4_0:
176 case R200_PP_CUBIC_OFFSET_F5_0:
177 case R200_PP_CUBIC_OFFSET_F1_1:

--- 25 unchanged lines hidden (view full) ---

203 face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4;
204 r = r100_cs_packet_next_reloc(p, &reloc);
205 if (r) {
206 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
207 idx, reg);
208 r100_cs_dump_packet(p, pkt);
209 return r;
210 }
169 track->textures[i].robj = reloc->robj;
170 break;
171 case R200_PP_CUBIC_OFFSET_F1_0:
172 case R200_PP_CUBIC_OFFSET_F2_0:
173 case R200_PP_CUBIC_OFFSET_F3_0:
174 case R200_PP_CUBIC_OFFSET_F4_0:
175 case R200_PP_CUBIC_OFFSET_F5_0:
176 case R200_PP_CUBIC_OFFSET_F1_1:

--- 25 unchanged lines hidden (view full) ---

202 face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4;
203 r = r100_cs_packet_next_reloc(p, &reloc);
204 if (r) {
205 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
206 idx, reg);
207 r100_cs_dump_packet(p, pkt);
208 return r;
209 }
211 track->textures[i].cube_info[face - 1].offset = ib_chunk->kdata[idx];
212 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
210 track->textures[i].cube_info[face - 1].offset = idx_value;
211 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
213 track->textures[i].cube_info[face - 1].robj = reloc->robj;
214 break;
215 case RADEON_RE_WIDTH_HEIGHT:
212 track->textures[i].cube_info[face - 1].robj = reloc->robj;
213 break;
214 case RADEON_RE_WIDTH_HEIGHT:
216 track->maxy = ((ib_chunk->kdata[idx] >> 16) & 0x7FF);
215 track->maxy = ((idx_value >> 16) & 0x7FF);
217 break;
218 case RADEON_RB3D_COLORPITCH:
219 r = r100_cs_packet_next_reloc(p, &reloc);
220 if (r) {
221 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
222 idx, reg);
223 r100_cs_dump_packet(p, pkt);
224 return r;
225 }
226
227 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
228 tile_flags |= RADEON_COLOR_TILE_ENABLE;
229 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
230 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
231
216 break;
217 case RADEON_RB3D_COLORPITCH:
218 r = r100_cs_packet_next_reloc(p, &reloc);
219 if (r) {
220 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
221 idx, reg);
222 r100_cs_dump_packet(p, pkt);
223 return r;
224 }
225
226 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
227 tile_flags |= RADEON_COLOR_TILE_ENABLE;
228 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
229 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
230
232 tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
231 tmp = idx_value & ~(0x7 << 16);
233 tmp |= tile_flags;
234 ib[idx] = tmp;
235
232 tmp |= tile_flags;
233 ib[idx] = tmp;
234
236 track->cb[0].pitch = ib_chunk->kdata[idx] & RADEON_COLORPITCH_MASK;
235 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
237 break;
238 case RADEON_RB3D_DEPTHPITCH:
236 break;
237 case RADEON_RB3D_DEPTHPITCH:
239 track->zb.pitch = ib_chunk->kdata[idx] & RADEON_DEPTHPITCH_MASK;
238 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
240 break;
241 case RADEON_RB3D_CNTL:
239 break;
240 case RADEON_RB3D_CNTL:
242 switch ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
241 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
243 case 7:
244 case 8:
245 case 9:
246 case 11:
247 case 12:
248 track->cb[0].cpp = 1;
249 break;
250 case 3:
251 case 4:
252 case 15:
253 track->cb[0].cpp = 2;
254 break;
255 case 6:
256 track->cb[0].cpp = 4;
257 break;
258 default:
259 DRM_ERROR("Invalid color buffer format (%d) !\n",
242 case 7:
243 case 8:
244 case 9:
245 case 11:
246 case 12:
247 track->cb[0].cpp = 1;
248 break;
249 case 3:
250 case 4:
251 case 15:
252 track->cb[0].cpp = 2;
253 break;
254 case 6:
255 track->cb[0].cpp = 4;
256 break;
257 default:
258 DRM_ERROR("Invalid color buffer format (%d) !\n",
260 ((ib_chunk->kdata[idx] >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
259 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
261 return -EINVAL;
262 }
260 return -EINVAL;
261 }
263 if (ib_chunk->kdata[idx] & RADEON_DEPTHXY_OFFSET_ENABLE) {
262 if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) {
264 DRM_ERROR("No support for depth xy offset in kms\n");
265 return -EINVAL;
266 }
267
263 DRM_ERROR("No support for depth xy offset in kms\n");
264 return -EINVAL;
265 }
266
268 track->z_enabled = !!(ib_chunk->kdata[idx] & RADEON_Z_ENABLE);
267 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
269 break;
270 case RADEON_RB3D_ZSTENCILCNTL:
268 break;
269 case RADEON_RB3D_ZSTENCILCNTL:
271 switch (ib_chunk->kdata[idx] & 0xf) {
270 switch (idx_value & 0xf) {
272 case 0:
273 track->zb.cpp = 2;
274 break;
275 case 2:
276 case 3:
277 case 4:
278 case 5:
279 case 9:

--- 7 unchanged lines hidden (view full) ---

287 case RADEON_RB3D_ZPASS_ADDR:
288 r = r100_cs_packet_next_reloc(p, &reloc);
289 if (r) {
290 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
291 idx, reg);
292 r100_cs_dump_packet(p, pkt);
293 return r;
294 }
271 case 0:
272 track->zb.cpp = 2;
273 break;
274 case 2:
275 case 3:
276 case 4:
277 case 5:
278 case 9:

--- 7 unchanged lines hidden (view full) ---

286 case RADEON_RB3D_ZPASS_ADDR:
287 r = r100_cs_packet_next_reloc(p, &reloc);
288 if (r) {
289 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
290 idx, reg);
291 r100_cs_dump_packet(p, pkt);
292 return r;
293 }
295 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
294 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
296 break;
297 case RADEON_PP_CNTL:
298 {
295 break;
296 case RADEON_PP_CNTL:
297 {
299 uint32_t temp = ib_chunk->kdata[idx] >> 4;
298 uint32_t temp = idx_value >> 4;
300 for (i = 0; i < track->num_texture; i++)
301 track->textures[i].enabled = !!(temp & (1 << i));
302 }
303 break;
304 case RADEON_SE_VF_CNTL:
299 for (i = 0; i < track->num_texture; i++)
300 track->textures[i].enabled = !!(temp & (1 << i));
301 }
302 break;
303 case RADEON_SE_VF_CNTL:
305 track->vap_vf_cntl = ib_chunk->kdata[idx];
304 track->vap_vf_cntl = idx_value;
306 break;
307 case 0x210c:
308 /* VAP_VF_MAX_VTX_INDX */
305 break;
306 case 0x210c:
307 /* VAP_VF_MAX_VTX_INDX */
309 track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL;
308 track->max_indx = idx_value & 0x00FFFFFFUL;
310 break;
311 case R200_SE_VTX_FMT_0:
309 break;
310 case R200_SE_VTX_FMT_0:
312 track->vtx_size = r200_get_vtx_size_0(ib_chunk->kdata[idx]);
311 track->vtx_size = r200_get_vtx_size_0(idx_value);
313 break;
314 case R200_SE_VTX_FMT_1:
312 break;
313 case R200_SE_VTX_FMT_1:
315 track->vtx_size += r200_get_vtx_size_1(ib_chunk->kdata[idx]);
314 track->vtx_size += r200_get_vtx_size_1(idx_value);
316 break;
317 case R200_PP_TXSIZE_0:
318 case R200_PP_TXSIZE_1:
319 case R200_PP_TXSIZE_2:
320 case R200_PP_TXSIZE_3:
321 case R200_PP_TXSIZE_4:
322 case R200_PP_TXSIZE_5:
323 i = (reg - R200_PP_TXSIZE_0) / 32;
315 break;
316 case R200_PP_TXSIZE_0:
317 case R200_PP_TXSIZE_1:
318 case R200_PP_TXSIZE_2:
319 case R200_PP_TXSIZE_3:
320 case R200_PP_TXSIZE_4:
321 case R200_PP_TXSIZE_5:
322 i = (reg - R200_PP_TXSIZE_0) / 32;
324 track->textures[i].width = (ib_chunk->kdata[idx] & RADEON_TEX_USIZE_MASK) + 1;
325 track->textures[i].height = ((ib_chunk->kdata[idx] & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
323 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
324 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
326 break;
327 case R200_PP_TXPITCH_0:
328 case R200_PP_TXPITCH_1:
329 case R200_PP_TXPITCH_2:
330 case R200_PP_TXPITCH_3:
331 case R200_PP_TXPITCH_4:
332 case R200_PP_TXPITCH_5:
333 i = (reg - R200_PP_TXPITCH_0) / 32;
325 break;
326 case R200_PP_TXPITCH_0:
327 case R200_PP_TXPITCH_1:
328 case R200_PP_TXPITCH_2:
329 case R200_PP_TXPITCH_3:
330 case R200_PP_TXPITCH_4:
331 case R200_PP_TXPITCH_5:
332 i = (reg - R200_PP_TXPITCH_0) / 32;
334 track->textures[i].pitch = ib_chunk->kdata[idx] + 32;
333 track->textures[i].pitch = idx_value + 32;
335 break;
336 case R200_PP_TXFILTER_0:
337 case R200_PP_TXFILTER_1:
338 case R200_PP_TXFILTER_2:
339 case R200_PP_TXFILTER_3:
340 case R200_PP_TXFILTER_4:
341 case R200_PP_TXFILTER_5:
342 i = (reg - R200_PP_TXFILTER_0) / 32;
334 break;
335 case R200_PP_TXFILTER_0:
336 case R200_PP_TXFILTER_1:
337 case R200_PP_TXFILTER_2:
338 case R200_PP_TXFILTER_3:
339 case R200_PP_TXFILTER_4:
340 case R200_PP_TXFILTER_5:
341 i = (reg - R200_PP_TXFILTER_0) / 32;
343 track->textures[i].num_levels = ((ib_chunk->kdata[idx] & R200_MAX_MIP_LEVEL_MASK)
342 track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK)
344 >> R200_MAX_MIP_LEVEL_SHIFT);
343 >> R200_MAX_MIP_LEVEL_SHIFT);
345 tmp = (ib_chunk->kdata[idx] >> 23) & 0x7;
344 tmp = (idx_value >> 23) & 0x7;
346 if (tmp == 2 || tmp == 6)
347 track->textures[i].roundup_w = false;
345 if (tmp == 2 || tmp == 6)
346 track->textures[i].roundup_w = false;
348 tmp = (ib_chunk->kdata[idx] >> 27) & 0x7;
347 tmp = (idx_value >> 27) & 0x7;
349 if (tmp == 2 || tmp == 6)
350 track->textures[i].roundup_h = false;
351 break;
352 case R200_PP_TXMULTI_CTL_0:
353 case R200_PP_TXMULTI_CTL_1:
354 case R200_PP_TXMULTI_CTL_2:
355 case R200_PP_TXMULTI_CTL_3:
356 case R200_PP_TXMULTI_CTL_4:
357 case R200_PP_TXMULTI_CTL_5:
358 i = (reg - R200_PP_TXMULTI_CTL_0) / 32;
359 break;
360 case R200_PP_TXFORMAT_X_0:
361 case R200_PP_TXFORMAT_X_1:
362 case R200_PP_TXFORMAT_X_2:
363 case R200_PP_TXFORMAT_X_3:
364 case R200_PP_TXFORMAT_X_4:
365 case R200_PP_TXFORMAT_X_5:
366 i = (reg - R200_PP_TXFORMAT_X_0) / 32;
348 if (tmp == 2 || tmp == 6)
349 track->textures[i].roundup_h = false;
350 break;
351 case R200_PP_TXMULTI_CTL_0:
352 case R200_PP_TXMULTI_CTL_1:
353 case R200_PP_TXMULTI_CTL_2:
354 case R200_PP_TXMULTI_CTL_3:
355 case R200_PP_TXMULTI_CTL_4:
356 case R200_PP_TXMULTI_CTL_5:
357 i = (reg - R200_PP_TXMULTI_CTL_0) / 32;
358 break;
359 case R200_PP_TXFORMAT_X_0:
360 case R200_PP_TXFORMAT_X_1:
361 case R200_PP_TXFORMAT_X_2:
362 case R200_PP_TXFORMAT_X_3:
363 case R200_PP_TXFORMAT_X_4:
364 case R200_PP_TXFORMAT_X_5:
365 i = (reg - R200_PP_TXFORMAT_X_0) / 32;
367 track->textures[i].txdepth = ib_chunk->kdata[idx] & 0x7;
368 tmp = (ib_chunk->kdata[idx] >> 16) & 0x3;
366 track->textures[i].txdepth = idx_value & 0x7;
367 tmp = (idx_value >> 16) & 0x3;
369 /* 2D, 3D, CUBE */
370 switch (tmp) {
371 case 0:
372 case 5:
373 case 6:
374 case 7:
375 track->textures[i].tex_coord_type = 0;
376 break;

--- 7 unchanged lines hidden (view full) ---

384 break;
385 case R200_PP_TXFORMAT_0:
386 case R200_PP_TXFORMAT_1:
387 case R200_PP_TXFORMAT_2:
388 case R200_PP_TXFORMAT_3:
389 case R200_PP_TXFORMAT_4:
390 case R200_PP_TXFORMAT_5:
391 i = (reg - R200_PP_TXFORMAT_0) / 32;
368 /* 2D, 3D, CUBE */
369 switch (tmp) {
370 case 0:
371 case 5:
372 case 6:
373 case 7:
374 track->textures[i].tex_coord_type = 0;
375 break;

--- 7 unchanged lines hidden (view full) ---

383 break;
384 case R200_PP_TXFORMAT_0:
385 case R200_PP_TXFORMAT_1:
386 case R200_PP_TXFORMAT_2:
387 case R200_PP_TXFORMAT_3:
388 case R200_PP_TXFORMAT_4:
389 case R200_PP_TXFORMAT_5:
390 i = (reg - R200_PP_TXFORMAT_0) / 32;
392 if (ib_chunk->kdata[idx] & R200_TXFORMAT_NON_POWER2) {
391 if (idx_value & R200_TXFORMAT_NON_POWER2) {
393 track->textures[i].use_pitch = 1;
394 } else {
395 track->textures[i].use_pitch = 0;
392 track->textures[i].use_pitch = 1;
393 } else {
394 track->textures[i].use_pitch = 0;
396 track->textures[i].width = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
397 track->textures[i].height = 1 << ((ib_chunk->kdata[idx] >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
395 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
396 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
398 }
397 }
399 switch ((ib_chunk->kdata[idx] & RADEON_TXFORMAT_FORMAT_MASK)) {
398 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
400 case R200_TXFORMAT_I8:
401 case R200_TXFORMAT_RGB332:
402 case R200_TXFORMAT_Y8:
403 track->textures[i].cpp = 1;
404 break;
405 case R200_TXFORMAT_DXT1:
406 case R200_TXFORMAT_AI88:
407 case R200_TXFORMAT_ARGB1555:

--- 11 unchanged lines hidden (view full) ---

419 case R200_TXFORMAT_ABGR8888:
420 case R200_TXFORMAT_BGR111110:
421 case R200_TXFORMAT_LDVDU8888:
422 case R200_TXFORMAT_DXT23:
423 case R200_TXFORMAT_DXT45:
424 track->textures[i].cpp = 4;
425 break;
426 }
399 case R200_TXFORMAT_I8:
400 case R200_TXFORMAT_RGB332:
401 case R200_TXFORMAT_Y8:
402 track->textures[i].cpp = 1;
403 break;
404 case R200_TXFORMAT_DXT1:
405 case R200_TXFORMAT_AI88:
406 case R200_TXFORMAT_ARGB1555:

--- 11 unchanged lines hidden (view full) ---

418 case R200_TXFORMAT_ABGR8888:
419 case R200_TXFORMAT_BGR111110:
420 case R200_TXFORMAT_LDVDU8888:
421 case R200_TXFORMAT_DXT23:
422 case R200_TXFORMAT_DXT45:
423 track->textures[i].cpp = 4;
424 break;
425 }
427 track->textures[i].cube_info[4].width = 1 << ((ib_chunk->kdata[idx] >> 16) & 0xf);
428 track->textures[i].cube_info[4].height = 1 << ((ib_chunk->kdata[idx] >> 20) & 0xf);
426 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
427 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
429 break;
430 case R200_PP_CUBIC_FACES_0:
431 case R200_PP_CUBIC_FACES_1:
432 case R200_PP_CUBIC_FACES_2:
433 case R200_PP_CUBIC_FACES_3:
434 case R200_PP_CUBIC_FACES_4:
435 case R200_PP_CUBIC_FACES_5:
428 break;
429 case R200_PP_CUBIC_FACES_0:
430 case R200_PP_CUBIC_FACES_1:
431 case R200_PP_CUBIC_FACES_2:
432 case R200_PP_CUBIC_FACES_3:
433 case R200_PP_CUBIC_FACES_4:
434 case R200_PP_CUBIC_FACES_5:
436 tmp = ib_chunk->kdata[idx];
435 tmp = idx_value;
437 i = (reg - R200_PP_CUBIC_FACES_0) / 32;
438 for (face = 0; face < 4; face++) {
439 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
440 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
441 }
442 break;
443 default:
444 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",

--- 12 unchanged lines hidden --- 		436 i = (reg - R200_PP_CUBIC_FACES_0) / 32;
437 for (face = 0; face < 4; face++) {
438 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
439 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
440 }
441 break;
442 default:
443 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",

--- 12 unchanged lines hidden ---