r100.c (3c3d7cb1db4af176dab843f22ea092a4ef1eb989) r100.c (ff212f25feb44a915ce9c0144faef7fae27a6e61)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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1188 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1189 else {
1190 tmp |= RADEON_RB_NO_UPDATE;
1191 WREG32(R_000770_SCRATCH_UMSK, 0);
1192 }
1193
1194 WREG32(RADEON_CP_RB_CNTL, tmp);
1195 udelay(10);
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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1188 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1189 else {
1190 tmp |= RADEON_RB_NO_UPDATE;
1191 WREG32(R_000770_SCRATCH_UMSK, 0);
1192 }
1193
1194 WREG32(RADEON_CP_RB_CNTL, tmp);
1195 udelay(10);
1196 ring->rptr = RREG32(RADEON_CP_RB_RPTR);
1197 /* Set cp mode to bus mastering & enable cp*/
1198 WREG32(RADEON_CP_CSQ_MODE,
1199 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1200 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1201 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1202 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1203 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1204

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2518}
2519
2520bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2521{
2522 u32 rbbm_status;
2523
2524 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2525 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
1196 /* Set cp mode to bus mastering & enable cp*/
1197 WREG32(RADEON_CP_CSQ_MODE,
1198 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1199 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1200 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1201 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1202 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1203

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2517}
2518
2519bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2520{
2521 u32 rbbm_status;
2522
2523 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2524 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2526 radeon_ring_lockup_update(ring);
2525 radeon_ring_lockup_update(rdev, ring);
2527 return false;
2528 }
2529 /* force CP activities */
2530 radeon_ring_force_activity(rdev, ring);
2531 return radeon_ring_test_lockup(rdev, ring);
2532}
2533
2534/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */

--- 1611 unchanged lines hidden --- 		2526 return false;
2527 }
2528 /* force CP activities */
2529 radeon_ring_force_activity(rdev, ring);
2530 return radeon_ring_test_lockup(rdev, ring);
2531}
2532
2533/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */

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