r100.c (38a5d6736e7f714cc56d58692001e66dcbb98799) r100.c (62f288cfe1c6257afe6ddfdff153c3803e8cdd72)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 1413 unchanged lines hidden (view full) ---

1422 if (r) {
1423 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1424 idx, reg);
1425 r100_cs_dump_packet(p, pkt);
1426 return r;
1427 }
1428 track->zb.robj = reloc->robj;
1429 track->zb.offset = idx_value;
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 1413 unchanged lines hidden (view full) ---

1422 if (r) {
1423 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1424 idx, reg);
1425 r100_cs_dump_packet(p, pkt);
1426 return r;
1427 }
1428 track->zb.robj = reloc->robj;
1429 track->zb.offset = idx_value;
1430 track->zb_dirty = true;
1431 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1432 break;
1433 case RADEON_RB3D_COLOROFFSET:
1434 r = r100_cs_packet_next_reloc(p, &reloc);
1435 if (r) {
1436 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1437 idx, reg);
1438 r100_cs_dump_packet(p, pkt);
1439 return r;
1440 }
1441 track->cb[0].robj = reloc->robj;
1442 track->cb[0].offset = idx_value;
1430 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1431 break;
1432 case RADEON_RB3D_COLOROFFSET:
1433 r = r100_cs_packet_next_reloc(p, &reloc);
1434 if (r) {
1435 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1436 idx, reg);
1437 r100_cs_dump_packet(p, pkt);
1438 return r;
1439 }
1440 track->cb[0].robj = reloc->robj;
1441 track->cb[0].offset = idx_value;
1443 track->cb_dirty = true;
1444 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1445 break;
1446 case RADEON_PP_TXOFFSET_0:
1447 case RADEON_PP_TXOFFSET_1:
1448 case RADEON_PP_TXOFFSET_2:
1449 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1450 r = r100_cs_packet_next_reloc(p, &reloc);
1451 if (r) {
1452 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1453 idx, reg);
1454 r100_cs_dump_packet(p, pkt);
1455 return r;
1456 }
1457 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1458 track->textures[i].robj = reloc->robj;
1442 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1443 break;
1444 case RADEON_PP_TXOFFSET_0:
1445 case RADEON_PP_TXOFFSET_1:
1446 case RADEON_PP_TXOFFSET_2:
1447 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1448 r = r100_cs_packet_next_reloc(p, &reloc);
1449 if (r) {
1450 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1451 idx, reg);
1452 r100_cs_dump_packet(p, pkt);
1453 return r;
1454 }
1455 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1456 track->textures[i].robj = reloc->robj;
1459 track->tex_dirty = true;
1460 break;
1461 case RADEON_PP_CUBIC_OFFSET_T0_0:
1462 case RADEON_PP_CUBIC_OFFSET_T0_1:
1463 case RADEON_PP_CUBIC_OFFSET_T0_2:
1464 case RADEON_PP_CUBIC_OFFSET_T0_3:
1465 case RADEON_PP_CUBIC_OFFSET_T0_4:
1466 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1467 r = r100_cs_packet_next_reloc(p, &reloc);
1468 if (r) {
1469 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1470 idx, reg);
1471 r100_cs_dump_packet(p, pkt);
1472 return r;
1473 }
1474 track->textures[0].cube_info[i].offset = idx_value;
1475 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1476 track->textures[0].cube_info[i].robj = reloc->robj;
1457 break;
1458 case RADEON_PP_CUBIC_OFFSET_T0_0:
1459 case RADEON_PP_CUBIC_OFFSET_T0_1:
1460 case RADEON_PP_CUBIC_OFFSET_T0_2:
1461 case RADEON_PP_CUBIC_OFFSET_T0_3:
1462 case RADEON_PP_CUBIC_OFFSET_T0_4:
1463 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1464 r = r100_cs_packet_next_reloc(p, &reloc);
1465 if (r) {
1466 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1467 idx, reg);
1468 r100_cs_dump_packet(p, pkt);
1469 return r;
1470 }
1471 track->textures[0].cube_info[i].offset = idx_value;
1472 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1473 track->textures[0].cube_info[i].robj = reloc->robj;
1477 track->tex_dirty = true;
1478 break;
1479 case RADEON_PP_CUBIC_OFFSET_T1_0:
1480 case RADEON_PP_CUBIC_OFFSET_T1_1:
1481 case RADEON_PP_CUBIC_OFFSET_T1_2:
1482 case RADEON_PP_CUBIC_OFFSET_T1_3:
1483 case RADEON_PP_CUBIC_OFFSET_T1_4:
1484 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1485 r = r100_cs_packet_next_reloc(p, &reloc);
1486 if (r) {
1487 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1488 idx, reg);
1489 r100_cs_dump_packet(p, pkt);
1490 return r;
1491 }
1492 track->textures[1].cube_info[i].offset = idx_value;
1493 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1494 track->textures[1].cube_info[i].robj = reloc->robj;
1474 break;
1475 case RADEON_PP_CUBIC_OFFSET_T1_0:
1476 case RADEON_PP_CUBIC_OFFSET_T1_1:
1477 case RADEON_PP_CUBIC_OFFSET_T1_2:
1478 case RADEON_PP_CUBIC_OFFSET_T1_3:
1479 case RADEON_PP_CUBIC_OFFSET_T1_4:
1480 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1481 r = r100_cs_packet_next_reloc(p, &reloc);
1482 if (r) {
1483 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1484 idx, reg);
1485 r100_cs_dump_packet(p, pkt);
1486 return r;
1487 }
1488 track->textures[1].cube_info[i].offset = idx_value;
1489 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1490 track->textures[1].cube_info[i].robj = reloc->robj;
1495 track->tex_dirty = true;
1496 break;
1497 case RADEON_PP_CUBIC_OFFSET_T2_0:
1498 case RADEON_PP_CUBIC_OFFSET_T2_1:
1499 case RADEON_PP_CUBIC_OFFSET_T2_2:
1500 case RADEON_PP_CUBIC_OFFSET_T2_3:
1501 case RADEON_PP_CUBIC_OFFSET_T2_4:
1502 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1503 r = r100_cs_packet_next_reloc(p, &reloc);
1504 if (r) {
1505 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1506 idx, reg);
1507 r100_cs_dump_packet(p, pkt);
1508 return r;
1509 }
1510 track->textures[2].cube_info[i].offset = idx_value;
1511 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1512 track->textures[2].cube_info[i].robj = reloc->robj;
1491 break;
1492 case RADEON_PP_CUBIC_OFFSET_T2_0:
1493 case RADEON_PP_CUBIC_OFFSET_T2_1:
1494 case RADEON_PP_CUBIC_OFFSET_T2_2:
1495 case RADEON_PP_CUBIC_OFFSET_T2_3:
1496 case RADEON_PP_CUBIC_OFFSET_T2_4:
1497 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1498 r = r100_cs_packet_next_reloc(p, &reloc);
1499 if (r) {
1500 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1501 idx, reg);
1502 r100_cs_dump_packet(p, pkt);
1503 return r;
1504 }
1505 track->textures[2].cube_info[i].offset = idx_value;
1506 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1507 track->textures[2].cube_info[i].robj = reloc->robj;
1513 track->tex_dirty = true;
1514 break;
1515 case RADEON_RE_WIDTH_HEIGHT:
1516 track->maxy = ((idx_value >> 16) & 0x7FF);
1508 break;
1509 case RADEON_RE_WIDTH_HEIGHT:
1510 track->maxy = ((idx_value >> 16) & 0x7FF);
1517 track->cb_dirty = true;
1518 track->zb_dirty = true;
1519 break;
1520 case RADEON_RB3D_COLORPITCH:
1521 r = r100_cs_packet_next_reloc(p, &reloc);
1522 if (r) {
1523 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1524 idx, reg);
1525 r100_cs_dump_packet(p, pkt);
1526 return r;

--- 4 unchanged lines hidden (view full) ---

1531 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1532 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1533
1534 tmp = idx_value & ~(0x7 << 16);
1535 tmp |= tile_flags;
1536 ib[idx] = tmp;
1537
1538 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1511 break;
1512 case RADEON_RB3D_COLORPITCH:
1513 r = r100_cs_packet_next_reloc(p, &reloc);
1514 if (r) {
1515 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1516 idx, reg);
1517 r100_cs_dump_packet(p, pkt);
1518 return r;

--- 4 unchanged lines hidden (view full) ---

1523 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1524 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1525
1526 tmp = idx_value & ~(0x7 << 16);
1527 tmp |= tile_flags;
1528 ib[idx] = tmp;
1529
1530 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1539 track->cb_dirty = true;
1540 break;
1541 case RADEON_RB3D_DEPTHPITCH:
1542 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1531 break;
1532 case RADEON_RB3D_DEPTHPITCH:
1533 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1543 track->zb_dirty = true;
1544 break;
1545 case RADEON_RB3D_CNTL:
1546 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1547 case 7:
1548 case 8:
1549 case 9:
1550 case 11:
1551 case 12:

--- 8 unchanged lines hidden (view full) ---

1560 track->cb[0].cpp = 4;
1561 break;
1562 default:
1563 DRM_ERROR("Invalid color buffer format (%d) !\n",
1564 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1565 return -EINVAL;
1566 }
1567 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1534 break;
1535 case RADEON_RB3D_CNTL:
1536 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1537 case 7:
1538 case 8:
1539 case 9:
1540 case 11:
1541 case 12:

--- 8 unchanged lines hidden (view full) ---

1550 track->cb[0].cpp = 4;
1551 break;
1552 default:
1553 DRM_ERROR("Invalid color buffer format (%d) !\n",
1554 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1555 return -EINVAL;
1556 }
1557 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1568 track->cb_dirty = true;
1569 track->zb_dirty = true;
1570 break;
1571 case RADEON_RB3D_ZSTENCILCNTL:
1572 switch (idx_value & 0xf) {
1573 case 0:
1574 track->zb.cpp = 2;
1575 break;
1576 case 2:
1577 case 3:
1578 case 4:
1579 case 5:
1580 case 9:
1581 case 11:
1582 track->zb.cpp = 4;
1583 break;
1584 default:
1585 break;
1586 }
1558 break;
1559 case RADEON_RB3D_ZSTENCILCNTL:
1560 switch (idx_value & 0xf) {
1561 case 0:
1562 track->zb.cpp = 2;
1563 break;
1564 case 2:
1565 case 3:
1566 case 4:
1567 case 5:
1568 case 9:
1569 case 11:
1570 track->zb.cpp = 4;
1571 break;
1572 default:
1573 break;
1574 }
1587 track->zb_dirty = true;
1588 break;
1589 case RADEON_RB3D_ZPASS_ADDR:
1590 r = r100_cs_packet_next_reloc(p, &reloc);
1591 if (r) {
1592 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1593 idx, reg);
1594 r100_cs_dump_packet(p, pkt);
1595 return r;
1596 }
1597 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1598 break;
1599 case RADEON_PP_CNTL:
1600 {
1601 uint32_t temp = idx_value >> 4;
1602 for (i = 0; i < track->num_texture; i++)
1603 track->textures[i].enabled = !!(temp & (1 << i));
1575 break;
1576 case RADEON_RB3D_ZPASS_ADDR:
1577 r = r100_cs_packet_next_reloc(p, &reloc);
1578 if (r) {
1579 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1580 idx, reg);
1581 r100_cs_dump_packet(p, pkt);
1582 return r;
1583 }
1584 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1585 break;
1586 case RADEON_PP_CNTL:
1587 {
1588 uint32_t temp = idx_value >> 4;
1589 for (i = 0; i < track->num_texture; i++)
1590 track->textures[i].enabled = !!(temp & (1 << i));
1604 track->tex_dirty = true;
1605 }
1606 break;
1607 case RADEON_SE_VF_CNTL:
1608 track->vap_vf_cntl = idx_value;
1609 break;
1610 case RADEON_SE_VTX_FMT:
1611 track->vtx_size = r100_get_vtx_size(idx_value);
1612 break;
1613 case RADEON_PP_TEX_SIZE_0:
1614 case RADEON_PP_TEX_SIZE_1:
1615 case RADEON_PP_TEX_SIZE_2:
1616 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1617 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1618 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1591 }
1592 break;
1593 case RADEON_SE_VF_CNTL:
1594 track->vap_vf_cntl = idx_value;
1595 break;
1596 case RADEON_SE_VTX_FMT:
1597 track->vtx_size = r100_get_vtx_size(idx_value);
1598 break;
1599 case RADEON_PP_TEX_SIZE_0:
1600 case RADEON_PP_TEX_SIZE_1:
1601 case RADEON_PP_TEX_SIZE_2:
1602 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1603 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1604 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1619 track->tex_dirty = true;
1620 break;
1621 case RADEON_PP_TEX_PITCH_0:
1622 case RADEON_PP_TEX_PITCH_1:
1623 case RADEON_PP_TEX_PITCH_2:
1624 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1625 track->textures[i].pitch = idx_value + 32;
1605 break;
1606 case RADEON_PP_TEX_PITCH_0:
1607 case RADEON_PP_TEX_PITCH_1:
1608 case RADEON_PP_TEX_PITCH_2:
1609 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1610 track->textures[i].pitch = idx_value + 32;
1626 track->tex_dirty = true;
1627 break;
1628 case RADEON_PP_TXFILTER_0:
1629 case RADEON_PP_TXFILTER_1:
1630 case RADEON_PP_TXFILTER_2:
1631 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1632 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1633 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1634 tmp = (idx_value >> 23) & 0x7;
1635 if (tmp == 2 || tmp == 6)
1636 track->textures[i].roundup_w = false;
1637 tmp = (idx_value >> 27) & 0x7;
1638 if (tmp == 2 || tmp == 6)
1639 track->textures[i].roundup_h = false;
1611 break;
1612 case RADEON_PP_TXFILTER_0:
1613 case RADEON_PP_TXFILTER_1:
1614 case RADEON_PP_TXFILTER_2:
1615 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1616 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1617 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1618 tmp = (idx_value >> 23) & 0x7;
1619 if (tmp == 2 || tmp == 6)
1620 track->textures[i].roundup_w = false;
1621 tmp = (idx_value >> 27) & 0x7;
1622 if (tmp == 2 || tmp == 6)
1623 track->textures[i].roundup_h = false;
1640 track->tex_dirty = true;
1641 break;
1642 case RADEON_PP_TXFORMAT_0:
1643 case RADEON_PP_TXFORMAT_1:
1644 case RADEON_PP_TXFORMAT_2:
1645 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1646 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1647 track->textures[i].use_pitch = 1;
1648 } else {

--- 36 unchanged lines hidden (view full) ---

1685 case RADEON_TXFORMAT_DXT23:
1686 case RADEON_TXFORMAT_DXT45:
1687 track->textures[i].cpp = 1;
1688 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1689 break;
1690 }
1691 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1692 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1624 break;
1625 case RADEON_PP_TXFORMAT_0:
1626 case RADEON_PP_TXFORMAT_1:
1627 case RADEON_PP_TXFORMAT_2:
1628 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1629 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1630 track->textures[i].use_pitch = 1;
1631 } else {

--- 36 unchanged lines hidden (view full) ---

1668 case RADEON_TXFORMAT_DXT23:
1669 case RADEON_TXFORMAT_DXT45:
1670 track->textures[i].cpp = 1;
1671 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1672 break;
1673 }
1674 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1675 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1693 track->tex_dirty = true;
1694 break;
1695 case RADEON_PP_CUBIC_FACES_0:
1696 case RADEON_PP_CUBIC_FACES_1:
1697 case RADEON_PP_CUBIC_FACES_2:
1698 tmp = idx_value;
1699 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1700 for (face = 0; face < 4; face++) {
1701 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1702 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1703 }
1676 break;
1677 case RADEON_PP_CUBIC_FACES_0:
1678 case RADEON_PP_CUBIC_FACES_1:
1679 case RADEON_PP_CUBIC_FACES_2:
1680 tmp = idx_value;
1681 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1682 for (face = 0; face < 4; face++) {
1683 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1684 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1685 }
1704 track->tex_dirty = true;
1705 break;
1706 default:
1707 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1708 reg, idx);
1709 return -EINVAL;
1710 }
1711 return 0;
1712}

--- 1619 unchanged lines hidden (view full) ---

3332}
3333
3334int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3335{
3336 unsigned i;
3337 unsigned long size;
3338 unsigned prim_walk;
3339 unsigned nverts;
1686 break;
1687 default:
1688 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1689 reg, idx);
1690 return -EINVAL;
1691 }
1692 return 0;
1693}

--- 1619 unchanged lines hidden (view full) ---

3313}
3314
3315int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3316{
3317 unsigned i;
3318 unsigned long size;
3319 unsigned prim_walk;
3320 unsigned nverts;
3340 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
3321 unsigned num_cb = track->num_cb;
3341
3322
3342 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
3323 if (!track->zb_cb_clear && !track->color_channel_mask &&
3343 !track->blend_read_enable)
3344 num_cb = 0;
3345
3346 for (i = 0; i < num_cb; i++) {
3347 if (track->cb[i].robj == NULL) {
3348 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3349 return -EINVAL;
3350 }

--- 4 unchanged lines hidden (view full) ---

3355 "(need %lu have %lu) !\n", i, size,
3356 radeon_bo_size(track->cb[i].robj));
3357 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3358 i, track->cb[i].pitch, track->cb[i].cpp,
3359 track->cb[i].offset, track->maxy);
3360 return -EINVAL;
3361 }
3362 }
3324 !track->blend_read_enable)
3325 num_cb = 0;
3326
3327 for (i = 0; i < num_cb; i++) {
3328 if (track->cb[i].robj == NULL) {
3329 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3330 return -EINVAL;
3331 }

--- 4 unchanged lines hidden (view full) ---

3336 "(need %lu have %lu) !\n", i, size,
3337 radeon_bo_size(track->cb[i].robj));
3338 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3339 i, track->cb[i].pitch, track->cb[i].cpp,
3340 track->cb[i].offset, track->maxy);
3341 return -EINVAL;
3342 }
3343 }
3363 track->cb_dirty = false;
3364
3365 if (track->zb_dirty && track->z_enabled) {
3344 if (track->z_enabled) {
3366 if (track->zb.robj == NULL) {
3367 DRM_ERROR("[drm] No buffer for z buffer !\n");
3368 return -EINVAL;
3369 }
3370 size = track->zb.pitch * track->zb.cpp * track->maxy;
3371 size += track->zb.offset;
3372 if (size > radeon_bo_size(track->zb.robj)) {
3373 DRM_ERROR("[drm] Buffer too small for z buffer "
3374 "(need %lu have %lu) !\n", size,
3375 radeon_bo_size(track->zb.robj));
3376 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3377 track->zb.pitch, track->zb.cpp,
3378 track->zb.offset, track->maxy);
3379 return -EINVAL;
3380 }
3381 }
3345 if (track->zb.robj == NULL) {
3346 DRM_ERROR("[drm] No buffer for z buffer !\n");
3347 return -EINVAL;
3348 }
3349 size = track->zb.pitch * track->zb.cpp * track->maxy;
3350 size += track->zb.offset;
3351 if (size > radeon_bo_size(track->zb.robj)) {
3352 DRM_ERROR("[drm] Buffer too small for z buffer "
3353 "(need %lu have %lu) !\n", size,
3354 radeon_bo_size(track->zb.robj));
3355 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3356 track->zb.pitch, track->zb.cpp,
3357 track->zb.offset, track->maxy);
3358 return -EINVAL;
3359 }
3360 }
3382 track->zb_dirty = false;
3383
3384 if (track->aa_dirty && track->aaresolve) {
3385 if (track->aa.robj == NULL) {
3386 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
3387 return -EINVAL;
3388 }
3389 /* I believe the format comes from colorbuffer0. */
3390 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
3391 size += track->aa.offset;
3392 if (size > radeon_bo_size(track->aa.robj)) {
3393 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
3394 "(need %lu have %lu) !\n", i, size,
3395 radeon_bo_size(track->aa.robj));
3396 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
3397 i, track->aa.pitch, track->cb[0].cpp,
3398 track->aa.offset, track->maxy);
3399 return -EINVAL;
3400 }
3401 }
3402 track->aa_dirty = false;
3403
3404 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3405 if (track->vap_vf_cntl & (1 << 14)) {
3406 nverts = track->vap_alt_nverts;
3407 } else {
3408 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3409 }
3410 switch (prim_walk) {
3411 case 1:

--- 43 unchanged lines hidden (view full) ---

3455 return -EINVAL;
3456 }
3457 break;
3458 default:
3459 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3460 prim_walk);
3461 return -EINVAL;
3462 }
3361 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3362 if (track->vap_vf_cntl & (1 << 14)) {
3363 nverts = track->vap_alt_nverts;
3364 } else {
3365 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3366 }
3367 switch (prim_walk) {
3368 case 1:

--- 43 unchanged lines hidden (view full) ---

3412 return -EINVAL;
3413 }
3414 break;
3415 default:
3416 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3417 prim_walk);
3418 return -EINVAL;
3419 }
3463
3464 if (track->tex_dirty) {
3465 track->tex_dirty = false;
3466 return r100_cs_track_texture_check(rdev, track);
3467 }
3468 return 0;
3420 return r100_cs_track_texture_check(rdev, track);
3469}
3470
3471void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3472{
3473 unsigned i, face;
3474
3421}
3422
3423void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3424{
3425 unsigned i, face;
3426
3475 track->cb_dirty = true;
3476 track->zb_dirty = true;
3477 track->tex_dirty = true;
3478 track->aa_dirty = true;
3479
3480 if (rdev->family < CHIP_R300) {
3481 track->num_cb = 1;
3482 if (rdev->family <= CHIP_RS200)
3483 track->num_texture = 3;
3484 else
3485 track->num_texture = 6;
3486 track->maxy = 2048;
3487 track->separate_cube = 1;
3488 } else {
3489 track->num_cb = 4;
3490 track->num_texture = 16;
3491 track->maxy = 4096;
3492 track->separate_cube = 0;
3427 if (rdev->family < CHIP_R300) {
3428 track->num_cb = 1;
3429 if (rdev->family <= CHIP_RS200)
3430 track->num_texture = 3;
3431 else
3432 track->num_texture = 6;
3433 track->maxy = 2048;
3434 track->separate_cube = 1;
3435 } else {
3436 track->num_cb = 4;
3437 track->num_texture = 16;
3438 track->maxy = 4096;
3439 track->separate_cube = 0;
3493 track->aaresolve = true;
3494 track->aa.robj = NULL;
3495 }
3496
3497 for (i = 0; i < track->num_cb; i++) {
3498 track->cb[i].robj = NULL;
3499 track->cb[i].pitch = 8192;
3500 track->cb[i].cpp = 16;
3501 track->cb[i].offset = 0;
3502 }

--- 131 unchanged lines hidden (view full) ---

3634 if (tmp == 0xDEADBEEF) {
3635 break;
3636 }
3637 DRM_UDELAY(1);
3638 }
3639 if (i < rdev->usec_timeout) {
3640 DRM_INFO("ib test succeeded in %u usecs\n", i);
3641 } else {
3440 }
3441
3442 for (i = 0; i < track->num_cb; i++) {
3443 track->cb[i].robj = NULL;
3444 track->cb[i].pitch = 8192;
3445 track->cb[i].cpp = 16;
3446 track->cb[i].offset = 0;
3447 }

--- 131 unchanged lines hidden (view full) ---

3579 if (tmp == 0xDEADBEEF) {
3580 break;
3581 }
3582 DRM_UDELAY(1);
3583 }
3584 if (i < rdev->usec_timeout) {
3585 DRM_INFO("ib test succeeded in %u usecs\n", i);
3586 } else {
3642 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3587 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3643 scratch, tmp);
3644 r = -EINVAL;
3645 }
3646 radeon_scratch_free(rdev, scratch);
3647 radeon_ib_free(rdev, &ib);
3648 return r;
3649}
3650
3651void r100_ib_fini(struct radeon_device *rdev)
3652{
3653 radeon_ib_pool_fini(rdev);
3654}
3655
3656int r100_ib_init(struct radeon_device *rdev)
3657{
3658 int r;
3659
3660 r = radeon_ib_pool_init(rdev);
3661 if (r) {
3588 scratch, tmp);
3589 r = -EINVAL;
3590 }
3591 radeon_scratch_free(rdev, scratch);
3592 radeon_ib_free(rdev, &ib);
3593 return r;
3594}
3595
3596void r100_ib_fini(struct radeon_device *rdev)
3597{
3598 radeon_ib_pool_fini(rdev);
3599}
3600
3601int r100_ib_init(struct radeon_device *rdev)
3602{
3603 int r;
3604
3605 r = radeon_ib_pool_init(rdev);
3606 if (r) {
3662 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3607 dev_err(rdev->dev, "failed initializing IB pool (%d).\n", r);
3663 r100_ib_fini(rdev);
3664 return r;
3665 }
3666 r = r100_ib_test(rdev);
3667 if (r) {
3608 r100_ib_fini(rdev);
3609 return r;
3610 }
3611 r = r100_ib_test(rdev);
3612 if (r) {
3668 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3613 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
3669 r100_ib_fini(rdev);
3670 return r;
3671 }
3672 return 0;
3673}
3674
3675void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3676{

--- 141 unchanged lines hidden (view full) ---

3818 return r;
3819
3820 /* Enable IRQ */
3821 r100_irq_set(rdev);
3822 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3823 /* 1M ring buffer */
3824 r = r100_cp_init(rdev, 1024 * 1024);
3825 if (r) {
3614 r100_ib_fini(rdev);
3615 return r;
3616 }
3617 return 0;
3618}
3619
3620void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3621{

--- 141 unchanged lines hidden (view full) ---

3763 return r;
3764
3765 /* Enable IRQ */
3766 r100_irq_set(rdev);
3767 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3768 /* 1M ring buffer */
3769 r = r100_cp_init(rdev, 1024 * 1024);
3770 if (r) {
3826 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3771 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3827 return r;
3828 }
3829 r = r100_ib_init(rdev);
3830 if (r) {
3772 return r;
3773 }
3774 r = r100_ib_init(rdev);
3775 if (r) {
3831 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3776 dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
3832 return r;
3833 }
3834 return 0;
3835}
3836
3837int r100_resume(struct radeon_device *rdev)
3838{
3839 /* Make sur GART are not working */

--- 154 unchanged lines hidden --- 		3777 return r;
3778 }
3779 return 0;
3780}
3781
3782int r100_resume(struct radeon_device *rdev)
3783{
3784 /* Make sur GART are not working */

--- 154 unchanged lines hidden ---