r100.c (1614f8b17b8cc3ad143541d41569623d30dbc9ec) r100.c (4c7886791264f03428d5424befb1b96f08fc90f4)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 247 unchanged lines hidden (view full) ---

256 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
257}
258
259int r100_wb_init(struct radeon_device *rdev)
260{
261 int r;
262
263 if (rdev->wb.wb_obj == NULL) {
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 247 unchanged lines hidden (view full) ---

256 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
257}
258
259int r100_wb_init(struct radeon_device *rdev)
260{
261 int r;
262
263 if (rdev->wb.wb_obj == NULL) {
264 r = radeon_object_create(rdev, NULL, RADEON_GPU_PAGE_SIZE,
265 true,
266 RADEON_GEM_DOMAIN_GTT,
267 false, &rdev->wb.wb_obj);
264 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
265 RADEON_GEM_DOMAIN_GTT,
266 &rdev->wb.wb_obj);
268 if (r) {
267 if (r) {
269 DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
268 dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
270 return r;
271 }
269 return r;
270 }
272 r = radeon_object_pin(rdev->wb.wb_obj,
273 RADEON_GEM_DOMAIN_GTT,
274 &rdev->wb.gpu_addr);
271 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
272 if (unlikely(r != 0))
273 return r;
274 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
275 &rdev->wb.gpu_addr);
275 if (r) {
276 if (r) {
276 DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
277 dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
278 radeon_bo_unreserve(rdev->wb.wb_obj);
277 return r;
278 }
279 return r;
280 }
279 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
281 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
282 radeon_bo_unreserve(rdev->wb.wb_obj);
280 if (r) {
283 if (r) {
281 DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
284 dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
282 return r;
283 }
284 }
285 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
286 WREG32(R_00070C_CP_RB_RPTR_ADDR,
287 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
288 WREG32(R_000770_SCRATCH_UMSK, 0xff);
289 return 0;
290}
291
292void r100_wb_disable(struct radeon_device *rdev)
293{
294 WREG32(R_000770_SCRATCH_UMSK, 0);
295}
296
297void r100_wb_fini(struct radeon_device *rdev)
298{
285 return r;
286 }
287 }
288 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
289 WREG32(R_00070C_CP_RB_RPTR_ADDR,
290 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
291 WREG32(R_000770_SCRATCH_UMSK, 0xff);
292 return 0;
293}
294
295void r100_wb_disable(struct radeon_device *rdev)
296{
297 WREG32(R_000770_SCRATCH_UMSK, 0);
298}
299
300void r100_wb_fini(struct radeon_device *rdev)
301{
302 int r;
303
299 r100_wb_disable(rdev);
300 if (rdev->wb.wb_obj) {
304 r100_wb_disable(rdev);
305 if (rdev->wb.wb_obj) {
301 radeon_object_kunmap(rdev->wb.wb_obj);
302 radeon_object_unpin(rdev->wb.wb_obj);
303 radeon_object_unref(&rdev->wb.wb_obj);
306 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
307 if (unlikely(r != 0)) {
308 dev_err(rdev->dev, "(%d) can't finish WB\n", r);
309 return;
310 }
311 radeon_bo_kunmap(rdev->wb.wb_obj);
312 radeon_bo_unpin(rdev->wb.wb_obj);
313 radeon_bo_unreserve(rdev->wb.wb_obj);
314 radeon_bo_unref(&rdev->wb.wb_obj);
304 rdev->wb.wb = NULL;
305 rdev->wb.wb_obj = NULL;
306 }
307}
308
309int r100_copy_blit(struct radeon_device *rdev,
310 uint64_t src_offset,
311 uint64_t dst_offset,

--- 977 unchanged lines hidden (view full) ---

1289 reg, idx);
1290 return -EINVAL;
1291 }
1292 return 0;
1293}
1294
1295int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1296 struct radeon_cs_packet *pkt,
315 rdev->wb.wb = NULL;
316 rdev->wb.wb_obj = NULL;
317 }
318}
319
320int r100_copy_blit(struct radeon_device *rdev,
321 uint64_t src_offset,
322 uint64_t dst_offset,

--- 977 unchanged lines hidden (view full) ---

1300 reg, idx);
1301 return -EINVAL;
1302 }
1303 return 0;
1304}
1305
1306int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1307 struct radeon_cs_packet *pkt,
1297 struct radeon_object *robj)
1308 struct radeon_bo *robj)
1298{
1299 unsigned idx;
1300 u32 value;
1301 idx = pkt->idx + 1;
1302 value = radeon_get_ib_value(p, idx + 2);
1309{
1310 unsigned idx;
1311 u32 value;
1312 idx = pkt->idx + 1;
1313 value = radeon_get_ib_value(p, idx + 2);
1303 if ((value + 1) > radeon_object_size(robj)) {
1314 if ((value + 1) > radeon_bo_size(robj)) {
1304 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1305 "(need %u have %lu) !\n",
1306 value + 1,
1315 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1316 "(need %u have %lu) !\n",
1317 value + 1,
1307 radeon_object_size(robj));
1318 radeon_bo_size(robj));
1308 return -EINVAL;
1309 }
1310 return 0;
1311}
1312
1313static int r100_packet3_check(struct radeon_cs_parser *p,
1314 struct radeon_cs_packet *pkt)
1315{

--- 1287 unchanged lines hidden (view full) ---

2603 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2604 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2605}
2606
2607static int r100_cs_track_cube(struct radeon_device *rdev,
2608 struct r100_cs_track *track, unsigned idx)
2609{
2610 unsigned face, w, h;
1319 return -EINVAL;
1320 }
1321 return 0;
1322}
1323
1324static int r100_packet3_check(struct radeon_cs_parser *p,
1325 struct radeon_cs_packet *pkt)
1326{

--- 1287 unchanged lines hidden (view full) ---

2614 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2615 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2616}
2617
2618static int r100_cs_track_cube(struct radeon_device *rdev,
2619 struct r100_cs_track *track, unsigned idx)
2620{
2621 unsigned face, w, h;
2611 struct radeon_object *cube_robj;
2622 struct radeon_bo *cube_robj;
2612 unsigned long size;
2613
2614 for (face = 0; face < 5; face++) {
2615 cube_robj = track->textures[idx].cube_info[face].robj;
2616 w = track->textures[idx].cube_info[face].width;
2617 h = track->textures[idx].cube_info[face].height;
2618
2619 size = w * h;
2620 size *= track->textures[idx].cpp;
2621
2622 size += track->textures[idx].cube_info[face].offset;
2623
2623 unsigned long size;
2624
2625 for (face = 0; face < 5; face++) {
2626 cube_robj = track->textures[idx].cube_info[face].robj;
2627 w = track->textures[idx].cube_info[face].width;
2628 h = track->textures[idx].cube_info[face].height;
2629
2630 size = w * h;
2631 size *= track->textures[idx].cpp;
2632
2633 size += track->textures[idx].cube_info[face].offset;
2634
2624 if (size > radeon_object_size(cube_robj)) {
2635 if (size > radeon_bo_size(cube_robj)) {
2625 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2636 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2626 size, radeon_object_size(cube_robj));
2637 size, radeon_bo_size(cube_robj));
2627 r100_cs_track_texture_print(&track->textures[idx]);
2628 return -1;
2629 }
2630 }
2631 return 0;
2632}
2633
2634static int r100_cs_track_texture_check(struct radeon_device *rdev,
2635 struct r100_cs_track *track)
2636{
2638 r100_cs_track_texture_print(&track->textures[idx]);
2639 return -1;
2640 }
2641 }
2642 return 0;
2643}
2644
2645static int r100_cs_track_texture_check(struct radeon_device *rdev,
2646 struct r100_cs_track *track)
2647{
2637 struct radeon_object *robj;
2648 struct radeon_bo *robj;
2638 unsigned long size;
2639 unsigned u, i, w, h;
2640 int ret;
2641
2642 for (u = 0; u < track->num_texture; u++) {
2643 if (!track->textures[u].enabled)
2644 continue;
2645 robj = track->textures[u].robj;

--- 39 unchanged lines hidden (view full) ---

2685 } else
2686 size *= 6;
2687 break;
2688 default:
2689 DRM_ERROR("Invalid texture coordinate type %u for unit "
2690 "%u\n", track->textures[u].tex_coord_type, u);
2691 return -EINVAL;
2692 }
2649 unsigned long size;
2650 unsigned u, i, w, h;
2651 int ret;
2652
2653 for (u = 0; u < track->num_texture; u++) {
2654 if (!track->textures[u].enabled)
2655 continue;
2656 robj = track->textures[u].robj;

--- 39 unchanged lines hidden (view full) ---

2696 } else
2697 size *= 6;
2698 break;
2699 default:
2700 DRM_ERROR("Invalid texture coordinate type %u for unit "
2701 "%u\n", track->textures[u].tex_coord_type, u);
2702 return -EINVAL;
2703 }
2693 if (size > radeon_object_size(robj)) {
2704 if (size > radeon_bo_size(robj)) {
2694 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2705 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2695 "%lu\n", u, size, radeon_object_size(robj));
2706 "%lu\n", u, size, radeon_bo_size(robj));
2696 r100_cs_track_texture_print(&track->textures[u]);
2697 return -EINVAL;
2698 }
2699 }
2700 return 0;
2701}
2702
2703int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)

--- 5 unchanged lines hidden (view full) ---

2709
2710 for (i = 0; i < track->num_cb; i++) {
2711 if (track->cb[i].robj == NULL) {
2712 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2713 return -EINVAL;
2714 }
2715 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2716 size += track->cb[i].offset;
2707 r100_cs_track_texture_print(&track->textures[u]);
2708 return -EINVAL;
2709 }
2710 }
2711 return 0;
2712}
2713
2714int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)

--- 5 unchanged lines hidden (view full) ---

2720
2721 for (i = 0; i < track->num_cb; i++) {
2722 if (track->cb[i].robj == NULL) {
2723 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2724 return -EINVAL;
2725 }
2726 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2727 size += track->cb[i].offset;
2717 if (size > radeon_object_size(track->cb[i].robj)) {
2728 if (size > radeon_bo_size(track->cb[i].robj)) {
2718 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2719 "(need %lu have %lu) !\n", i, size,
2729 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2730 "(need %lu have %lu) !\n", i, size,
2720 radeon_object_size(track->cb[i].robj));
2731 radeon_bo_size(track->cb[i].robj));
2721 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2722 i, track->cb[i].pitch, track->cb[i].cpp,
2723 track->cb[i].offset, track->maxy);
2724 return -EINVAL;
2725 }
2726 }
2727 if (track->z_enabled) {
2728 if (track->zb.robj == NULL) {
2729 DRM_ERROR("[drm] No buffer for z buffer !\n");
2730 return -EINVAL;
2731 }
2732 size = track->zb.pitch * track->zb.cpp * track->maxy;
2733 size += track->zb.offset;
2732 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2733 i, track->cb[i].pitch, track->cb[i].cpp,
2734 track->cb[i].offset, track->maxy);
2735 return -EINVAL;
2736 }
2737 }
2738 if (track->z_enabled) {
2739 if (track->zb.robj == NULL) {
2740 DRM_ERROR("[drm] No buffer for z buffer !\n");
2741 return -EINVAL;
2742 }
2743 size = track->zb.pitch * track->zb.cpp * track->maxy;
2744 size += track->zb.offset;
2734 if (size > radeon_object_size(track->zb.robj)) {
2745 if (size > radeon_bo_size(track->zb.robj)) {
2735 DRM_ERROR("[drm] Buffer too small for z buffer "
2736 "(need %lu have %lu) !\n", size,
2746 DRM_ERROR("[drm] Buffer too small for z buffer "
2747 "(need %lu have %lu) !\n", size,
2737 radeon_object_size(track->zb.robj));
2748 radeon_bo_size(track->zb.robj));
2738 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2739 track->zb.pitch, track->zb.cpp,
2740 track->zb.offset, track->maxy);
2741 return -EINVAL;
2742 }
2743 }
2744 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2745 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2746 switch (prim_walk) {
2747 case 1:
2748 for (i = 0; i < track->num_arrays; i++) {
2749 size = track->arrays[i].esize * track->max_indx * 4;
2750 if (track->arrays[i].robj == NULL) {
2751 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2752 "bound\n", prim_walk, i);
2753 return -EINVAL;
2754 }
2749 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2750 track->zb.pitch, track->zb.cpp,
2751 track->zb.offset, track->maxy);
2752 return -EINVAL;
2753 }
2754 }
2755 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2756 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2757 switch (prim_walk) {
2758 case 1:
2759 for (i = 0; i < track->num_arrays; i++) {
2760 size = track->arrays[i].esize * track->max_indx * 4;
2761 if (track->arrays[i].robj == NULL) {
2762 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2763 "bound\n", prim_walk, i);
2764 return -EINVAL;
2765 }
2755 if (size > radeon_object_size(track->arrays[i].robj)) {
2756 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2757 "have %lu dwords\n", prim_walk, i,
2758 size >> 2,
2759 radeon_object_size(track->arrays[i].robj) >> 2);
2766 if (size > radeon_bo_size(track->arrays[i].robj)) {
2767 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2768 "need %lu dwords have %lu dwords\n",
2769 prim_walk, i, size >> 2,
2770 radeon_bo_size(track->arrays[i].robj)
2771 >> 2);
2760 DRM_ERROR("Max indices %u\n", track->max_indx);
2761 return -EINVAL;
2762 }
2763 }
2764 break;
2765 case 2:
2766 for (i = 0; i < track->num_arrays; i++) {
2767 size = track->arrays[i].esize * (nverts - 1) * 4;
2768 if (track->arrays[i].robj == NULL) {
2769 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2770 "bound\n", prim_walk, i);
2771 return -EINVAL;
2772 }
2772 DRM_ERROR("Max indices %u\n", track->max_indx);
2773 return -EINVAL;
2774 }
2775 }
2776 break;
2777 case 2:
2778 for (i = 0; i < track->num_arrays; i++) {
2779 size = track->arrays[i].esize * (nverts - 1) * 4;
2780 if (track->arrays[i].robj == NULL) {
2781 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2782 "bound\n", prim_walk, i);
2783 return -EINVAL;
2784 }
2773 if (size > radeon_object_size(track->arrays[i].robj)) {
2774 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2775 "have %lu dwords\n", prim_walk, i, size >> 2,
2776 radeon_object_size(track->arrays[i].robj) >> 2);
2785 if (size > radeon_bo_size(track->arrays[i].robj)) {
2786 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2787 "need %lu dwords have %lu dwords\n",
2788 prim_walk, i, size >> 2,
2789 radeon_bo_size(track->arrays[i].robj)
2790 >> 2);
2777 return -EINVAL;
2778 }
2779 }
2780 break;
2781 case 3:
2782 size = track->vtx_size * nverts;
2783 if (size != track->immd_dwords) {
2784 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",

--- 398 unchanged lines hidden (view full) ---

3183 r100_cp_fini(rdev);
3184 r100_wb_fini(rdev);
3185 r100_ib_fini(rdev);
3186 radeon_gem_fini(rdev);
3187 if (rdev->flags & RADEON_IS_PCI)
3188 r100_pci_gart_fini(rdev);
3189 radeon_irq_kms_fini(rdev);
3190 radeon_fence_driver_fini(rdev);
2791 return -EINVAL;
2792 }
2793 }
2794 break;
2795 case 3:
2796 size = track->vtx_size * nverts;
2797 if (size != track->immd_dwords) {
2798 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",

--- 398 unchanged lines hidden (view full) ---

3197 r100_cp_fini(rdev);
3198 r100_wb_fini(rdev);
3199 r100_ib_fini(rdev);
3200 radeon_gem_fini(rdev);
3201 if (rdev->flags & RADEON_IS_PCI)
3202 r100_pci_gart_fini(rdev);
3203 radeon_irq_kms_fini(rdev);
3204 radeon_fence_driver_fini(rdev);
3191 radeon_object_fini(rdev);
3205 radeon_bo_fini(rdev);
3192 radeon_atombios_fini(rdev);
3193 kfree(rdev->bios);
3194 rdev->bios = NULL;
3195}
3196
3197int r100_mc_init(struct radeon_device *rdev)
3198{
3199 int r;

--- 71 unchanged lines hidden (view full) ---

3271 /* Fence driver */
3272 r = radeon_fence_driver_init(rdev);
3273 if (r)
3274 return r;
3275 r = radeon_irq_kms_init(rdev);
3276 if (r)
3277 return r;
3278 /* Memory manager */
3206 radeon_atombios_fini(rdev);
3207 kfree(rdev->bios);
3208 rdev->bios = NULL;
3209}
3210
3211int r100_mc_init(struct radeon_device *rdev)
3212{
3213 int r;

--- 71 unchanged lines hidden (view full) ---

3285 /* Fence driver */
3286 r = radeon_fence_driver_init(rdev);
3287 if (r)
3288 return r;
3289 r = radeon_irq_kms_init(rdev);
3290 if (r)
3291 return r;
3292 /* Memory manager */
3279 r = radeon_object_init(rdev);
3293 r = radeon_bo_init(rdev);
3280 if (r)
3281 return r;
3282 if (rdev->flags & RADEON_IS_PCI) {
3283 r = r100_pci_gart_init(rdev);
3284 if (r)
3285 return r;
3286 }
3287 r100_set_safe_registers(rdev);

--- 16 unchanged lines hidden --- 		3294 if (r)
3295 return r;
3296 if (rdev->flags & RADEON_IS_PCI) {
3297 r = r100_pci_gart_init(rdev);
3298 if (r)
3299 return r;
3300 }
3301 r100_set_safe_registers(rdev);

--- 16 unchanged lines hidden ---