| nid.h (4bc22a1aa02a0aae97a905091727345085281e61) | nid.h (721604a15b934f0a8d1909acb8017f029128be2f) |
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| 1/* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the --- 208 unchanged lines hidden (view full) --- 217#define SCRATCH_REG3 0x850C 218#define SCRATCH_REG4 0x8510 219#define SCRATCH_REG5 0x8514 220#define SCRATCH_REG6 0x8518 221#define SCRATCH_REG7 0x851C 222#define SCRATCH_UMSK 0x8540 223#define SCRATCH_ADDR 0x8544 224#define CP_SEM_WAIT_TIMER 0x85BC | 1/* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the --- 208 unchanged lines hidden (view full) --- 217#define SCRATCH_REG3 0x850C 218#define SCRATCH_REG4 0x8510 219#define SCRATCH_REG5 0x8514 220#define SCRATCH_REG6 0x8518 221#define SCRATCH_REG7 0x851C 222#define SCRATCH_UMSK 0x8540 223#define SCRATCH_ADDR 0x8544 224#define CP_SEM_WAIT_TIMER 0x85BC |
| 225#define CP_COHER_CNTL2 0x85E8 |
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| 225#define CP_ME_CNTL 0x86D8 226#define CP_ME_HALT (1 << 28) 227#define CP_PFP_HALT (1 << 26) 228#define CP_RB2_RPTR 0x86f8 229#define CP_RB1_RPTR 0x86fc 230#define CP_RB0_RPTR 0x8700 231#define CP_RB_WPTR_DELAY 0x8704 232#define CP_MEQ_THRESHOLDS 0x8764 --- 220 unchanged lines hidden (view full) --- 453#define PACKET3_NOP 0x10 454#define PACKET3_SET_BASE 0x11 455#define PACKET3_CLEAR_STATE 0x12 456#define PACKET3_INDEX_BUFFER_SIZE 0x13 457#define PACKET3_DEALLOC_STATE 0x14 458#define PACKET3_DISPATCH_DIRECT 0x15 459#define PACKET3_DISPATCH_INDIRECT 0x16 460#define PACKET3_INDIRECT_BUFFER_END 0x17 | 226#define CP_ME_CNTL 0x86D8 227#define CP_ME_HALT (1 << 28) 228#define CP_PFP_HALT (1 << 26) 229#define CP_RB2_RPTR 0x86f8 230#define CP_RB1_RPTR 0x86fc 231#define CP_RB0_RPTR 0x8700 232#define CP_RB_WPTR_DELAY 0x8704 233#define CP_MEQ_THRESHOLDS 0x8764 --- 220 unchanged lines hidden (view full) --- 454#define PACKET3_NOP 0x10 455#define PACKET3_SET_BASE 0x11 456#define PACKET3_CLEAR_STATE 0x12 457#define PACKET3_INDEX_BUFFER_SIZE 0x13 458#define PACKET3_DEALLOC_STATE 0x14 459#define PACKET3_DISPATCH_DIRECT 0x15 460#define PACKET3_DISPATCH_INDIRECT 0x16 461#define PACKET3_INDIRECT_BUFFER_END 0x17 |
| 462#define PACKET3_MODE_CONTROL 0x18 |
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| 461#define PACKET3_SET_PREDICATION 0x20 462#define PACKET3_REG_RMW 0x21 463#define PACKET3_COND_EXEC 0x22 464#define PACKET3_PRED_EXEC 0x23 465#define PACKET3_DRAW_INDIRECT 0x24 466#define PACKET3_DRAW_INDEX_INDIRECT 0x25 467#define PACKET3_INDEX_BASE 0x26 468#define PACKET3_DRAW_INDEX_2 0x27 --- 103 unchanged lines hidden --- | 463#define PACKET3_SET_PREDICATION 0x20 464#define PACKET3_REG_RMW 0x21 465#define PACKET3_COND_EXEC 0x22 466#define PACKET3_PRED_EXEC 0x23 467#define PACKET3_DRAW_INDIRECT 0x24 468#define PACKET3_DRAW_INDEX_INDIRECT 0x25 469#define PACKET3_INDEX_BASE 0x26 470#define PACKET3_DRAW_INDEX_2 0x27 --- 103 unchanged lines hidden --- |