| ni.c (3c3d7cb1db4af176dab843f22ea092a4ef1eb989) | ni.c (ff212f25feb44a915ce9c0144faef7fae27a6e61) |
|---|---|
| 1/* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the --- 1628 unchanged lines hidden (view full) --- 1637 WREG32(cp_rb_base[i], ring->gpu_addr >> 8); 1638 } 1639 1640 for (i = 0; i < 3; ++i) { 1641 /* Initialize the ring buffer's read and write pointers */ 1642 ring = &rdev->ring[ridx[i]]; 1643 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA); 1644 | 1/* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the --- 1628 unchanged lines hidden (view full) --- 1637 WREG32(cp_rb_base[i], ring->gpu_addr >> 8); 1638 } 1639 1640 for (i = 0; i < 3; ++i) { 1641 /* Initialize the ring buffer's read and write pointers */ 1642 ring = &rdev->ring[ridx[i]]; 1643 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA); 1644 |
| 1645 ring->rptr = ring->wptr = 0; 1646 WREG32(cp_rb_rptr[i], ring->rptr); | 1645 ring->wptr = 0; 1646 WREG32(cp_rb_rptr[i], 0); |
| 1647 WREG32(cp_rb_wptr[i], ring->wptr); 1648 1649 mdelay(1); 1650 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA); 1651 } 1652 1653 /* start the rings */ 1654 cayman_cp_start(rdev); --- 257 unchanged lines hidden (view full) --- 1912 */ 1913bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1914{ 1915 u32 reset_mask = cayman_gpu_check_soft_reset(rdev); 1916 1917 if (!(reset_mask & (RADEON_RESET_GFX | 1918 RADEON_RESET_COMPUTE | 1919 RADEON_RESET_CP))) { | 1647 WREG32(cp_rb_wptr[i], ring->wptr); 1648 1649 mdelay(1); 1650 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA); 1651 } 1652 1653 /* start the rings */ 1654 cayman_cp_start(rdev); --- 257 unchanged lines hidden (view full) --- 1912 */ 1913bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1914{ 1915 u32 reset_mask = cayman_gpu_check_soft_reset(rdev); 1916 1917 if (!(reset_mask & (RADEON_RESET_GFX | 1918 RADEON_RESET_COMPUTE | 1919 RADEON_RESET_CP))) { |
| 1920 radeon_ring_lockup_update(ring); | 1920 radeon_ring_lockup_update(rdev, ring); |
| 1921 return false; 1922 } 1923 /* force CP activities */ 1924 radeon_ring_force_activity(rdev, ring); 1925 return radeon_ring_test_lockup(rdev, ring); 1926} 1927 1928static int cayman_startup(struct radeon_device *rdev) --- 578 unchanged lines hidden --- | 1921 return false; 1922 } 1923 /* force CP activities */ 1924 radeon_ring_force_activity(rdev, ring); 1925 return radeon_ring_test_lockup(rdev, ring); 1926} 1927 1928static int cayman_startup(struct radeon_device *rdev) --- 578 unchanged lines hidden --- |