| evergreend.h (e0273728564a395a13cfed70e34da4f2613d2d44) | evergreend.h (721604a15b934f0a8d1909acb8017f029128be2f) |
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| 1/* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the --- 228 unchanged lines hidden (view full) --- 237 238#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 239#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 240#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 241 242#define PA_CL_ENHANCE 0x8A14 243#define CLIP_VTX_REORDER_ENA (1 << 0) 244#define NUM_CLIP_SEQ(x) ((x) << 1) | 1/* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the --- 228 unchanged lines hidden (view full) --- 237 238#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 239#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 240#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 241 242#define PA_CL_ENHANCE 0x8A14 243#define CLIP_VTX_REORDER_ENA (1 << 0) 244#define NUM_CLIP_SEQ(x) ((x) << 1) |
| 245#define PA_SC_ENHANCE 0x8BF0 |
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| 245#define PA_SC_AA_CONFIG 0x28C04 246#define MSAA_NUM_SAMPLES_SHIFT 0 247#define MSAA_NUM_SAMPLES_MASK 0x3 248#define PA_SC_CLIPRECT_RULE 0x2820C 249#define PA_SC_EDGERULE 0x28230 250#define PA_SC_FIFO_SIZE 0x8BCC 251#define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 252#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) --- 61 unchanged lines hidden (view full) --- 314#define NUM_VS_GPRS(x) ((x) << 16) 315#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 316#define SQ_GPR_RESOURCE_MGMT_2 0x8C08 317#define NUM_GS_GPRS(x) ((x) << 0) 318#define NUM_ES_GPRS(x) ((x) << 16) 319#define SQ_GPR_RESOURCE_MGMT_3 0x8C0C 320#define NUM_HS_GPRS(x) ((x) << 0) 321#define NUM_LS_GPRS(x) ((x) << 16) | 246#define PA_SC_AA_CONFIG 0x28C04 247#define MSAA_NUM_SAMPLES_SHIFT 0 248#define MSAA_NUM_SAMPLES_MASK 0x3 249#define PA_SC_CLIPRECT_RULE 0x2820C 250#define PA_SC_EDGERULE 0x28230 251#define PA_SC_FIFO_SIZE 0x8BCC 252#define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 253#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) --- 61 unchanged lines hidden (view full) --- 315#define NUM_VS_GPRS(x) ((x) << 16) 316#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 317#define SQ_GPR_RESOURCE_MGMT_2 0x8C08 318#define NUM_GS_GPRS(x) ((x) << 0) 319#define NUM_ES_GPRS(x) ((x) << 16) 320#define SQ_GPR_RESOURCE_MGMT_3 0x8C0C 321#define NUM_HS_GPRS(x) ((x) << 0) 322#define NUM_LS_GPRS(x) ((x) << 16) |
| 323#define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10 324#define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14 |
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| 322#define SQ_THREAD_RESOURCE_MGMT 0x8C18 323#define NUM_PS_THREADS(x) ((x) << 0) 324#define NUM_VS_THREADS(x) ((x) << 8) 325#define NUM_GS_THREADS(x) ((x) << 16) 326#define NUM_ES_THREADS(x) ((x) << 24) 327#define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C 328#define NUM_HS_THREADS(x) ((x) << 0) 329#define NUM_LS_THREADS(x) ((x) << 8) 330#define SQ_STACK_RESOURCE_MGMT_1 0x8C20 331#define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 332#define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 333#define SQ_STACK_RESOURCE_MGMT_2 0x8C24 334#define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 335#define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 336#define SQ_STACK_RESOURCE_MGMT_3 0x8C28 337#define NUM_HS_STACK_ENTRIES(x) ((x) << 0) 338#define NUM_LS_STACK_ENTRIES(x) ((x) << 16) 339#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C | 325#define SQ_THREAD_RESOURCE_MGMT 0x8C18 326#define NUM_PS_THREADS(x) ((x) << 0) 327#define NUM_VS_THREADS(x) ((x) << 8) 328#define NUM_GS_THREADS(x) ((x) << 16) 329#define NUM_ES_THREADS(x) ((x) << 24) 330#define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C 331#define NUM_HS_THREADS(x) ((x) << 0) 332#define NUM_LS_THREADS(x) ((x) << 8) 333#define SQ_STACK_RESOURCE_MGMT_1 0x8C20 334#define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 335#define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 336#define SQ_STACK_RESOURCE_MGMT_2 0x8C24 337#define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 338#define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 339#define SQ_STACK_RESOURCE_MGMT_3 0x8C28 340#define NUM_HS_STACK_ENTRIES(x) ((x) << 0) 341#define NUM_LS_STACK_ENTRIES(x) ((x) << 16) 342#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C |
| 343#define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94 344#define SQ_STATIC_THREAD_MGMT_1 0x8E20 345#define SQ_STATIC_THREAD_MGMT_2 0x8E24 346#define SQ_STATIC_THREAD_MGMT_3 0x8E28 |
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| 340#define SQ_LDS_RESOURCE_MGMT 0x8E2C 341 342#define SQ_MS_FIFO_SIZES 0x8CF0 343#define CACHE_FIFO_SIZE(x) ((x) << 0) 344#define FETCH_FIFO_HIWATER(x) ((x) << 8) 345#define DONE_FIFO_HIWATER(x) ((x) << 16) 346#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 347 --- 338 unchanged lines hidden (view full) --- 686#define PACKET3_DRAW_INDEX_IMMD 0x2E 687#define PACKET3_NUM_INSTANCES 0x2F 688#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 689#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 690#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 691#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 692#define PACKET3_MEM_SEMAPHORE 0x39 693#define PACKET3_MPEG_INDEX 0x3A | 347#define SQ_LDS_RESOURCE_MGMT 0x8E2C 348 349#define SQ_MS_FIFO_SIZES 0x8CF0 350#define CACHE_FIFO_SIZE(x) ((x) << 0) 351#define FETCH_FIFO_HIWATER(x) ((x) << 8) 352#define DONE_FIFO_HIWATER(x) ((x) << 16) 353#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 354 --- 338 unchanged lines hidden (view full) --- 693#define PACKET3_DRAW_INDEX_IMMD 0x2E 694#define PACKET3_NUM_INSTANCES 0x2F 695#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 696#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 697#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 698#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 699#define PACKET3_MEM_SEMAPHORE 0x39 700#define PACKET3_MPEG_INDEX 0x3A |
| 701#define PACKET3_COPY_DW 0x3B |
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| 694#define PACKET3_WAIT_REG_MEM 0x3C 695#define PACKET3_MEM_WRITE 0x3D 696#define PACKET3_INDIRECT_BUFFER 0x32 697#define PACKET3_SURFACE_SYNC 0x43 698# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 699# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 700# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 701# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) --- 61 unchanged lines hidden (view full) --- 763#define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c 764#define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30) 765#define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3) 766#define SQ_TEX_VTX_INVALID_TEXTURE 0x0 767#define SQ_TEX_VTX_INVALID_BUFFER 0x1 768#define SQ_TEX_VTX_VALID_TEXTURE 0x2 769#define SQ_TEX_VTX_VALID_BUFFER 0x3 770 | 702#define PACKET3_WAIT_REG_MEM 0x3C 703#define PACKET3_MEM_WRITE 0x3D 704#define PACKET3_INDIRECT_BUFFER 0x32 705#define PACKET3_SURFACE_SYNC 0x43 706# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 707# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 708# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 709# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) --- 61 unchanged lines hidden (view full) --- 771#define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c 772#define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30) 773#define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3) 774#define SQ_TEX_VTX_INVALID_TEXTURE 0x0 775#define SQ_TEX_VTX_INVALID_BUFFER 0x1 776#define SQ_TEX_VTX_VALID_TEXTURE 0x2 777#define SQ_TEX_VTX_VALID_BUFFER 0x3 778 |
| 779#define VGT_VTX_VECT_EJECT_REG 0x88b0 780 |
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| 771#define SQ_CONST_MEM_BASE 0x8df8 772 773#define SQ_ESGS_RING_BASE 0x8c40 774#define SQ_ESGS_RING_SIZE 0x8c44 775#define SQ_GSVS_RING_BASE 0x8c48 776#define SQ_GSVS_RING_SIZE 0x8c4c 777#define SQ_ESTMP_RING_BASE 0x8c50 778#define SQ_ESTMP_RING_SIZE 0x8c54 --- 108 unchanged lines hidden (view full) --- 887#define SQ_ALU_CONST_CACHE_LS_12 0x28f70 888#define SQ_ALU_CONST_CACHE_LS_13 0x28f74 889#define SQ_ALU_CONST_CACHE_LS_14 0x28f78 890#define SQ_ALU_CONST_CACHE_LS_15 0x28f7c 891 892#define PA_SC_SCREEN_SCISSOR_TL 0x28030 893#define PA_SC_GENERIC_SCISSOR_TL 0x28240 894#define PA_SC_WINDOW_SCISSOR_TL 0x28204 | 781#define SQ_CONST_MEM_BASE 0x8df8 782 783#define SQ_ESGS_RING_BASE 0x8c40 784#define SQ_ESGS_RING_SIZE 0x8c44 785#define SQ_GSVS_RING_BASE 0x8c48 786#define SQ_GSVS_RING_SIZE 0x8c4c 787#define SQ_ESTMP_RING_BASE 0x8c50 788#define SQ_ESTMP_RING_SIZE 0x8c54 --- 108 unchanged lines hidden (view full) --- 897#define SQ_ALU_CONST_CACHE_LS_12 0x28f70 898#define SQ_ALU_CONST_CACHE_LS_13 0x28f74 899#define SQ_ALU_CONST_CACHE_LS_14 0x28f78 900#define SQ_ALU_CONST_CACHE_LS_15 0x28f7c 901 902#define PA_SC_SCREEN_SCISSOR_TL 0x28030 903#define PA_SC_GENERIC_SCISSOR_TL 0x28240 904#define PA_SC_WINDOW_SCISSOR_TL 0x28204 |
| 905 |
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| 895#define VGT_PRIMITIVE_TYPE 0x8958 | 906#define VGT_PRIMITIVE_TYPE 0x8958 |
| 907#define VGT_INDEX_TYPE 0x895C |
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| 896 | 908 |
| 909#define VGT_NUM_INDICES 0x8970 910 911#define VGT_COMPUTE_DIM_X 0x8990 912#define VGT_COMPUTE_DIM_Y 0x8994 913#define VGT_COMPUTE_DIM_Z 0x8998 914#define VGT_COMPUTE_START_X 0x899C 915#define VGT_COMPUTE_START_Y 0x89A0 916#define VGT_COMPUTE_START_Z 0x89A4 917#define VGT_COMPUTE_INDEX 0x89A8 918#define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC 919#define VGT_HS_OFFCHIP_PARAM 0x89B0 920 921#define DB_DEBUG 0x9830 922#define DB_DEBUG2 0x9834 923#define DB_DEBUG3 0x9838 924#define DB_DEBUG4 0x983C 925#define DB_WATERMARKS 0x9854 |
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| 897#define DB_DEPTH_CONTROL 0x28800 898#define DB_DEPTH_VIEW 0x28008 899#define DB_HTILE_DATA_BASE 0x28014 900#define DB_Z_INFO 0x28040 901# define Z_ARRAY_MODE(x) ((x) << 4) 902# define DB_TILE_SPLIT(x) (((x) & 0x7) << 8) 903# define DB_NUM_BANKS(x) (((x) & 0x3) << 12) 904# define DB_BANK_WIDTH(x) (((x) & 0x3) << 16) --- 279 unchanged lines hidden (view full) --- 1184# define SQ_VTCX_SEL_Y(x) ((x) << 6) 1185# define SQ_VTCX_SEL_Z(x) ((x) << 9) 1186# define SQ_VTCX_SEL_W(x) ((x) << 12) 1187#define SQ_VTX_CONSTANT_WORD4_0 0x30010 1188#define SQ_VTX_CONSTANT_WORD5_0 0x30014 1189#define SQ_VTX_CONSTANT_WORD6_0 0x30018 1190#define SQ_VTX_CONSTANT_WORD7_0 0x3001c 1191 | 926#define DB_DEPTH_CONTROL 0x28800 927#define DB_DEPTH_VIEW 0x28008 928#define DB_HTILE_DATA_BASE 0x28014 929#define DB_Z_INFO 0x28040 930# define Z_ARRAY_MODE(x) ((x) << 4) 931# define DB_TILE_SPLIT(x) (((x) & 0x7) << 8) 932# define DB_NUM_BANKS(x) (((x) & 0x3) << 12) 933# define DB_BANK_WIDTH(x) (((x) & 0x3) << 16) --- 279 unchanged lines hidden (view full) --- 1213# define SQ_VTCX_SEL_Y(x) ((x) << 6) 1214# define SQ_VTCX_SEL_Z(x) ((x) << 9) 1215# define SQ_VTCX_SEL_W(x) ((x) << 12) 1216#define SQ_VTX_CONSTANT_WORD4_0 0x30010 1217#define SQ_VTX_CONSTANT_WORD5_0 0x30014 1218#define SQ_VTX_CONSTANT_WORD6_0 0x30018 1219#define SQ_VTX_CONSTANT_WORD7_0 0x3001c 1220 |
| 1221#define TD_PS_BORDER_COLOR_INDEX 0xA400 1222#define TD_PS_BORDER_COLOR_RED 0xA404 1223#define TD_PS_BORDER_COLOR_GREEN 0xA408 1224#define TD_PS_BORDER_COLOR_BLUE 0xA40C 1225#define TD_PS_BORDER_COLOR_ALPHA 0xA410 1226#define TD_VS_BORDER_COLOR_INDEX 0xA414 1227#define TD_VS_BORDER_COLOR_RED 0xA418 1228#define TD_VS_BORDER_COLOR_GREEN 0xA41C 1229#define TD_VS_BORDER_COLOR_BLUE 0xA420 1230#define TD_VS_BORDER_COLOR_ALPHA 0xA424 1231#define TD_GS_BORDER_COLOR_INDEX 0xA428 1232#define TD_GS_BORDER_COLOR_RED 0xA42C 1233#define TD_GS_BORDER_COLOR_GREEN 0xA430 1234#define TD_GS_BORDER_COLOR_BLUE 0xA434 1235#define TD_GS_BORDER_COLOR_ALPHA 0xA438 1236#define TD_HS_BORDER_COLOR_INDEX 0xA43C 1237#define TD_HS_BORDER_COLOR_RED 0xA440 1238#define TD_HS_BORDER_COLOR_GREEN 0xA444 1239#define TD_HS_BORDER_COLOR_BLUE 0xA448 1240#define TD_HS_BORDER_COLOR_ALPHA 0xA44C 1241#define TD_LS_BORDER_COLOR_INDEX 0xA450 1242#define TD_LS_BORDER_COLOR_RED 0xA454 1243#define TD_LS_BORDER_COLOR_GREEN 0xA458 1244#define TD_LS_BORDER_COLOR_BLUE 0xA45C 1245#define TD_LS_BORDER_COLOR_ALPHA 0xA460 1246#define TD_CS_BORDER_COLOR_INDEX 0xA464 1247#define TD_CS_BORDER_COLOR_RED 0xA468 1248#define TD_CS_BORDER_COLOR_GREEN 0xA46C 1249#define TD_CS_BORDER_COLOR_BLUE 0xA470 1250#define TD_CS_BORDER_COLOR_ALPHA 0xA474 1251 |
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| 1192/* cayman 3D regs */ | 1252/* cayman 3D regs */ |
| 1193#define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B0 | 1253#define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4 1254#define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48 |
| 1194#define CAYMAN_DB_EQAA 0x28804 1195#define CAYMAN_DB_DEPTH_INFO 0x2803C 1196#define CAYMAN_PA_SC_AA_CONFIG 0x28BE0 1197#define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0 1198#define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7 1199#define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358 1200/* cayman packet3 addition */ 1201#define CAYMAN_PACKET3_DEALLOC_STATE 0x14 1202 1203#endif | 1255#define CAYMAN_DB_EQAA 0x28804 1256#define CAYMAN_DB_DEPTH_INFO 0x2803C 1257#define CAYMAN_PA_SC_AA_CONFIG 0x28BE0 1258#define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0 1259#define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7 1260#define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358 1261/* cayman packet3 addition */ 1262#define CAYMAN_PACKET3_DEALLOC_STATE 0x14 1263 1264#endif |