cik.c (a1d6f97c8cfa7c3554d0391c0b16505d1d97f380) cik.c (ff212f25feb44a915ce9c0144faef7fae27a6e61)
1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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4026
4027 mdelay(1);
4028 WREG32(CP_RB0_CNTL, tmp);
4029
4030 rb_addr = ring->gpu_addr >> 8;
4031 WREG32(CP_RB0_BASE, rb_addr);
4032 WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr));
4033
1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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4026
4027 mdelay(1);
4028 WREG32(CP_RB0_CNTL, tmp);
4029
4030 rb_addr = ring->gpu_addr >> 8;
4031 WREG32(CP_RB0_BASE, rb_addr);
4032 WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr));
4033
4034 ring->rptr = RREG32(CP_RB0_RPTR);
4035
4036 /* start the ring */
4037 cik_cp_gfx_start(rdev);
4038 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
4039 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
4040 if (r) {
4041 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
4042 return r;
4043 }

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4582 }
4583 WREG32(CP_HQD_PQ_DOORBELL_CONTROL,
4584 mqd->queue_state.cp_hqd_pq_doorbell_control);
4585
4586 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4587 rdev->ring[idx].wptr = 0;
4588 mqd->queue_state.cp_hqd_pq_wptr = rdev->ring[idx].wptr;
4589 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
4034 /* start the ring */
4035 cik_cp_gfx_start(rdev);
4036 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
4037 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
4038 if (r) {
4039 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
4040 return r;
4041 }

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4580 }
4581 WREG32(CP_HQD_PQ_DOORBELL_CONTROL,
4582 mqd->queue_state.cp_hqd_pq_doorbell_control);
4583
4584 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4585 rdev->ring[idx].wptr = 0;
4586 mqd->queue_state.cp_hqd_pq_wptr = rdev->ring[idx].wptr;
4587 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
4590 rdev->ring[idx].rptr = RREG32(CP_HQD_PQ_RPTR);
4591 mqd->queue_state.cp_hqd_pq_rptr = rdev->ring[idx].rptr;
4588 mqd->queue_state.cp_hqd_pq_rptr = RREG32(CP_HQD_PQ_RPTR);
4592
4593 /* set the vmid for the queue */
4594 mqd->queue_state.cp_hqd_vmid = 0;
4595 WREG32(CP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
4596
4597 /* activate the queue */
4598 mqd->queue_state.cp_hqd_active = 1;
4599 WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);

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5113 */
5114bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
5115{
5116 u32 reset_mask = cik_gpu_check_soft_reset(rdev);
5117
5118 if (!(reset_mask & (RADEON_RESET_GFX |
5119 RADEON_RESET_COMPUTE |
5120 RADEON_RESET_CP))) {
4589
4590 /* set the vmid for the queue */
4591 mqd->queue_state.cp_hqd_vmid = 0;
4592 WREG32(CP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
4593
4594 /* activate the queue */
4595 mqd->queue_state.cp_hqd_active = 1;
4596 WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);

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5110 */
5111bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
5112{
5113 u32 reset_mask = cik_gpu_check_soft_reset(rdev);
5114
5115 if (!(reset_mask & (RADEON_RESET_GFX |
5116 RADEON_RESET_COMPUTE |
5117 RADEON_RESET_CP))) {
5121 radeon_ring_lockup_update(ring);
5118 radeon_ring_lockup_update(rdev, ring);
5122 return false;
5123 }
5124 /* force CP activities */
5125 radeon_ring_force_activity(rdev, ring);
5126 return radeon_ring_test_lockup(rdev, ring);
5127}
5128
5129/* MC */

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5120 }
5121 /* force CP activities */
5122 radeon_ring_force_activity(rdev, ring);
5123 return radeon_ring_test_lockup(rdev, ring);
5124}
5125
5126/* MC */

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