cik.c (336879b1da97fffc097f77c6d6f818660f2826f0) cik.c (57d20a43c9b30663bdbacde8294a902edef35a84)
1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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3954
3955/**
3956 * cik_copy_cpdma - copy pages using the CP DMA engine
3957 *
3958 * @rdev: radeon_device pointer
3959 * @src_offset: src GPU address
3960 * @dst_offset: dst GPU address
3961 * @num_gpu_pages: number of GPU pages to xfer
1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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3954
3955/**
3956 * cik_copy_cpdma - copy pages using the CP DMA engine
3957 *
3958 * @rdev: radeon_device pointer
3959 * @src_offset: src GPU address
3960 * @dst_offset: dst GPU address
3961 * @num_gpu_pages: number of GPU pages to xfer
3962 * @fence: radeon fence object
3962 * @resv: reservation object to sync to
3963 *
3964 * Copy GPU paging using the CP DMA engine (CIK+).
3965 * Used by the radeon ttm implementation to move pages if
3966 * registered as the asic copy callback.
3967 */
3963 *
3964 * Copy GPU paging using the CP DMA engine (CIK+).
3965 * Used by the radeon ttm implementation to move pages if
3966 * registered as the asic copy callback.
3967 */
3968int cik_copy_cpdma(struct radeon_device *rdev,
3969 uint64_t src_offset, uint64_t dst_offset,
3970 unsigned num_gpu_pages,
3971 struct radeon_fence **fence)
3968struct radeon_fence *cik_copy_cpdma(struct radeon_device *rdev,
3969 uint64_t src_offset, uint64_t dst_offset,
3970 unsigned num_gpu_pages,
3971 struct reservation_object *resv)
3972{
3973 struct radeon_semaphore *sem = NULL;
3972{
3973 struct radeon_semaphore *sem = NULL;
3974 struct radeon_fence *fence;
3974 int ring_index = rdev->asic->copy.blit_ring_index;
3975 struct radeon_ring *ring = &rdev->ring[ring_index];
3976 u32 size_in_bytes, cur_size_in_bytes, control;
3977 int i, num_loops;
3978 int r = 0;
3979
3980 r = radeon_semaphore_create(rdev, &sem);
3981 if (r) {
3982 DRM_ERROR("radeon: moving bo (%d).\n", r);
3975 int ring_index = rdev->asic->copy.blit_ring_index;
3976 struct radeon_ring *ring = &rdev->ring[ring_index];
3977 u32 size_in_bytes, cur_size_in_bytes, control;
3978 int i, num_loops;
3979 int r = 0;
3980
3981 r = radeon_semaphore_create(rdev, &sem);
3982 if (r) {
3983 DRM_ERROR("radeon: moving bo (%d).\n", r);
3983 return r;
3984 return ERR_PTR(r);
3984 }
3985
3986 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
3987 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
3988 r = radeon_ring_lock(rdev, ring, num_loops * 7 + 18);
3989 if (r) {
3990 DRM_ERROR("radeon: moving bo (%d).\n", r);
3991 radeon_semaphore_free(rdev, &sem, NULL);
3985 }
3986
3987 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
3988 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
3989 r = radeon_ring_lock(rdev, ring, num_loops * 7 + 18);
3990 if (r) {
3991 DRM_ERROR("radeon: moving bo (%d).\n", r);
3992 radeon_semaphore_free(rdev, &sem, NULL);
3992 return r;
3993 return ERR_PTR(r);
3993 }
3994
3994 }
3995
3995 radeon_semaphore_sync_to(sem, *fence);
3996 radeon_semaphore_sync_resv(sem, resv, false);
3996 radeon_semaphore_sync_rings(rdev, sem, ring->idx);
3997
3998 for (i = 0; i < num_loops; i++) {
3999 cur_size_in_bytes = size_in_bytes;
4000 if (cur_size_in_bytes > 0x1fffff)
4001 cur_size_in_bytes = 0x1fffff;
4002 size_in_bytes -= cur_size_in_bytes;
4003 control = 0;

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4009 radeon_ring_write(ring, upper_32_bits(src_offset));
4010 radeon_ring_write(ring, lower_32_bits(dst_offset));
4011 radeon_ring_write(ring, upper_32_bits(dst_offset));
4012 radeon_ring_write(ring, cur_size_in_bytes);
4013 src_offset += cur_size_in_bytes;
4014 dst_offset += cur_size_in_bytes;
4015 }
4016
3997 radeon_semaphore_sync_rings(rdev, sem, ring->idx);
3998
3999 for (i = 0; i < num_loops; i++) {
4000 cur_size_in_bytes = size_in_bytes;
4001 if (cur_size_in_bytes > 0x1fffff)
4002 cur_size_in_bytes = 0x1fffff;
4003 size_in_bytes -= cur_size_in_bytes;
4004 control = 0;

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4010 radeon_ring_write(ring, upper_32_bits(src_offset));
4011 radeon_ring_write(ring, lower_32_bits(dst_offset));
4012 radeon_ring_write(ring, upper_32_bits(dst_offset));
4013 radeon_ring_write(ring, cur_size_in_bytes);
4014 src_offset += cur_size_in_bytes;
4015 dst_offset += cur_size_in_bytes;
4016 }
4017
4017 r = radeon_fence_emit(rdev, fence, ring->idx);
4018 r = radeon_fence_emit(rdev, &fence, ring->idx);
4018 if (r) {
4019 radeon_ring_unlock_undo(rdev, ring);
4020 radeon_semaphore_free(rdev, &sem, NULL);
4019 if (r) {
4020 radeon_ring_unlock_undo(rdev, ring);
4021 radeon_semaphore_free(rdev, &sem, NULL);
4021 return r;
4022 return ERR_PTR(r);
4022 }
4023
4024 radeon_ring_unlock_commit(rdev, ring, false);
4023 }
4024
4025 radeon_ring_unlock_commit(rdev, ring, false);
4025 radeon_semaphore_free(rdev, &sem, *fence);
4026 radeon_semaphore_free(rdev, &sem, fence);
4026
4027
4027 return r;
4028 return fence;
4028}
4029
4030/*
4031 * IB stuff
4032 */
4033/**
4034 * cik_ring_ib_execute - emit an IB (Indirect Buffer) on the gfx ring
4035 *

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4030
4031/*
4032 * IB stuff
4033 */
4034/**
4035 * cik_ring_ib_execute - emit an IB (Indirect Buffer) on the gfx ring
4036 *

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