cik.c (1e9a328e4b35af22c23ce9357c2c2a77159e74bb) cik.c (4c0ab318a18b86b80f604410e8ed10bb59f0d7eb)
1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

--- 1613 unchanged lines hidden (view full) ---

1622 0x88c4, 0x001f3ae3, 0x00000082,
1623 0x88d4, 0x0000001f, 0x00000010,
1624 0x30934, 0xffffffff, 0x00000000
1625};
1626
1627
1628static void cik_init_golden_registers(struct radeon_device *rdev)
1629{
1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

--- 1613 unchanged lines hidden (view full) ---

1622 0x88c4, 0x001f3ae3, 0x00000082,
1623 0x88d4, 0x0000001f, 0x00000010,
1624 0x30934, 0xffffffff, 0x00000000
1625};
1626
1627
1628static void cik_init_golden_registers(struct radeon_device *rdev)
1629{
1630 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
1631 mutex_lock(&rdev->grbm_idx_mutex);
1632 switch (rdev->family) {
1633 case CHIP_BONAIRE:
1634 radeon_program_register_sequence(rdev,
1635 bonaire_mgcg_cgcg_init,
1636 (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
1637 radeon_program_register_sequence(rdev,
1638 bonaire_golden_registers,
1639 (const u32)ARRAY_SIZE(bonaire_golden_registers));

--- 58 unchanged lines hidden (view full) ---

1698 (const u32)ARRAY_SIZE(hawaii_golden_common_registers));
1699 radeon_program_register_sequence(rdev,
1700 hawaii_golden_spm_registers,
1701 (const u32)ARRAY_SIZE(hawaii_golden_spm_registers));
1702 break;
1703 default:
1704 break;
1705 }
1630 switch (rdev->family) {
1631 case CHIP_BONAIRE:
1632 radeon_program_register_sequence(rdev,
1633 bonaire_mgcg_cgcg_init,
1634 (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
1635 radeon_program_register_sequence(rdev,
1636 bonaire_golden_registers,
1637 (const u32)ARRAY_SIZE(bonaire_golden_registers));

--- 58 unchanged lines hidden (view full) ---

1696 (const u32)ARRAY_SIZE(hawaii_golden_common_registers));
1697 radeon_program_register_sequence(rdev,
1698 hawaii_golden_spm_registers,
1699 (const u32)ARRAY_SIZE(hawaii_golden_spm_registers));
1700 break;
1701 default:
1702 break;
1703 }
1706 mutex_unlock(&rdev->grbm_idx_mutex);
1707}
1708
1709/**
1710 * cik_get_xclk - get the xclk
1711 *
1712 * @rdev: radeon_device pointer
1713 *
1714 * Returns the reference clock used by the gfx engine

--- 1400 unchanged lines hidden (view full) ---

3115 u32 se_num, u32 sh_per_se,
3116 u32 max_rb_num_per_se)
3117{
3118 int i, j;
3119 u32 data, mask;
3120 u32 disabled_rbs = 0;
3121 u32 enabled_rbs = 0;
3122
1704}
1705
1706/**
1707 * cik_get_xclk - get the xclk
1708 *
1709 * @rdev: radeon_device pointer
1710 *
1711 * Returns the reference clock used by the gfx engine

--- 1400 unchanged lines hidden (view full) ---

3112 u32 se_num, u32 sh_per_se,
3113 u32 max_rb_num_per_se)
3114{
3115 int i, j;
3116 u32 data, mask;
3117 u32 disabled_rbs = 0;
3118 u32 enabled_rbs = 0;
3119
3123 mutex_lock(&rdev->grbm_idx_mutex);
3124 for (i = 0; i < se_num; i++) {
3125 for (j = 0; j < sh_per_se; j++) {
3126 cik_select_se_sh(rdev, i, j);
3127 data = cik_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
3128 if (rdev->family == CHIP_HAWAII)
3129 disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
3130 else
3131 disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH);
3132 }
3133 }
3134 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3120 for (i = 0; i < se_num; i++) {
3121 for (j = 0; j < sh_per_se; j++) {
3122 cik_select_se_sh(rdev, i, j);
3123 data = cik_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
3124 if (rdev->family == CHIP_HAWAII)
3125 disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
3126 else
3127 disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH);
3128 }
3129 }
3130 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3135 mutex_unlock(&rdev->grbm_idx_mutex);
3136
3137 mask = 1;
3138 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
3139 if (!(disabled_rbs & mask))
3140 enabled_rbs |= mask;
3141 mask <<= 1;
3142 }
3143
3144 rdev->config.cik.backend_enable_mask = enabled_rbs;
3145
3131
3132 mask = 1;
3133 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
3134 if (!(disabled_rbs & mask))
3135 enabled_rbs |= mask;
3136 mask <<= 1;
3137 }
3138
3139 rdev->config.cik.backend_enable_mask = enabled_rbs;
3140
3146 mutex_lock(&rdev->grbm_idx_mutex);
3147 for (i = 0; i < se_num; i++) {
3148 cik_select_se_sh(rdev, i, 0xffffffff);
3149 data = 0;
3150 for (j = 0; j < sh_per_se; j++) {
3151 switch (enabled_rbs & 3) {
3152 case 0:
3153 if (j == 0)
3154 data |= PKR_MAP(RASTER_CONFIG_RB_MAP_3);

--- 11 unchanged lines hidden (view full) ---

3166 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
3167 break;
3168 }
3169 enabled_rbs >>= 2;
3170 }
3171 WREG32(PA_SC_RASTER_CONFIG, data);
3172 }
3173 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3141 for (i = 0; i < se_num; i++) {
3142 cik_select_se_sh(rdev, i, 0xffffffff);
3143 data = 0;
3144 for (j = 0; j < sh_per_se; j++) {
3145 switch (enabled_rbs & 3) {
3146 case 0:
3147 if (j == 0)
3148 data |= PKR_MAP(RASTER_CONFIG_RB_MAP_3);

--- 11 unchanged lines hidden (view full) ---

3160 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
3161 break;
3162 }
3163 enabled_rbs >>= 2;
3164 }
3165 WREG32(PA_SC_RASTER_CONFIG, data);
3166 }
3167 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3174 mutex_unlock(&rdev->grbm_idx_mutex);
3175}
3176
3177/**
3178 * cik_gpu_init - setup the 3D engine
3179 *
3180 * @rdev: radeon_device pointer
3181 *
3182 * Configures the 3D engine and tiling configuration

--- 203 unchanged lines hidden (view full) ---

3386 rdev->config.cik.active_cus +=
3387 hweight32(cik_get_cu_active_bitmap(rdev, i, j));
3388 }
3389 }
3390
3391 /* set HW defaults for 3D engine */
3392 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
3393
3168}
3169
3170/**
3171 * cik_gpu_init - setup the 3D engine
3172 *
3173 * @rdev: radeon_device pointer
3174 *
3175 * Configures the 3D engine and tiling configuration

--- 203 unchanged lines hidden (view full) ---

3379 rdev->config.cik.active_cus +=
3380 hweight32(cik_get_cu_active_bitmap(rdev, i, j));
3381 }
3382 }
3383
3384 /* set HW defaults for 3D engine */
3385 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
3386
3394 mutex_lock(&rdev->grbm_idx_mutex);
3395 /*
3396 * making sure that the following register writes will be broadcasted
3397 * to all the shaders
3398 */
3399 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3400 WREG32(SX_DEBUG_1, 0x20);
3401
3402 WREG32(TA_CNTL_AUX, 0x00010000);
3403
3404 tmp = RREG32(SPI_CONFIG_CNTL);
3405 tmp |= 0x03000000;
3406 WREG32(SPI_CONFIG_CNTL, tmp);
3407

--- 39 unchanged lines hidden (view full) ---

3447 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
3448 WREG32(HDP_MISC_CNTL, tmp);
3449
3450 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
3451 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
3452
3453 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
3454 WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER);
3387 WREG32(SX_DEBUG_1, 0x20);
3388
3389 WREG32(TA_CNTL_AUX, 0x00010000);
3390
3391 tmp = RREG32(SPI_CONFIG_CNTL);
3392 tmp |= 0x03000000;
3393 WREG32(SPI_CONFIG_CNTL, tmp);
3394

--- 39 unchanged lines hidden (view full) ---

3434 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
3435 WREG32(HDP_MISC_CNTL, tmp);
3436
3437 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
3438 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
3439
3440 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
3441 WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER);
3455 mutex_unlock(&rdev->grbm_idx_mutex);
3456
3457 udelay(50);
3458}
3459
3460/*
3461 * GPU scratch registers helpers function.
3462 */
3463/**

--- 2361 unchanged lines hidden (view full) ---

5825 WREG32(RLC_LB_CNTL, tmp);
5826}
5827
5828static void cik_wait_for_rlc_serdes(struct radeon_device *rdev)
5829{
5830 u32 i, j, k;
5831 u32 mask;
5832
3442
3443 udelay(50);
3444}
3445
3446/*
3447 * GPU scratch registers helpers function.
3448 */
3449/**

--- 2361 unchanged lines hidden (view full) ---

5811 WREG32(RLC_LB_CNTL, tmp);
5812}
5813
5814static void cik_wait_for_rlc_serdes(struct radeon_device *rdev)
5815{
5816 u32 i, j, k;
5817 u32 mask;
5818
5833 mutex_lock(&rdev->grbm_idx_mutex);
5834 for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
5835 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
5836 cik_select_se_sh(rdev, i, j);
5837 for (k = 0; k < rdev->usec_timeout; k++) {
5838 if (RREG32(RLC_SERDES_CU_MASTER_BUSY) == 0)
5839 break;
5840 udelay(1);
5841 }
5842 }
5843 }
5844 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5819 for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
5820 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
5821 cik_select_se_sh(rdev, i, j);
5822 for (k = 0; k < rdev->usec_timeout; k++) {
5823 if (RREG32(RLC_SERDES_CU_MASTER_BUSY) == 0)
5824 break;
5825 udelay(1);
5826 }
5827 }
5828 }
5829 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5845 mutex_unlock(&rdev->grbm_idx_mutex);
5846
5847 mask = SE_MASTER_BUSY_MASK | GC_MASTER_BUSY | TC0_MASTER_BUSY | TC1_MASTER_BUSY;
5848 for (k = 0; k < rdev->usec_timeout; k++) {
5849 if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
5850 break;
5851 udelay(1);
5852 }
5853}

--- 118 unchanged lines hidden (view full) ---

5972
5973 cik_init_pg(rdev);
5974
5975 cik_init_cg(rdev);
5976
5977 WREG32(RLC_LB_CNTR_INIT, 0);
5978 WREG32(RLC_LB_CNTR_MAX, 0x00008000);
5979
5830
5831 mask = SE_MASTER_BUSY_MASK | GC_MASTER_BUSY | TC0_MASTER_BUSY | TC1_MASTER_BUSY;
5832 for (k = 0; k < rdev->usec_timeout; k++) {
5833 if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
5834 break;
5835 udelay(1);
5836 }
5837}

--- 118 unchanged lines hidden (view full) ---

5956
5957 cik_init_pg(rdev);
5958
5959 cik_init_cg(rdev);
5960
5961 WREG32(RLC_LB_CNTR_INIT, 0);
5962 WREG32(RLC_LB_CNTR_MAX, 0x00008000);
5963
5980 mutex_lock(&rdev->grbm_idx_mutex);
5981 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5982 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
5983 WREG32(RLC_LB_PARAMS, 0x00600408);
5984 WREG32(RLC_LB_CNTL, 0x80000004);
5964 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5965 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
5966 WREG32(RLC_LB_PARAMS, 0x00600408);
5967 WREG32(RLC_LB_CNTL, 0x80000004);
5985 mutex_unlock(&rdev->grbm_idx_mutex);
5986
5987 WREG32(RLC_MC_CNTL, 0);
5988 WREG32(RLC_UCODE_CNTL, 0);
5989
5990 if (rdev->new_fw) {
5991 const struct rlc_firmware_header_v1_0 *hdr =
5992 (const struct rlc_firmware_header_v1_0 *)rdev->rlc_fw->data;
5993 const __le32 *fw_data = (const __le32 *)

--- 50 unchanged lines hidden (view full) ---

6044
6045 orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
6046
6047 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) {
6048 cik_enable_gui_idle_interrupt(rdev, true);
6049
6050 tmp = cik_halt_rlc(rdev);
6051
5968
5969 WREG32(RLC_MC_CNTL, 0);
5970 WREG32(RLC_UCODE_CNTL, 0);
5971
5972 if (rdev->new_fw) {
5973 const struct rlc_firmware_header_v1_0 *hdr =
5974 (const struct rlc_firmware_header_v1_0 *)rdev->rlc_fw->data;
5975 const __le32 *fw_data = (const __le32 *)

--- 50 unchanged lines hidden (view full) ---

6026
6027 orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
6028
6029 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) {
6030 cik_enable_gui_idle_interrupt(rdev, true);
6031
6032 tmp = cik_halt_rlc(rdev);
6033
6052 mutex_lock(&rdev->grbm_idx_mutex);
6053 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
6054 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
6055 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
6056 tmp2 = BPM_ADDR_MASK | CGCG_OVERRIDE_0 | CGLS_ENABLE;
6057 WREG32(RLC_SERDES_WR_CTRL, tmp2);
6034 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
6035 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
6036 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
6037 tmp2 = BPM_ADDR_MASK | CGCG_OVERRIDE_0 | CGLS_ENABLE;
6038 WREG32(RLC_SERDES_WR_CTRL, tmp2);
6058 mutex_unlock(&rdev->grbm_idx_mutex);
6059
6060 cik_update_rlc(rdev, tmp);
6061
6062 data |= CGCG_EN | CGLS_EN;
6063 } else {
6064 cik_enable_gui_idle_interrupt(rdev, false);
6065
6066 RREG32(CB_CGTT_SCLK_CTRL);

--- 26 unchanged lines hidden (view full) ---

6093 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
6094 data |= 0x00000001;
6095 data &= 0xfffffffd;
6096 if (orig != data)
6097 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
6098
6099 tmp = cik_halt_rlc(rdev);
6100
6039
6040 cik_update_rlc(rdev, tmp);
6041
6042 data |= CGCG_EN | CGLS_EN;
6043 } else {
6044 cik_enable_gui_idle_interrupt(rdev, false);
6045
6046 RREG32(CB_CGTT_SCLK_CTRL);

--- 26 unchanged lines hidden (view full) ---

6073 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
6074 data |= 0x00000001;
6075 data &= 0xfffffffd;
6076 if (orig != data)
6077 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
6078
6079 tmp = cik_halt_rlc(rdev);
6080
6101 mutex_lock(&rdev->grbm_idx_mutex);
6102 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
6103 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
6104 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
6105 data = BPM_ADDR_MASK | MGCG_OVERRIDE_0;
6106 WREG32(RLC_SERDES_WR_CTRL, data);
6081 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
6082 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
6083 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
6084 data = BPM_ADDR_MASK | MGCG_OVERRIDE_0;
6085 WREG32(RLC_SERDES_WR_CTRL, data);
6107 mutex_unlock(&rdev->grbm_idx_mutex);
6108
6109 cik_update_rlc(rdev, tmp);
6110
6111 if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGTS) {
6112 orig = data = RREG32(CGTS_SM_CTRL_REG);
6113 data &= ~SM_MODE_MASK;
6114 data |= SM_MODE(0x2);
6115 data |= SM_MODE_ENABLE;

--- 27 unchanged lines hidden (view full) ---

6143
6144 orig = data = RREG32(CGTS_SM_CTRL_REG);
6145 data |= CGTS_OVERRIDE | CGTS_LS_OVERRIDE;
6146 if (orig != data)
6147 WREG32(CGTS_SM_CTRL_REG, data);
6148
6149 tmp = cik_halt_rlc(rdev);
6150
6086
6087 cik_update_rlc(rdev, tmp);
6088
6089 if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGTS) {
6090 orig = data = RREG32(CGTS_SM_CTRL_REG);
6091 data &= ~SM_MODE_MASK;
6092 data |= SM_MODE(0x2);
6093 data |= SM_MODE_ENABLE;

--- 27 unchanged lines hidden (view full) ---

6121
6122 orig = data = RREG32(CGTS_SM_CTRL_REG);
6123 data |= CGTS_OVERRIDE | CGTS_LS_OVERRIDE;
6124 if (orig != data)
6125 WREG32(CGTS_SM_CTRL_REG, data);
6126
6127 tmp = cik_halt_rlc(rdev);
6128
6151 mutex_lock(&rdev->grbm_idx_mutex);
6152 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
6153 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
6154 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
6155 data = BPM_ADDR_MASK | MGCG_OVERRIDE_1;
6156 WREG32(RLC_SERDES_WR_CTRL, data);
6129 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
6130 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
6131 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
6132 data = BPM_ADDR_MASK | MGCG_OVERRIDE_1;
6133 WREG32(RLC_SERDES_WR_CTRL, data);
6157 mutex_unlock(&rdev->grbm_idx_mutex);
6158
6159 cik_update_rlc(rdev, tmp);
6160 }
6161}
6162
6163static const u32 mc_cg_registers[] =
6164{
6165 MC_HUB_MISC_HUB_CG,

--- 412 unchanged lines hidden (view full) ---

6578 }
6579}
6580
6581static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh)
6582{
6583 u32 mask = 0, tmp, tmp1;
6584 int i;
6585
6134
6135 cik_update_rlc(rdev, tmp);
6136 }
6137}
6138
6139static const u32 mc_cg_registers[] =
6140{
6141 MC_HUB_MISC_HUB_CG,

--- 412 unchanged lines hidden (view full) ---

6554 }
6555}
6556
6557static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh)
6558{
6559 u32 mask = 0, tmp, tmp1;
6560 int i;
6561
6586 mutex_lock(&rdev->grbm_idx_mutex);
6587 cik_select_se_sh(rdev, se, sh);
6588 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
6589 tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
6590 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
6562 cik_select_se_sh(rdev, se, sh);
6563 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
6564 tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
6565 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
6591 mutex_unlock(&rdev->grbm_idx_mutex);
6592
6593 tmp &= 0xffff0000;
6594
6595 tmp |= tmp1;
6596 tmp >>= 16;
6597
6598 for (i = 0; i < rdev->config.cik.max_cu_per_sh; i ++) {
6599 mask <<= 1;

--- 3186 unchanged lines hidden --- 		6566
6567 tmp &= 0xffff0000;
6568
6569 tmp |= tmp1;
6570 tmp >>= 16;
6571
6572 for (i = 0; i < rdev->config.cik.max_cu_per_sh; i ++) {
6573 mask <<= 1;

--- 3186 unchanged lines hidden ---