disp.c (9793083f1dd9da8dda0ef68e90934dd7d112203b) disp.c (f530bc60a30bee47ff51b7fb71511fdd058b774a)
1/*
2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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43#include <drm/drm_vblank.h>
44
45#include <nvif/push507c.h>
46
47#include <nvif/class.h>
48#include <nvif/cl0002.h>
49#include <nvif/cl5070.h>
50#include <nvif/event.h>
1/*
2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

--- 34 unchanged lines hidden (view full) ---

43#include <drm/drm_vblank.h>
44
45#include <nvif/push507c.h>
46
47#include <nvif/class.h>
48#include <nvif/cl0002.h>
49#include <nvif/cl5070.h>
50#include <nvif/event.h>
51#include <nvif/if0012.h>
51#include <nvif/if0014.h>
52#include <nvif/timer.h>
53
54#include <nvhw/class/cl507c.h>
55#include <nvhw/class/cl507d.h>
56#include <nvhw/class/cl837d.h>
57#include <nvhw/class/cl887d.h>
58#include <nvhw/class/cl907d.h>

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740
741 nv50_audio_component_eld_notify(drm->audio.component, outp->or.id, nv_crtc->index);
742}
743
744/******************************************************************************
745 * HDMI
746 *****************************************************************************/
747static void
52#include <nvif/if0014.h>
53#include <nvif/timer.h>
54
55#include <nvhw/class/cl507c.h>
56#include <nvhw/class/cl507d.h>
57#include <nvhw/class/cl837d.h>
58#include <nvhw/class/cl887d.h>
59#include <nvhw/class/cl907d.h>

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741
742 nv50_audio_component_eld_notify(drm->audio.component, outp->or.id, nv_crtc->index);
743}
744
745/******************************************************************************
746 * HDMI
747 *****************************************************************************/
748static void
748nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
749{
750 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
751 struct nv50_disp *disp = nv50_disp(encoder->dev);
752 struct {
753 struct nv50_disp_mthd_v1 base;
754 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
755 } args = {
756 .base.version = 1,
757 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
758 .base.hasht = nv_encoder->dcb->hasht,
759 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
760 (0x0100 << nv_crtc->index),
761 };
762
763 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
764}
765
766static void
767nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
768 struct nouveau_connector *nv_connector, struct drm_atomic_state *state,
749nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
750 struct nouveau_connector *nv_connector, struct drm_atomic_state *state,
769 struct drm_display_mode *mode)
751 struct drm_display_mode *mode, bool hda)
770{
771 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
772 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
752{
753 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
754 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
773 struct nv50_disp *disp = nv50_disp(encoder->dev);
774 struct {
775 struct nv50_disp_mthd_v1 base;
776 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
777 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
778 } args = {
779 .base.version = 1,
780 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
781 .base.hasht = nv_encoder->dcb->hasht,
782 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
783 (0x0100 << nv_crtc->index),
784 .pwr.state = 1,
785 .pwr.rekey = 56, /* binary driver, and tegra, constant */
786 };
787 struct drm_hdmi_info *hdmi;
755 struct drm_hdmi_info *hdmi = &nv_connector->base.display_info.hdmi;
756 union hdmi_infoframe infoframe;
757 const u8 rekey = 56; /* binary driver, and tegra, constant */
758 u8 config, scdc = 0;
788 u32 max_ac_packet;
759 u32 max_ac_packet;
789 union hdmi_infoframe avi_frame;
790 union hdmi_infoframe vendor_frame;
791 bool high_tmds_clock_ratio = false, scrambling = false;
792 u8 config;
793 int ret;
794 int size;
760 struct {
761 struct nvif_outp_infoframe_v0 infoframe;
762 u8 data[17];
763 } args;
764 int ret, size;
795
765
796 if (!drm_detect_hdmi_monitor(nv_connector->edid))
797 return;
798
799 hdmi = &nv_connector->base.display_info.hdmi;
800
801 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
802 &nv_connector->base, mode);
803 if (!ret) {
804 drm_hdmi_avi_infoframe_quant_range(&avi_frame.avi,
805 &nv_connector->base, mode,
806 HDMI_QUANTIZATION_RANGE_FULL);
807 /* We have an AVI InfoFrame, populate it to the display */
808 args.pwr.avi_infoframe_length
809 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
810 }
811
812 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
813 &nv_connector->base, mode);
814 if (!ret) {
815 /* We have a Vendor InfoFrame, populate it to the display */
816 args.pwr.vendor_infoframe_length
817 = hdmi_infoframe_pack(&vendor_frame,
818 args.infoframes
819 + args.pwr.avi_infoframe_length,
820 17);
821 }
822
823 max_ac_packet = mode->htotal - mode->hdisplay;
766 max_ac_packet = mode->htotal - mode->hdisplay;
824 max_ac_packet -= args.pwr.rekey;
767 max_ac_packet -= rekey;
825 max_ac_packet -= 18; /* constant from tegra */
768 max_ac_packet -= 18; /* constant from tegra */
826 args.pwr.max_ac_packet = max_ac_packet / 32;
769 max_ac_packet /= 32;
827
828 if (hdmi->scdc.scrambling.supported) {
770
771 if (hdmi->scdc.scrambling.supported) {
829 high_tmds_clock_ratio = mode->clock > 340000;
830 scrambling = high_tmds_clock_ratio ||
831 hdmi->scdc.scrambling.low_rates;
832 }
772 const bool high_tmds_clock_ratio = mode->clock > 340000;
833
773
834 args.pwr.scdc =
835 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
836 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
774 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
775 if (ret < 0) {
776 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
777 return;
778 }
837
779
838 size = sizeof(args.base)
839 + sizeof(args.pwr)
840 + args.pwr.avi_infoframe_length
841 + args.pwr.vendor_infoframe_length;
842 nvif_mthd(&disp->disp->object, 0, &args, size);
780 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
781 if (high_tmds_clock_ratio || hdmi->scdc.scrambling.low_rates)
782 config |= SCDC_SCRAMBLING_ENABLE;
783 if (high_tmds_clock_ratio)
784 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
843
785
844 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode);
786 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
787 if (ret < 0)
788 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
789 config, ret);
845
790
846 /* If SCDC is supported by the downstream monitor, update
847 * divider / scrambling settings to what we programmed above.
848 */
849 if (!hdmi->scdc.scrambling.supported)
850 return;
791 if (high_tmds_clock_ratio || hdmi->scdc.scrambling.low_rates)
792 scdc |= NVIF_OUTP_ACQUIRE_V0_TMDS_HDMI_SCDC_SCRAMBLE;
793 if (high_tmds_clock_ratio)
794 scdc |= NVIF_OUTP_ACQUIRE_V0_TMDS_HDMI_SCDC_DIV_BY_4;
795 }
851
796
852 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
853 if (ret < 0) {
854 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
797 ret = nvif_outp_acquire_tmds(&nv_encoder->outp, nv_crtc->index, true,
798 max_ac_packet, rekey, scdc, hda);
799 if (ret)
855 return;
800 return;
801
802 /* AVI InfoFrame. */
803 args.infoframe.version = 0;
804 args.infoframe.head = nv_crtc->index;
805
806 if (!drm_hdmi_avi_infoframe_from_display_mode(&infoframe.avi, &nv_connector->base, mode)) {
807 drm_hdmi_avi_infoframe_quant_range(&infoframe.avi, &nv_connector->base, mode,
808 HDMI_QUANTIZATION_RANGE_FULL);
809
810 size = hdmi_infoframe_pack(&infoframe, args.data, 17);
811 } else {
812 size = 0;
856 }
813 }
857 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
858 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
859 config |= SCDC_SCRAMBLING_ENABLE * scrambling;
860 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
861 if (ret < 0)
862 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
863 config, ret);
814
815 nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_AVI, &args.infoframe, size);
816
817 /* Vendor InfoFrame. */
818 if (!drm_hdmi_vendor_infoframe_from_display_mode(&infoframe.vendor.hdmi,
819 &nv_connector->base, mode))
820 size = hdmi_infoframe_pack(&infoframe, args.data, 17);
821 else
822 size = 0;
823
824 nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_VSI, &args.infoframe, size);
825
826 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode);
864}
865
866/******************************************************************************
867 * MST
868 *****************************************************************************/
869#define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
870#define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
871#define nv50_msto(p) container_of((p), struct nv50_msto, encoder)

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1617 pwr &= ~DP_SET_POWER_MASK;
1618 pwr |= DP_SET_POWER_D3;
1619 drm_dp_dpcd_writeb(aux, DP_SET_POWER, pwr);
1620 }
1621 }
1622
1623 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1624 nv50_audio_disable(encoder, nv_crtc);
827}
828
829/******************************************************************************
830 * MST
831 *****************************************************************************/
832#define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
833#define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
834#define nv50_msto(p) container_of((p), struct nv50_msto, encoder)

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1580 pwr &= ~DP_SET_POWER_MASK;
1581 pwr |= DP_SET_POWER_D3;
1582 drm_dp_dpcd_writeb(aux, DP_SET_POWER, pwr);
1583 }
1584 }
1585
1586 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1587 nv50_audio_disable(encoder, nv_crtc);
1625 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1626 nvif_outp_release(&nv_encoder->outp);
1627 nv_encoder->crtc = NULL;
1628}
1629
1630static void
1631nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1632{
1633 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1634 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
1635 struct nv50_head_atom *asyh =
1636 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
1637 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1638 struct nv50_disp *disp = nv50_disp(encoder->dev);
1588 nvif_outp_release(&nv_encoder->outp);
1589 nv_encoder->crtc = NULL;
1590}
1591
1592static void
1593nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state)
1594{
1595 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1596 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder);
1597 struct nv50_head_atom *asyh =
1598 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
1599 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1600 struct nv50_disp *disp = nv50_disp(encoder->dev);
1601 struct nvif_outp *outp = &nv_encoder->outp;
1639 struct drm_device *dev = encoder->dev;
1640 struct nouveau_drm *drm = nouveau_drm(dev);
1641 struct nouveau_connector *nv_connector;
1642#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1643 struct nouveau_backlight *backlight;
1644#endif
1645 struct nvbios *bios = &drm->vbios;
1646 bool lvds_dual = false, lvds_8bpc = false, hda = false;

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1652
1653 if ((disp->disp->object.oclass == GT214_DISP ||
1654 disp->disp->object.oclass >= GF110_DISP) &&
1655 drm_detect_monitor_audio(nv_connector->edid))
1656 hda = true;
1657
1658 switch (nv_encoder->dcb->type) {
1659 case DCB_OUTPUT_TMDS:
1602 struct drm_device *dev = encoder->dev;
1603 struct nouveau_drm *drm = nouveau_drm(dev);
1604 struct nouveau_connector *nv_connector;
1605#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
1606 struct nouveau_backlight *backlight;
1607#endif
1608 struct nvbios *bios = &drm->vbios;
1609 bool lvds_dual = false, lvds_8bpc = false, hda = false;

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1615
1616 if ((disp->disp->object.oclass == GT214_DISP ||
1617 disp->disp->object.oclass >= GF110_DISP) &&
1618 drm_detect_monitor_audio(nv_connector->edid))
1619 hda = true;
1620
1621 switch (nv_encoder->dcb->type) {
1622 case DCB_OUTPUT_TMDS:
1660 nvif_outp_acquire_tmds(&nv_encoder->outp, hda);
1623 if (disp->disp->object.oclass == NV50_DISP ||
1624 !drm_detect_hdmi_monitor(nv_connector->edid))
1625 nvif_outp_acquire_tmds(outp, nv_crtc->index, false, 0, 0, 0, false);
1626 else
1627 nv50_hdmi_enable(encoder, nv_crtc, nv_connector, state, mode, hda);
1628
1661 if (nv_encoder->outp.or.link & 1) {
1662 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A;
1663 /* Only enable dual-link if:
1664 * - Need to (i.e. rate > 165MHz)
1665 * - DCB says we can
1666 * - Not an HDMI monitor, since there's no dual-link
1667 * on HDMI.
1668 */
1669 if (mode->clock >= 165000 &&
1670 nv_encoder->dcb->duallink_possible &&
1671 !drm_detect_hdmi_monitor(nv_connector->edid))
1672 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS;
1673 } else {
1674 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B;
1675 }
1629 if (nv_encoder->outp.or.link & 1) {
1630 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A;
1631 /* Only enable dual-link if:
1632 * - Need to (i.e. rate > 165MHz)
1633 * - DCB says we can
1634 * - Not an HDMI monitor, since there's no dual-link
1635 * on HDMI.
1636 */
1637 if (mode->clock >= 165000 &&
1638 nv_encoder->dcb->duallink_possible &&
1639 !drm_detect_hdmi_monitor(nv_connector->edid))
1640 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS;
1641 } else {
1642 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B;
1643 }
1676
1677 nv50_hdmi_enable(&nv_encoder->base.base, nv_crtc, nv_connector, state, mode);
1678 break;
1679 case DCB_OUTPUT_LVDS:
1680 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM;
1681
1682 if (bios->fp_no_ddc) {
1683 lvds_dual = bios->fp.dual_link;
1684 lvds_8bpc = bios->fp.if_is_24bit;
1685 } else {

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1895 case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;
1896 case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;
1897 default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;
1898 }
1899
1900 switch (nv_encoder->dcb->type) {
1901 case DCB_OUTPUT_TMDS:
1902 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
1644 break;
1645 case DCB_OUTPUT_LVDS:
1646 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM;
1647
1648 if (bios->fp_no_ddc) {
1649 lvds_dual = bios->fp.dual_link;
1650 lvds_8bpc = bios->fp.if_is_24bit;
1651 } else {

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1861 case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;
1862 case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;
1863 default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;
1864 }
1865
1866 switch (nv_encoder->dcb->type) {
1867 case DCB_OUTPUT_TMDS:
1868 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
1903 nvif_outp_acquire_tmds(&nv_encoder->outp, false);
1869 nvif_outp_acquire_tmds(&nv_encoder->outp, false, false, 0, 0, 0, false);
1904 break;
1905 case DCB_OUTPUT_DP:
1906 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
1907 nvif_outp_acquire_dp(&nv_encoder->outp, false);
1908 break;
1909 default:
1910 BUG();
1911 break;

--- 929 unchanged lines hidden --- 		1870 break;
1871 case DCB_OUTPUT_DP:
1872 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC);
1873 nvif_outp_acquire_dp(&nv_encoder->outp, false);
1874 break;
1875 default:
1876 BUG();
1877 break;

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