tvnv17.c (5e2aa2ed08e2e280121dc7cf5609c87d464f12ef) tvnv17.c (967e7bde8739fe3b215f7537e8f1f39c044902af)
1/*
2 * Copyright (C) 2009 Francisco Jerez.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,

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46 "\t\t*NOTE* Ignored for cards with external TV encoders.");
47static char *nouveau_tv_norm;
48module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
49
50static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
51{
52 struct drm_device *dev = encoder->dev;
53 struct nouveau_drm *drm = nouveau_drm(dev);
1/*
2 * Copyright (C) 2009 Francisco Jerez.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,

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46 "\t\t*NOTE* Ignored for cards with external TV encoders.");
47static char *nouveau_tv_norm;
48module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
49
50static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
51{
52 struct drm_device *dev = encoder->dev;
53 struct nouveau_drm *drm = nouveau_drm(dev);
54 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
54 struct nouveau_gpio *gpio = nvkm_gpio(&drm->device);
55 uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
56 uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
57 fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
58 uint32_t sample = 0;
59 int head;
60
61#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
62 testval = RGB_TEST_DATA(0x82, 0xeb, 0x82);

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130
131 return sample;
132}
133
134static bool
135get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask)
136{
137 struct nouveau_drm *drm = nouveau_drm(dev);
55 uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
56 uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
57 fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
58 uint32_t sample = 0;
59 int head;
60
61#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
62 testval = RGB_TEST_DATA(0x82, 0xeb, 0x82);

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130
131 return sample;
132}
133
134static bool
135get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask)
136{
137 struct nouveau_drm *drm = nouveau_drm(dev);
138 struct nouveau_object *device = drm->device;
138 struct nvif_device *device = &drm->device;
139
140 /* Zotac FX5200 */
139
140 /* Zotac FX5200 */
141 if (nv_device_match(device, 0x0322, 0x19da, 0x1035) ||
142 nv_device_match(device, 0x0322, 0x19da, 0x2035)) {
141 if (nv_device_match(nvkm_object(device), 0x0322, 0x19da, 0x1035) ||
142 nv_device_match(nvkm_object(device), 0x0322, 0x19da, 0x2035)) {
143 *pin_mask = 0xc;
144 return false;
145 }
146
147 /* MSI nForce2 IGP */
143 *pin_mask = 0xc;
144 return false;
145 }
146
147 /* MSI nForce2 IGP */
148 if (nv_device_match(device, 0x01f0, 0x1462, 0x5710)) {
148 if (nv_device_match(nvkm_object(device), 0x01f0, 0x1462, 0x5710)) {
149 *pin_mask = 0xc;
150 return false;
151 }
152
153 return true;
154}
155
156static enum drm_connector_status

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162 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
163 struct dcb_output *dcb = tv_enc->base.dcb;
164 bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask);
165
166 if (nv04_dac_in_use(encoder))
167 return connector_status_disconnected;
168
169 if (reliable) {
149 *pin_mask = 0xc;
150 return false;
151 }
152
153 return true;
154}
155
156static enum drm_connector_status

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162 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
163 struct dcb_output *dcb = tv_enc->base.dcb;
164 bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask);
165
166 if (nv04_dac_in_use(encoder))
167 return connector_status_disconnected;
168
169 if (reliable) {
170 if (nv_device(drm->device)->chipset == 0x42 ||
171 nv_device(drm->device)->chipset == 0x43)
170 if (drm->device.info.chipset == 0x42 ||
171 drm->device.info.chipset == 0x43)
172 tv_enc->pin_mask =
173 nv42_tv_sample_load(encoder) >> 28 & 0xe;
174 else
175 tv_enc->pin_mask =
176 nv17_dac_sample_load(encoder) >> 28 & 0xe;
177 }
178
179 switch (tv_enc->pin_mask) {

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370
371 return true;
372}
373
374static void nv17_tv_dpms(struct drm_encoder *encoder, int mode)
375{
376 struct drm_device *dev = encoder->dev;
377 struct nouveau_drm *drm = nouveau_drm(dev);
172 tv_enc->pin_mask =
173 nv42_tv_sample_load(encoder) >> 28 & 0xe;
174 else
175 tv_enc->pin_mask =
176 nv17_dac_sample_load(encoder) >> 28 & 0xe;
177 }
178
179 switch (tv_enc->pin_mask) {

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370
371 return true;
372}
373
374static void nv17_tv_dpms(struct drm_encoder *encoder, int mode)
375{
376 struct drm_device *dev = encoder->dev;
377 struct nouveau_drm *drm = nouveau_drm(dev);
378 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
378 struct nouveau_gpio *gpio = nvkm_gpio(&drm->device);
379 struct nv17_tv_state *regs = &to_tv_enc(encoder)->state;
380 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
381
382 if (nouveau_encoder(encoder)->last_dpms == mode)
383 return;
384 nouveau_encoder(encoder)->last_dpms = mode;
385
386 NV_INFO(drm, "Setting dpms mode %d on TV encoder (output %d)\n",

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443 }
444
445 if (tv_norm->kind == CTV_ENC_MODE)
446 *cr_lcd |= 0x1 | (head ? 0x0 : 0x8);
447
448 /* Set the DACCLK register */
449 dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
450
379 struct nv17_tv_state *regs = &to_tv_enc(encoder)->state;
380 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
381
382 if (nouveau_encoder(encoder)->last_dpms == mode)
383 return;
384 nouveau_encoder(encoder)->last_dpms = mode;
385
386 NV_INFO(drm, "Setting dpms mode %d on TV encoder (output %d)\n",

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443 }
444
445 if (tv_norm->kind == CTV_ENC_MODE)
446 *cr_lcd |= 0x1 | (head ? 0x0 : 0x8);
447
448 /* Set the DACCLK register */
449 dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
450
451 if (nv_device(drm->device)->card_type == NV_40)
451 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
452 dacclk |= 0x1a << 16;
453
454 if (tv_norm->kind == CTV_ENC_MODE) {
455 dacclk |= 0x20;
456
457 if (head)
458 dacclk |= 0x100;
459 else

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500 tv_regs->ptv_508 = 0x1200000;
501 tv_regs->ptv_614 = 0x33;
502
503 } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
504 tv_regs->ptv_508 = 0xf00000;
505 tv_regs->ptv_614 = 0x13;
506 }
507
452 dacclk |= 0x1a << 16;
453
454 if (tv_norm->kind == CTV_ENC_MODE) {
455 dacclk |= 0x20;
456
457 if (head)
458 dacclk |= 0x100;
459 else

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500 tv_regs->ptv_508 = 0x1200000;
501 tv_regs->ptv_614 = 0x33;
502
503 } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
504 tv_regs->ptv_508 = 0xf00000;
505 tv_regs->ptv_614 = 0x13;
506 }
507
508 if (nv_device(drm->device)->card_type >= NV_30) {
508 if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) {
509 tv_regs->ptv_500 = 0xe8e0;
510 tv_regs->ptv_504 = 0x1710;
511 tv_regs->ptv_604 = 0x0;
512 tv_regs->ptv_608 = 0x0;
513 } else {
514 if (tv_norm->tv_enc_mode.vdisplay == 576) {
515 tv_regs->ptv_604 = 0x20;
516 tv_regs->ptv_608 = 0x10;

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595 nv17_tv_update_properties(encoder);
596 } else {
597 nv17_ctv_update_rescaler(encoder);
598 }
599
600 nv17_tv_state_load(dev, &to_tv_enc(encoder)->state);
601
602 /* This could use refinement for flatpanels, but it should work */
509 tv_regs->ptv_500 = 0xe8e0;
510 tv_regs->ptv_504 = 0x1710;
511 tv_regs->ptv_604 = 0x0;
512 tv_regs->ptv_608 = 0x0;
513 } else {
514 if (tv_norm->tv_enc_mode.vdisplay == 576) {
515 tv_regs->ptv_604 = 0x20;
516 tv_regs->ptv_608 = 0x10;

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595 nv17_tv_update_properties(encoder);
596 } else {
597 nv17_ctv_update_rescaler(encoder);
598 }
599
600 nv17_tv_state_load(dev, &to_tv_enc(encoder)->state);
601
602 /* This could use refinement for flatpanels, but it should work */
603 if (nv_device(drm->device)->chipset < 0x44)
603 if (drm->device.info.chipset < 0x44)
604 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
605 nv04_dac_output_offset(encoder),
606 0xf0000000);
607 else
608 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
609 nv04_dac_output_offset(encoder),
610 0x00100000);
611

--- 231 unchanged lines hidden --- 		604 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
605 nv04_dac_output_offset(encoder),
606 0xf0000000);
607 else
608 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
609 nv04_dac_output_offset(encoder),
610 0x00100000);
611

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