hw.h (db2bec187dd68e79d512112df1f6e7a849e7f0ce) hw.h (967e7bde8739fe3b215f7537e8f1f39c044902af)
1/*
2 * Copyright 2008 Stuart Bennett
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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55
56/* nouveau_calc.c */
57extern void nouveau_calc_arb(struct drm_device *, int vclk, int bpp,
58 int *burst, int *lwm);
59
60static inline uint32_t NVReadCRTC(struct drm_device *dev,
61 int head, uint32_t reg)
62{
1/*
2 * Copyright 2008 Stuart Bennett
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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55
56/* nouveau_calc.c */
57extern void nouveau_calc_arb(struct drm_device *, int vclk, int bpp,
58 int *burst, int *lwm);
59
60static inline uint32_t NVReadCRTC(struct drm_device *dev,
61 int head, uint32_t reg)
62{
63 struct nouveau_object *device = nouveau_drm(dev)->device;
63 struct nvif_device *device = &nouveau_drm(dev)->device;
64 uint32_t val;
65 if (head)
66 reg += NV_PCRTC0_SIZE;
67 val = nvif_rd32(device, reg);
68 return val;
69}
70
71static inline void NVWriteCRTC(struct drm_device *dev,
72 int head, uint32_t reg, uint32_t val)
73{
64 uint32_t val;
65 if (head)
66 reg += NV_PCRTC0_SIZE;
67 val = nvif_rd32(device, reg);
68 return val;
69}
70
71static inline void NVWriteCRTC(struct drm_device *dev,
72 int head, uint32_t reg, uint32_t val)
73{
74 struct nouveau_object *device = nouveau_drm(dev)->device;
74 struct nvif_device *device = &nouveau_drm(dev)->device;
75 if (head)
76 reg += NV_PCRTC0_SIZE;
77 nvif_wr32(device, reg, val);
78}
79
80static inline uint32_t NVReadRAMDAC(struct drm_device *dev,
81 int head, uint32_t reg)
82{
75 if (head)
76 reg += NV_PCRTC0_SIZE;
77 nvif_wr32(device, reg, val);
78}
79
80static inline uint32_t NVReadRAMDAC(struct drm_device *dev,
81 int head, uint32_t reg)
82{
83 struct nouveau_object *device = nouveau_drm(dev)->device;
83 struct nvif_device *device = &nouveau_drm(dev)->device;
84 uint32_t val;
85 if (head)
86 reg += NV_PRAMDAC0_SIZE;
87 val = nvif_rd32(device, reg);
88 return val;
89}
90
91static inline void NVWriteRAMDAC(struct drm_device *dev,
92 int head, uint32_t reg, uint32_t val)
93{
84 uint32_t val;
85 if (head)
86 reg += NV_PRAMDAC0_SIZE;
87 val = nvif_rd32(device, reg);
88 return val;
89}
90
91static inline void NVWriteRAMDAC(struct drm_device *dev,
92 int head, uint32_t reg, uint32_t val)
93{
94 struct nouveau_object *device = nouveau_drm(dev)->device;
94 struct nvif_device *device = &nouveau_drm(dev)->device;
95 if (head)
96 reg += NV_PRAMDAC0_SIZE;
97 nvif_wr32(device, reg, val);
98}
99
100static inline uint8_t nv_read_tmds(struct drm_device *dev,
101 int or, int dl, uint8_t address)
102{

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115
116 NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA + dl * 8, data);
117 NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL + dl * 8, address);
118}
119
120static inline void NVWriteVgaCrtc(struct drm_device *dev,
121 int head, uint8_t index, uint8_t value)
122{
95 if (head)
96 reg += NV_PRAMDAC0_SIZE;
97 nvif_wr32(device, reg, val);
98}
99
100static inline uint8_t nv_read_tmds(struct drm_device *dev,
101 int or, int dl, uint8_t address)
102{

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115
116 NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA + dl * 8, data);
117 NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL + dl * 8, address);
118}
119
120static inline void NVWriteVgaCrtc(struct drm_device *dev,
121 int head, uint8_t index, uint8_t value)
122{
123 struct nouveau_object *device = nouveau_drm(dev)->device;
123 struct nvif_device *device = &nouveau_drm(dev)->device;
124 nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
125 nvif_wr08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value);
126}
127
128static inline uint8_t NVReadVgaCrtc(struct drm_device *dev,
129 int head, uint8_t index)
130{
124 nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
125 nvif_wr08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value);
126}
127
128static inline uint8_t NVReadVgaCrtc(struct drm_device *dev,
129 int head, uint8_t index)
130{
131 struct nouveau_object *device = nouveau_drm(dev)->device;
131 struct nvif_device *device = &nouveau_drm(dev)->device;
132 uint8_t val;
133 nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
134 val = nvif_rd08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE);
135 return val;
136}
137
138/* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
139 * I suspect they in fact do nothing, but are merely a way to carry useful

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160{
161 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index);
162 return NVReadVgaCrtc(dev, head, NV_CIO_CRE_58);
163}
164
165static inline uint8_t NVReadPRMVIO(struct drm_device *dev,
166 int head, uint32_t reg)
167{
132 uint8_t val;
133 nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
134 val = nvif_rd08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE);
135 return val;
136}
137
138/* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
139 * I suspect they in fact do nothing, but are merely a way to carry useful

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160{
161 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index);
162 return NVReadVgaCrtc(dev, head, NV_CIO_CRE_58);
163}
164
165static inline uint8_t NVReadPRMVIO(struct drm_device *dev,
166 int head, uint32_t reg)
167{
168 struct nouveau_object *device = nouveau_drm(dev)->device;
168 struct nvif_device *device = &nouveau_drm(dev)->device;
169 struct nouveau_drm *drm = nouveau_drm(dev);
170 uint8_t val;
171
172 /* Only NV4x have two pvio ranges; other twoHeads cards MUST call
173 * NVSetOwner for the relevant head to be programmed */
169 struct nouveau_drm *drm = nouveau_drm(dev);
170 uint8_t val;
171
172 /* Only NV4x have two pvio ranges; other twoHeads cards MUST call
173 * NVSetOwner for the relevant head to be programmed */
174 if (head && nv_device(drm->device)->card_type == NV_40)
174 if (head && drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
175 reg += NV_PRMVIO_SIZE;
176
177 val = nvif_rd08(device, reg);
178 return val;
179}
180
181static inline void NVWritePRMVIO(struct drm_device *dev,
182 int head, uint32_t reg, uint8_t value)
183{
175 reg += NV_PRMVIO_SIZE;
176
177 val = nvif_rd08(device, reg);
178 return val;
179}
180
181static inline void NVWritePRMVIO(struct drm_device *dev,
182 int head, uint32_t reg, uint8_t value)
183{
184 struct nouveau_object *device = nouveau_drm(dev)->device;
184 struct nvif_device *device = &nouveau_drm(dev)->device;
185 struct nouveau_drm *drm = nouveau_drm(dev);
186
187 /* Only NV4x have two pvio ranges; other twoHeads cards MUST call
188 * NVSetOwner for the relevant head to be programmed */
185 struct nouveau_drm *drm = nouveau_drm(dev);
186
187 /* Only NV4x have two pvio ranges; other twoHeads cards MUST call
188 * NVSetOwner for the relevant head to be programmed */
189 if (head && nv_device(drm->device)->card_type == NV_40)
189 if (head && drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
190 reg += NV_PRMVIO_SIZE;
191
192 nvif_wr08(device, reg, value);
193}
194
195static inline void NVSetEnablePalette(struct drm_device *dev, int head, bool enable)
196{
190 reg += NV_PRMVIO_SIZE;
191
192 nvif_wr08(device, reg, value);
193}
194
195static inline void NVSetEnablePalette(struct drm_device *dev, int head, bool enable)
196{
197 struct nouveau_object *device = nouveau_drm(dev)->device;
197 struct nvif_device *device = &nouveau_drm(dev)->device;
198 nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
199 nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20);
200}
201
202static inline bool NVGetEnablePalette(struct drm_device *dev, int head)
203{
198 nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
199 nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20);
200}
201
202static inline bool NVGetEnablePalette(struct drm_device *dev, int head)
203{
204 struct nouveau_object *device = nouveau_drm(dev)->device;
204 struct nvif_device *device = &nouveau_drm(dev)->device;
205 nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
206 return !(nvif_rd08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20);
207}
208
209static inline void NVWriteVgaAttr(struct drm_device *dev,
210 int head, uint8_t index, uint8_t value)
211{
205 nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
206 return !(nvif_rd08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20);
207}
208
209static inline void NVWriteVgaAttr(struct drm_device *dev,
210 int head, uint8_t index, uint8_t value)
211{
212 struct nouveau_object *device = nouveau_drm(dev)->device;
212 struct nvif_device *device = &nouveau_drm(dev)->device;
213 if (NVGetEnablePalette(dev, head))
214 index &= ~0x20;
215 else
216 index |= 0x20;
217
218 nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
219 nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
220 nvif_wr08(device, NV_PRMCIO_AR__WRITE + head * NV_PRMCIO_SIZE, value);
221}
222
223static inline uint8_t NVReadVgaAttr(struct drm_device *dev,
224 int head, uint8_t index)
225{
213 if (NVGetEnablePalette(dev, head))
214 index &= ~0x20;
215 else
216 index |= 0x20;
217
218 nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
219 nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
220 nvif_wr08(device, NV_PRMCIO_AR__WRITE + head * NV_PRMCIO_SIZE, value);
221}
222
223static inline uint8_t NVReadVgaAttr(struct drm_device *dev,
224 int head, uint8_t index)
225{
226 struct nouveau_object *device = nouveau_drm(dev)->device;
226 struct nvif_device *device = &nouveau_drm(dev)->device;
227 uint8_t val;
228 if (NVGetEnablePalette(dev, head))
229 index &= ~0x20;
230 else
231 index |= 0x20;
232
233 nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
234 nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);

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254 NVVgaSeqReset(dev, head, false);
255 }
256 NVSetEnablePalette(dev, head, protect);
257}
258
259static inline bool
260nv_heads_tied(struct drm_device *dev)
261{
227 uint8_t val;
228 if (NVGetEnablePalette(dev, head))
229 index &= ~0x20;
230 else
231 index |= 0x20;
232
233 nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
234 nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);

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254 NVVgaSeqReset(dev, head, false);
255 }
256 NVSetEnablePalette(dev, head, protect);
257}
258
259static inline bool
260nv_heads_tied(struct drm_device *dev)
261{
262 struct nouveau_object *device = nouveau_drm(dev)->device;
262 struct nvif_device *device = &nouveau_drm(dev)->device;
263 struct nouveau_drm *drm = nouveau_drm(dev);
264
263 struct nouveau_drm *drm = nouveau_drm(dev);
264
265 if (nv_device(drm->device)->chipset == 0x11)
265 if (drm->device.info.chipset == 0x11)
266 return !!(nvif_rd32(device, NV_PBUS_DEBUG_1) & (1 << 28));
267
268 return NVReadVgaCrtc(dev, 0, NV_CIO_CRE_44) & 0x4;
269}
270
271/* makes cr0-7 on the specified head read-only */
272static inline bool
273nv_lock_vga_crtc_base(struct drm_device *dev, int head, bool lock)

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313NVLockVgaCrtcs(struct drm_device *dev, bool lock)
314{
315 struct nouveau_drm *drm = nouveau_drm(dev);
316 bool waslocked = !NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX);
317
318 NVWriteVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX,
319 lock ? NV_CIO_SR_LOCK_VALUE : NV_CIO_SR_UNLOCK_RW_VALUE);
320 /* NV11 has independently lockable extended crtcs, except when tied */
266 return !!(nvif_rd32(device, NV_PBUS_DEBUG_1) & (1 << 28));
267
268 return NVReadVgaCrtc(dev, 0, NV_CIO_CRE_44) & 0x4;
269}
270
271/* makes cr0-7 on the specified head read-only */
272static inline bool
273nv_lock_vga_crtc_base(struct drm_device *dev, int head, bool lock)

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313NVLockVgaCrtcs(struct drm_device *dev, bool lock)
314{
315 struct nouveau_drm *drm = nouveau_drm(dev);
316 bool waslocked = !NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX);
317
318 NVWriteVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX,
319 lock ? NV_CIO_SR_LOCK_VALUE : NV_CIO_SR_UNLOCK_RW_VALUE);
320 /* NV11 has independently lockable extended crtcs, except when tied */
321 if (nv_device(drm->device)->chipset == 0x11 && !nv_heads_tied(dev))
321 if (drm->device.info.chipset == 0x11 && !nv_heads_tied(dev))
322 NVWriteVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX,
323 lock ? NV_CIO_SR_LOCK_VALUE :
324 NV_CIO_SR_UNLOCK_RW_VALUE);
325
326 return waslocked;
327}
328
329/* nv04 cursor max dimensions of 32x32 (A1R5G5B5) */
330#define NV04_CURSOR_SIZE 32
331/* limit nv10 cursors to 64x64 (ARGB8) (we could go to 64x255) */
332#define NV10_CURSOR_SIZE 64
333
334static inline int nv_cursor_width(struct drm_device *dev)
335{
336 struct nouveau_drm *drm = nouveau_drm(dev);
337
322 NVWriteVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX,
323 lock ? NV_CIO_SR_LOCK_VALUE :
324 NV_CIO_SR_UNLOCK_RW_VALUE);
325
326 return waslocked;
327}
328
329/* nv04 cursor max dimensions of 32x32 (A1R5G5B5) */
330#define NV04_CURSOR_SIZE 32
331/* limit nv10 cursors to 64x64 (ARGB8) (we could go to 64x255) */
332#define NV10_CURSOR_SIZE 64
333
334static inline int nv_cursor_width(struct drm_device *dev)
335{
336 struct nouveau_drm *drm = nouveau_drm(dev);
337
338 return nv_device(drm->device)->card_type >= NV_10 ? NV10_CURSOR_SIZE : NV04_CURSOR_SIZE;
338 return drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS ? NV10_CURSOR_SIZE : NV04_CURSOR_SIZE;
339}
340
341static inline void
342nv_fix_nv40_hw_cursor(struct drm_device *dev, int head)
343{
344 /* on some nv40 (such as the "true" (in the NV_PFB_BOOT_0 sense) nv40,
345 * the gf6800gt) a hardware bug requires a write to PRAMDAC_CURSOR_POS
346 * for changes to the CRTC CURCTL regs to take effect, whether changing

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352
353static inline void
354nv_set_crtc_base(struct drm_device *dev, int head, uint32_t offset)
355{
356 struct nouveau_drm *drm = nouveau_drm(dev);
357
358 NVWriteCRTC(dev, head, NV_PCRTC_START, offset);
359
339}
340
341static inline void
342nv_fix_nv40_hw_cursor(struct drm_device *dev, int head)
343{
344 /* on some nv40 (such as the "true" (in the NV_PFB_BOOT_0 sense) nv40,
345 * the gf6800gt) a hardware bug requires a write to PRAMDAC_CURSOR_POS
346 * for changes to the CRTC CURCTL regs to take effect, whether changing

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352
353static inline void
354nv_set_crtc_base(struct drm_device *dev, int head, uint32_t offset)
355{
356 struct nouveau_drm *drm = nouveau_drm(dev);
357
358 NVWriteCRTC(dev, head, NV_PCRTC_START, offset);
359
360 if (nv_device(drm->device)->card_type == NV_04) {
360 if (drm->device.info.family == NV_DEVICE_INFO_V0_TNT) {
361 /*
362 * Hilarious, the 24th bit doesn't want to stick to
363 * PCRTC_START...
364 */
365 int cre_heb = NVReadVgaCrtc(dev, head, NV_CIO_CRE_HEB__INDEX);
366
367 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HEB__INDEX,
368 (cre_heb & ~0x40) | ((offset >> 18) & 0x40));

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377 &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
378
379 if (show)
380 *curctl1 |= MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE);
381 else
382 *curctl1 &= ~MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE);
383 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, *curctl1);
384
361 /*
362 * Hilarious, the 24th bit doesn't want to stick to
363 * PCRTC_START...
364 */
365 int cre_heb = NVReadVgaCrtc(dev, head, NV_CIO_CRE_HEB__INDEX);
366
367 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HEB__INDEX,
368 (cre_heb & ~0x40) | ((offset >> 18) & 0x40));

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377 &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
378
379 if (show)
380 *curctl1 |= MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE);
381 else
382 *curctl1 &= ~MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE);
383 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, *curctl1);
384
385 if (nv_device(drm->device)->card_type == NV_40)
385 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
386 nv_fix_nv40_hw_cursor(dev, head);
387}
388
389static inline uint32_t
390nv_pitch_align(struct drm_device *dev, uint32_t width, int bpp)
391{
392 struct nouveau_drm *drm = nouveau_drm(dev);
393 int mask;
394
395 if (bpp == 15)
396 bpp = 16;
397 if (bpp == 24)
398 bpp = 8;
399
400 /* Alignment requirements taken from the Haiku driver */
386 nv_fix_nv40_hw_cursor(dev, head);
387}
388
389static inline uint32_t
390nv_pitch_align(struct drm_device *dev, uint32_t width, int bpp)
391{
392 struct nouveau_drm *drm = nouveau_drm(dev);
393 int mask;
394
395 if (bpp == 15)
396 bpp = 16;
397 if (bpp == 24)
398 bpp = 8;
399
400 /* Alignment requirements taken from the Haiku driver */
401 if (nv_device(drm->device)->card_type == NV_04)
401 if (drm->device.info.family == NV_DEVICE_INFO_V0_TNT)
402 mask = 128 / bpp - 1;
403 else
404 mask = 512 / bpp - 1;
405
406 return (width + mask) & ~mask;
407}
408
409#endif /* __NOUVEAU_HW_H__ */
402 mask = 128 / bpp - 1;
403 else
404 mask = 512 / bpp - 1;
405
406 return (width + mask) & ~mask;
407}
408
409#endif /* __NOUVEAU_HW_H__ */