hw.c (db2bec187dd68e79d512112df1f6e7a849e7f0ce) hw.c (967e7bde8739fe3b215f7537e8f1f39c044902af)
1/*
2 * Copyright 2006 Dave Airlie
3 * Copyright 2007 Maarten Maathuis
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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87void
88NVSetOwner(struct drm_device *dev, int owner)
89{
90 struct nouveau_drm *drm = nouveau_drm(dev);
91
92 if (owner == 1)
93 owner *= 3;
94
1/*
2 * Copyright 2006 Dave Airlie
3 * Copyright 2007 Maarten Maathuis
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 78 unchanged lines hidden (view full) ---

87void
88NVSetOwner(struct drm_device *dev, int owner)
89{
90 struct nouveau_drm *drm = nouveau_drm(dev);
91
92 if (owner == 1)
93 owner *= 3;
94
95 if (nv_device(drm->device)->chipset == 0x11) {
95 if (drm->device.info.chipset == 0x11) {
96 /* This might seem stupid, but the blob does it and
97 * omitting it often locks the system up.
98 */
99 NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX);
100 NVReadVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX);
101 }
102
103 /* CR44 is always changed on CRTC0 */
104 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner);
105
96 /* This might seem stupid, but the blob does it and
97 * omitting it often locks the system up.
98 */
99 NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX);
100 NVReadVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX);
101 }
102
103 /* CR44 is always changed on CRTC0 */
104 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner);
105
106 if (nv_device(drm->device)->chipset == 0x11) { /* set me harder */
106 if (drm->device.info.chipset == 0x11) { /* set me harder */
107 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
108 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
109 }
110}
111
112void
113NVBlankScreen(struct drm_device *dev, int head, bool blank)
114{

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147 pllvals->NM1 = pll2 & 0xffff;
148 /* single stage NVPLL and VPLLs use 1 << 8, MPLL uses 1 << 12 */
149 if (!(pll1 & 0x1100))
150 pllvals->NM2 = pll2 >> 16;
151 } else {
152 pllvals->NM1 = pll1 & 0xffff;
153 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2)
154 pllvals->NM2 = pll2 & 0xffff;
107 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
108 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
109 }
110}
111
112void
113NVBlankScreen(struct drm_device *dev, int head, bool blank)
114{

--- 32 unchanged lines hidden (view full) ---

147 pllvals->NM1 = pll2 & 0xffff;
148 /* single stage NVPLL and VPLLs use 1 << 8, MPLL uses 1 << 12 */
149 if (!(pll1 & 0x1100))
150 pllvals->NM2 = pll2 >> 16;
151 } else {
152 pllvals->NM1 = pll1 & 0xffff;
153 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2)
154 pllvals->NM2 = pll2 & 0xffff;
155 else if (nv_device(drm->device)->chipset == 0x30 || nv_device(drm->device)->chipset == 0x35) {
155 else if (drm->device.info.chipset == 0x30 || drm->device.info.chipset == 0x35) {
156 pllvals->M1 &= 0xf; /* only 4 bits */
157 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) {
158 pllvals->M2 = (pll1 >> 4) & 0x7;
159 pllvals->N2 = ((pll1 >> 21) & 0x18) |
160 ((pll1 >> 19) & 0x7);
161 }
162 }
163 }
164}
165
166int
167nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype,
168 struct nouveau_pll_vals *pllvals)
169{
170 struct nouveau_drm *drm = nouveau_drm(dev);
156 pllvals->M1 &= 0xf; /* only 4 bits */
157 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) {
158 pllvals->M2 = (pll1 >> 4) & 0x7;
159 pllvals->N2 = ((pll1 >> 21) & 0x18) |
160 ((pll1 >> 19) & 0x7);
161 }
162 }
163 }
164}
165
166int
167nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype,
168 struct nouveau_pll_vals *pllvals)
169{
170 struct nouveau_drm *drm = nouveau_drm(dev);
171 struct nouveau_object *device = drm->device;
172 struct nouveau_bios *bios = nouveau_bios(device);
171 struct nvif_device *device = &drm->device;
172 struct nouveau_bios *bios = nvkm_bios(device);
173 uint32_t reg1, pll1, pll2 = 0;
174 struct nvbios_pll pll_lim;
175 int ret;
176
177 ret = nvbios_pll_parse(bios, plltype, &pll_lim);
178 if (ret || !(reg1 = pll_lim.reg))
179 return -ENOENT;
180
181 pll1 = nvif_rd32(device, reg1);
182 if (reg1 <= 0x405c)
183 pll2 = nvif_rd32(device, reg1 + 4);
184 else if (nv_two_reg_pll(dev)) {
185 uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70);
186
187 pll2 = nvif_rd32(device, reg2);
188 }
189
173 uint32_t reg1, pll1, pll2 = 0;
174 struct nvbios_pll pll_lim;
175 int ret;
176
177 ret = nvbios_pll_parse(bios, plltype, &pll_lim);
178 if (ret || !(reg1 = pll_lim.reg))
179 return -ENOENT;
180
181 pll1 = nvif_rd32(device, reg1);
182 if (reg1 <= 0x405c)
183 pll2 = nvif_rd32(device, reg1 + 4);
184 else if (nv_two_reg_pll(dev)) {
185 uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70);
186
187 pll2 = nvif_rd32(device, reg2);
188 }
189
190 if (nv_device(drm->device)->card_type == 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) {
190 if (drm->device.info.family == NV_DEVICE_INFO_V0_CELSIUS && reg1 >= NV_PRAMDAC_VPLL_COEFF) {
191 uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580);
192
193 /* check whether vpll has been forced into single stage mode */
194 if (reg1 == NV_PRAMDAC_VPLL_COEFF) {
195 if (ramdac580 & NV_RAMDAC_580_VPLL1_ACTIVE)
196 pll2 = 0;
197 } else
198 if (ramdac580 & NV_RAMDAC_580_VPLL2_ACTIVE)

--- 51 unchanged lines hidden (view full) ---

250{
251 /* the vpll on an unused head can come up with a random value, way
252 * beyond the pll limits. for some reason this causes the chip to
253 * lock up when reading the dac palette regs, so set a valid pll here
254 * when such a condition detected. only seen on nv11 to date
255 */
256
257 struct nouveau_drm *drm = nouveau_drm(dev);
191 uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580);
192
193 /* check whether vpll has been forced into single stage mode */
194 if (reg1 == NV_PRAMDAC_VPLL_COEFF) {
195 if (ramdac580 & NV_RAMDAC_580_VPLL1_ACTIVE)
196 pll2 = 0;
197 } else
198 if (ramdac580 & NV_RAMDAC_580_VPLL2_ACTIVE)

--- 51 unchanged lines hidden (view full) ---

250{
251 /* the vpll on an unused head can come up with a random value, way
252 * beyond the pll limits. for some reason this causes the chip to
253 * lock up when reading the dac palette regs, so set a valid pll here
254 * when such a condition detected. only seen on nv11 to date
255 */
256
257 struct nouveau_drm *drm = nouveau_drm(dev);
258 struct nouveau_object *device = drm->device;
259 struct nouveau_clock *clk = nouveau_clock(device);
260 struct nouveau_bios *bios = nouveau_bios(device);
258 struct nvif_device *device = &drm->device;
259 struct nouveau_clock *clk = nvkm_clock(device);
260 struct nouveau_bios *bios = nvkm_bios(device);
261 struct nvbios_pll pll_lim;
262 struct nouveau_pll_vals pv;
263 enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0;
264
265 if (nvbios_pll_parse(bios, pll, &pll_lim))
266 return;
267 nouveau_hw_get_pllvals(dev, pll, &pv);
268

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389static void
390nv_save_state_ramdac(struct drm_device *dev, int head,
391 struct nv04_mode_state *state)
392{
393 struct nouveau_drm *drm = nouveau_drm(dev);
394 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
395 int i;
396
261 struct nvbios_pll pll_lim;
262 struct nouveau_pll_vals pv;
263 enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0;
264
265 if (nvbios_pll_parse(bios, pll, &pll_lim))
266 return;
267 nouveau_hw_get_pllvals(dev, pll, &pv);
268

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389static void
390nv_save_state_ramdac(struct drm_device *dev, int head,
391 struct nv04_mode_state *state)
392{
393 struct nouveau_drm *drm = nouveau_drm(dev);
394 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
395 int i;
396
397 if (nv_device(drm->device)->card_type >= NV_10)
397 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
398 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC);
399
400 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, &regp->pllvals);
401 state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT);
402 if (nv_two_heads(dev))
403 state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
398 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC);
399
400 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, &regp->pllvals);
401 state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT);
402 if (nv_two_heads(dev))
403 state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
404 if (nv_device(drm->device)->chipset == 0x11)
404 if (drm->device.info.chipset == 0x11)
405 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11);
406
407 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL);
408
409 if (nv_gf4_disp_arch(dev))
410 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630);
405 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11);
406
407 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL);
408
409 if (nv_gf4_disp_arch(dev))
410 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630);
411 if (nv_device(drm->device)->chipset >= 0x30)
411 if (drm->device.info.chipset >= 0x30)
412 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634);
413
414 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP);
415 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL);
416 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW);
417 regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY);
418 regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL);
419 regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW);

--- 25 unchanged lines hidden (view full) ---

445 regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1);
446 regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2);
447
448 regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR);
449
450 if (nv_gf4_disp_arch(dev))
451 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0);
452
412 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634);
413
414 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP);
415 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL);
416 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW);
417 regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY);
418 regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL);
419 regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW);

--- 25 unchanged lines hidden (view full) ---

445 regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1);
446 regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2);
447
448 regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR);
449
450 if (nv_gf4_disp_arch(dev))
451 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0);
452
453 if (nv_device(drm->device)->card_type == NV_40) {
453 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) {
454 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20);
455 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24);
456 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34);
457
458 for (i = 0; i < 38; i++)
459 regp->ctv_regs[i] = NVReadRAMDAC(dev, head,
460 NV_PRAMDAC_CTV + 4*i);
461 }
462}
463
464static void
465nv_load_state_ramdac(struct drm_device *dev, int head,
466 struct nv04_mode_state *state)
467{
468 struct nouveau_drm *drm = nouveau_drm(dev);
454 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20);
455 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24);
456 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34);
457
458 for (i = 0; i < 38; i++)
459 regp->ctv_regs[i] = NVReadRAMDAC(dev, head,
460 NV_PRAMDAC_CTV + 4*i);
461 }
462}
463
464static void
465nv_load_state_ramdac(struct drm_device *dev, int head,
466 struct nv04_mode_state *state)
467{
468 struct nouveau_drm *drm = nouveau_drm(dev);
469 struct nouveau_clock *clk = nouveau_clock(drm->device);
469 struct nouveau_clock *clk = nvkm_clock(&drm->device);
470 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
471 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
472 int i;
473
470 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
471 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
472 int i;
473
474 if (nv_device(drm->device)->card_type >= NV_10)
474 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
475 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
476
477 clk->pll_prog(clk, pllreg, &regp->pllvals);
478 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel);
479 if (nv_two_heads(dev))
480 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk);
475 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
476
477 clk->pll_prog(clk, pllreg, &regp->pllvals);
478 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel);
479 if (nv_two_heads(dev))
480 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk);
481 if (nv_device(drm->device)->chipset == 0x11)
481 if (drm->device.info.chipset == 0x11)
482 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither);
483
484 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl);
485
486 if (nv_gf4_disp_arch(dev))
487 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630);
482 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither);
483
484 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl);
485
486 if (nv_gf4_disp_arch(dev))
487 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630);
488 if (nv_device(drm->device)->chipset >= 0x30)
488 if (drm->device.info.chipset >= 0x30)
489 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634);
490
491 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup);
492 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal);
493 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew);
494 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay);
495 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal);
496 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew);

--- 20 unchanged lines hidden (view full) ---

517 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1);
518 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2);
519
520 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color);
521
522 if (nv_gf4_disp_arch(dev))
523 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0);
524
489 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634);
490
491 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup);
492 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal);
493 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew);
494 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay);
495 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal);
496 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew);

--- 20 unchanged lines hidden (view full) ---

517 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1);
518 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2);
519
520 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color);
521
522 if (nv_gf4_disp_arch(dev))
523 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0);
524
525 if (nv_device(drm->device)->card_type == NV_40) {
525 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) {
526 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20);
527 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24);
528 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34);
529
530 for (i = 0; i < 38; i++)
531 NVWriteRAMDAC(dev, head,
532 NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]);
533 }

--- 64 unchanged lines hidden (view full) ---

598 rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
599 rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
600 rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
601
602 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
603 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
604 rd_cio_state(dev, head, regp, NV_CIO_CRE_21);
605
526 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20);
527 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24);
528 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34);
529
530 for (i = 0; i < 38; i++)
531 NVWriteRAMDAC(dev, head,
532 NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]);
533 }

--- 64 unchanged lines hidden (view full) ---

598 rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
599 rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
600 rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
601
602 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
603 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
604 rd_cio_state(dev, head, regp, NV_CIO_CRE_21);
605
606 if (nv_device(drm->device)->card_type >= NV_20)
606 if (drm->device.info.family >= NV_DEVICE_INFO_V0_KELVIN)
607 rd_cio_state(dev, head, regp, NV_CIO_CRE_47);
608
607 rd_cio_state(dev, head, regp, NV_CIO_CRE_47);
608
609 if (nv_device(drm->device)->card_type >= NV_30)
609 if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
610 rd_cio_state(dev, head, regp, 0x9f);
611
612 rd_cio_state(dev, head, regp, NV_CIO_CRE_49);
613 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
614 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
615 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
616 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
617
610 rd_cio_state(dev, head, regp, 0x9f);
611
612 rd_cio_state(dev, head, regp, NV_CIO_CRE_49);
613 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
614 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
615 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
616 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
617
618 if (nv_device(drm->device)->card_type >= NV_10) {
618 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
619 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830);
620 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834);
621
619 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830);
620 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834);
621
622 if (nv_device(drm->device)->card_type >= NV_30)
622 if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
623 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT);
624
623 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT);
624
625 if (nv_device(drm->device)->card_type == NV_40)
625 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
626 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850);
627
628 if (nv_two_heads(dev))
629 regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL);
630 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG);
631 }
632
633 regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG);
634
635 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
636 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
626 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850);
627
628 if (nv_two_heads(dev))
629 regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL);
630 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG);
631 }
632
633 regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG);
634
635 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
636 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
637 if (nv_device(drm->device)->card_type >= NV_10) {
637 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
638 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
639 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
640 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B);
641 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
642 }
643 /* NV11 and NV20 don't have this, they stop at 0x52. */
644 if (nv_gf4_disp_arch(dev)) {
645 rd_cio_state(dev, head, regp, NV_CIO_CRE_42);

--- 12 unchanged lines hidden (view full) ---

658 regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START);
659}
660
661static void
662nv_load_state_ext(struct drm_device *dev, int head,
663 struct nv04_mode_state *state)
664{
665 struct nouveau_drm *drm = nouveau_drm(dev);
638 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
639 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
640 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B);
641 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
642 }
643 /* NV11 and NV20 don't have this, they stop at 0x52. */
644 if (nv_gf4_disp_arch(dev)) {
645 rd_cio_state(dev, head, regp, NV_CIO_CRE_42);

--- 12 unchanged lines hidden (view full) ---

658 regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START);
659}
660
661static void
662nv_load_state_ext(struct drm_device *dev, int head,
663 struct nv04_mode_state *state)
664{
665 struct nouveau_drm *drm = nouveau_drm(dev);
666 struct nouveau_object *device = drm->device;
667 struct nouveau_timer *ptimer = nouveau_timer(device);
668 struct nouveau_fb *pfb = nouveau_fb(device);
666 struct nvif_device *device = &drm->device;
667 struct nouveau_timer *ptimer = nvkm_timer(device);
668 struct nouveau_fb *pfb = nvkm_fb(device);
669 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
670 uint32_t reg900;
671 int i;
672
669 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
670 uint32_t reg900;
671 int i;
672
673 if (nv_device(drm->device)->card_type >= NV_10) {
673 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
674 if (nv_two_heads(dev))
675 /* setting ENGINE_CTRL (EC) *must* come before
676 * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in
677 * EC that should not be overwritten by writing stale EC
678 */
679 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);
680
681 nvif_wr32(device, NV_PVIDEO_STOP, 1);

--- 5 unchanged lines hidden (view full) ---

687 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), pfb->ram->size - 1);
688 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), pfb->ram->size - 1);
689 nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0);
690
691 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
692 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);
693 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834);
694
674 if (nv_two_heads(dev))
675 /* setting ENGINE_CTRL (EC) *must* come before
676 * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in
677 * EC that should not be overwritten by writing stale EC
678 */
679 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);
680
681 nvif_wr32(device, NV_PVIDEO_STOP, 1);

--- 5 unchanged lines hidden (view full) ---

687 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), pfb->ram->size - 1);
688 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), pfb->ram->size - 1);
689 nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0);
690
691 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
692 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);
693 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834);
694
695 if (nv_device(drm->device)->card_type >= NV_30)
695 if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
696 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
697
696 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
697
698 if (nv_device(drm->device)->card_type == NV_40) {
698 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) {
699 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850);
700
701 reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900);
702 if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC)
703 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000);
704 else
705 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000);
706 }

--- 6 unchanged lines hidden (view full) ---

713 wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
714 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
715 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
716 wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
717 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
718 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
719 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
720
699 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850);
700
701 reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900);
702 if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC)
703 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000);
704 else
705 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000);
706 }

--- 6 unchanged lines hidden (view full) ---

713 wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
714 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
715 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
716 wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
717 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
718 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
719 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
720
721 if (nv_device(drm->device)->card_type >= NV_20)
721 if (drm->device.info.family >= NV_DEVICE_INFO_V0_KELVIN)
722 wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
723
722 wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
723
724 if (nv_device(drm->device)->card_type >= NV_30)
724 if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
725 wr_cio_state(dev, head, regp, 0x9f);
726
727 wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
728 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
729 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
730 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
725 wr_cio_state(dev, head, regp, 0x9f);
726
727 wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
728 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
729 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
730 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
731 if (nv_device(drm->device)->card_type == NV_40)
731 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
732 nv_fix_nv40_hw_cursor(dev, head);
733 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
734
735 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
736 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
732 nv_fix_nv40_hw_cursor(dev, head);
733 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
734
735 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
736 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
737 if (nv_device(drm->device)->card_type >= NV_10) {
737 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
738 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
739 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
740 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B);
741 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
742 }
743 /* NV11 and NV20 stop at 0x52. */
744 if (nv_gf4_disp_arch(dev)) {
738 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
739 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
740 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B);
741 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
742 }
743 /* NV11 and NV20 stop at 0x52. */
744 if (nv_gf4_disp_arch(dev)) {
745 if (nv_device(drm->device)->card_type < NV_20) {
745 if (drm->device.info.family < NV_DEVICE_INFO_V0_KELVIN) {
746 /* Not waiting for vertical retrace before modifying
747 CRE_53/CRE_54 causes lockups. */
748 nouveau_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8);
749 nouveau_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0);
750 }
751
752 wr_cio_state(dev, head, regp, NV_CIO_CRE_42);
753 wr_cio_state(dev, head, regp, NV_CIO_CRE_53);

--- 10 unchanged lines hidden (view full) ---

764
765 NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start);
766}
767
768static void
769nv_save_state_palette(struct drm_device *dev, int head,
770 struct nv04_mode_state *state)
771{
746 /* Not waiting for vertical retrace before modifying
747 CRE_53/CRE_54 causes lockups. */
748 nouveau_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8);
749 nouveau_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0);
750 }
751
752 wr_cio_state(dev, head, regp, NV_CIO_CRE_42);
753 wr_cio_state(dev, head, regp, NV_CIO_CRE_53);

--- 10 unchanged lines hidden (view full) ---

764
765 NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start);
766}
767
768static void
769nv_save_state_palette(struct drm_device *dev, int head,
770 struct nv04_mode_state *state)
771{
772 struct nouveau_object *device = nouveau_drm(dev)->device;
772 struct nvif_device *device = &nouveau_drm(dev)->device;
773 int head_offset = head * NV_PRMDIO_SIZE, i;
774
775 nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
776 NV_PRMDIO_PIXEL_MASK_MASK);
777 nvif_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0);
778
779 for (i = 0; i < 768; i++) {
780 state->crtc_reg[head].DAC[i] = nvif_rd08(device,
781 NV_PRMDIO_PALETTE_DATA + head_offset);
782 }
783
784 NVSetEnablePalette(dev, head, false);
785}
786
787void
788nouveau_hw_load_state_palette(struct drm_device *dev, int head,
789 struct nv04_mode_state *state)
790{
773 int head_offset = head * NV_PRMDIO_SIZE, i;
774
775 nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
776 NV_PRMDIO_PIXEL_MASK_MASK);
777 nvif_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0);
778
779 for (i = 0; i < 768; i++) {
780 state->crtc_reg[head].DAC[i] = nvif_rd08(device,
781 NV_PRMDIO_PALETTE_DATA + head_offset);
782 }
783
784 NVSetEnablePalette(dev, head, false);
785}
786
787void
788nouveau_hw_load_state_palette(struct drm_device *dev, int head,
789 struct nv04_mode_state *state)
790{
791 struct nouveau_object *device = nouveau_drm(dev)->device;
791 struct nvif_device *device = &nouveau_drm(dev)->device;
792 int head_offset = head * NV_PRMDIO_SIZE, i;
793
794 nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
795 NV_PRMDIO_PIXEL_MASK_MASK);
796 nvif_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0);
797
798 for (i = 0; i < 768; i++) {
799 nvif_wr08(device, NV_PRMDIO_PALETTE_DATA + head_offset,
800 state->crtc_reg[head].DAC[i]);
801 }
802
803 NVSetEnablePalette(dev, head, false);
804}
805
806void nouveau_hw_save_state(struct drm_device *dev, int head,
807 struct nv04_mode_state *state)
808{
809 struct nouveau_drm *drm = nouveau_drm(dev);
810
792 int head_offset = head * NV_PRMDIO_SIZE, i;
793
794 nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
795 NV_PRMDIO_PIXEL_MASK_MASK);
796 nvif_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0);
797
798 for (i = 0; i < 768; i++) {
799 nvif_wr08(device, NV_PRMDIO_PALETTE_DATA + head_offset,
800 state->crtc_reg[head].DAC[i]);
801 }
802
803 NVSetEnablePalette(dev, head, false);
804}
805
806void nouveau_hw_save_state(struct drm_device *dev, int head,
807 struct nv04_mode_state *state)
808{
809 struct nouveau_drm *drm = nouveau_drm(dev);
810
811 if (nv_device(drm->device)->chipset == 0x11)
811 if (drm->device.info.chipset == 0x11)
812 /* NB: no attempt is made to restore the bad pll later on */
813 nouveau_hw_fix_bad_vpll(dev, head);
814 nv_save_state_ramdac(dev, head, state);
815 nv_save_state_vga(dev, head, state);
816 nv_save_state_palette(dev, head, state);
817 nv_save_state_ext(dev, head, state);
818}
819
820void nouveau_hw_load_state(struct drm_device *dev, int head,
821 struct nv04_mode_state *state)
822{
823 NVVgaProtect(dev, head, true);
824 nv_load_state_ramdac(dev, head, state);
825 nv_load_state_ext(dev, head, state);
826 nouveau_hw_load_state_palette(dev, head, state);
827 nv_load_state_vga(dev, head, state);
828 NVVgaProtect(dev, head, false);
829}
812 /* NB: no attempt is made to restore the bad pll later on */
813 nouveau_hw_fix_bad_vpll(dev, head);
814 nv_save_state_ramdac(dev, head, state);
815 nv_save_state_vga(dev, head, state);
816 nv_save_state_palette(dev, head, state);
817 nv_save_state_ext(dev, head, state);
818}
819
820void nouveau_hw_load_state(struct drm_device *dev, int head,
821 struct nv04_mode_state *state)
822{
823 NVVgaProtect(dev, head, true);
824 nv_load_state_ramdac(dev, head, state);
825 nv_load_state_ext(dev, head, state);
826 nouveau_hw_load_state_palette(dev, head, state);
827 nv_load_state_vga(dev, head, state);
828 NVVgaProtect(dev, head, false);
829}