dfp.c (db2bec187dd68e79d512112df1f6e7a849e7f0ce) dfp.c (967e7bde8739fe3b215f7537e8f1f39c044902af)
1/*
2 * Copyright 2003 NVIDIA, Corporation
3 * Copyright 2006 Dave Airlie
4 * Copyright 2007 Maarten Maathuis
5 * Copyright 2007-2009 Stuart Bennett
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),

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276}
277
278
279static void nv04_dfp_mode_set(struct drm_encoder *encoder,
280 struct drm_display_mode *mode,
281 struct drm_display_mode *adjusted_mode)
282{
283 struct drm_device *dev = encoder->dev;
1/*
2 * Copyright 2003 NVIDIA, Corporation
3 * Copyright 2006 Dave Airlie
4 * Copyright 2007 Maarten Maathuis
5 * Copyright 2007-2009 Stuart Bennett
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),

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276}
277
278
279static void nv04_dfp_mode_set(struct drm_encoder *encoder,
280 struct drm_display_mode *mode,
281 struct drm_display_mode *adjusted_mode)
282{
283 struct drm_device *dev = encoder->dev;
284 struct nouveau_object *device = nouveau_drm(dev)->device;
284 struct nvif_device *device = &nouveau_drm(dev)->device;
285 struct nouveau_drm *drm = nouveau_drm(dev);
286 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
287 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
288 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
289 struct nouveau_connector *nv_connector = nouveau_crtc_connector_get(nv_crtc);
290 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
291 struct drm_display_mode *output_mode = &nv_encoder->mode;
292 struct drm_connector *connector = &nv_connector->base;

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411 regp->fp_vert_regs[FP_VALID_END] -= diff / 2;
412 }
413 }
414
415 /* Output property. */
416 if ((nv_connector->dithering_mode == DITHERING_MODE_ON) ||
417 (nv_connector->dithering_mode == DITHERING_MODE_AUTO &&
418 encoder->crtc->primary->fb->depth > connector->display_info.bpc * 3)) {
285 struct nouveau_drm *drm = nouveau_drm(dev);
286 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
287 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
288 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
289 struct nouveau_connector *nv_connector = nouveau_crtc_connector_get(nv_crtc);
290 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
291 struct drm_display_mode *output_mode = &nv_encoder->mode;
292 struct drm_connector *connector = &nv_connector->base;

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411 regp->fp_vert_regs[FP_VALID_END] -= diff / 2;
412 }
413 }
414
415 /* Output property. */
416 if ((nv_connector->dithering_mode == DITHERING_MODE_ON) ||
417 (nv_connector->dithering_mode == DITHERING_MODE_AUTO &&
418 encoder->crtc->primary->fb->depth > connector->display_info.bpc * 3)) {
419 if (nv_device(drm->device)->chipset == 0x11)
419 if (drm->device.info.chipset == 0x11)
420 regp->dither = savep->dither | 0x00010000;
421 else {
422 int i;
423 regp->dither = savep->dither | 0x00000001;
424 for (i = 0; i < 3; i++) {
425 regp->dither_regs[i] = 0xe4e4e4e4;
426 regp->dither_regs[i + 3] = 0x44444444;
427 }
428 }
429 } else {
420 regp->dither = savep->dither | 0x00010000;
421 else {
422 int i;
423 regp->dither = savep->dither | 0x00000001;
424 for (i = 0; i < 3; i++) {
425 regp->dither_regs[i] = 0xe4e4e4e4;
426 regp->dither_regs[i + 3] = 0x44444444;
427 }
428 }
429 } else {
430 if (nv_device(drm->device)->chipset != 0x11) {
430 if (drm->device.info.chipset != 0x11) {
431 /* reset them */
432 int i;
433 for (i = 0; i < 3; i++) {
434 regp->dither_regs[i] = savep->dither_regs[i];
435 regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
436 }
437 }
438 regp->dither = savep->dither;

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458 call_lvds_script(dev, dcbe, head, LVDS_RESET, nv_encoder->mode.clock);
459
460 /* update fp_control state for any changes made by scripts,
461 * so correct value is written at DPMS on */
462 nv04_display(dev)->mode_reg.crtc_reg[head].fp_control =
463 NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
464
465 /* This could use refinement for flatpanels, but it should work this way */
431 /* reset them */
432 int i;
433 for (i = 0; i < 3; i++) {
434 regp->dither_regs[i] = savep->dither_regs[i];
435 regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
436 }
437 }
438 regp->dither = savep->dither;

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458 call_lvds_script(dev, dcbe, head, LVDS_RESET, nv_encoder->mode.clock);
459
460 /* update fp_control state for any changes made by scripts,
461 * so correct value is written at DPMS on */
462 nv04_display(dev)->mode_reg.crtc_reg[head].fp_control =
463 NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
464
465 /* This could use refinement for flatpanels, but it should work this way */
466 if (nv_device(drm->device)->chipset < 0x44)
466 if (drm->device.info.chipset < 0x44)
467 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000);
468 else
469 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
470
471 /* Init external transmitters */
472 slave_encoder = get_tmds_slave(encoder);
473 if (slave_encoder)
474 get_slave_funcs(slave_encoder)->mode_set(

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480 nouveau_encoder_connector_get(nv_encoder)->base.name,
481 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
482}
483
484static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode)
485{
486#ifdef __powerpc__
487 struct drm_device *dev = encoder->dev;
467 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000);
468 else
469 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
470
471 /* Init external transmitters */
472 slave_encoder = get_tmds_slave(encoder);
473 if (slave_encoder)
474 get_slave_funcs(slave_encoder)->mode_set(

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480 nouveau_encoder_connector_get(nv_encoder)->base.name,
481 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
482}
483
484static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode)
485{
486#ifdef __powerpc__
487 struct drm_device *dev = encoder->dev;
488 struct nouveau_object *device = nouveau_drm(dev)->device;
488 struct nvif_device *device = &nouveau_drm(dev)->device;
489
490 /* BIOS scripts usually take care of the backlight, thanks
491 * Apple for your consistency.
492 */
493 if (dev->pdev->device == 0x0174 || dev->pdev->device == 0x0179 ||
494 dev->pdev->device == 0x0189 || dev->pdev->device == 0x0329) {
495 if (mode == DRM_MODE_DPMS_ON) {
496 nv_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 1 << 31);

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618 kfree(nv_encoder);
619}
620
621static void nv04_tmds_slave_init(struct drm_encoder *encoder)
622{
623 struct drm_device *dev = encoder->dev;
624 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
625 struct nouveau_drm *drm = nouveau_drm(dev);
489
490 /* BIOS scripts usually take care of the backlight, thanks
491 * Apple for your consistency.
492 */
493 if (dev->pdev->device == 0x0174 || dev->pdev->device == 0x0179 ||
494 dev->pdev->device == 0x0189 || dev->pdev->device == 0x0329) {
495 if (mode == DRM_MODE_DPMS_ON) {
496 nv_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 1 << 31);

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618 kfree(nv_encoder);
619}
620
621static void nv04_tmds_slave_init(struct drm_encoder *encoder)
622{
623 struct drm_device *dev = encoder->dev;
624 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
625 struct nouveau_drm *drm = nouveau_drm(dev);
626 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
626 struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
627 struct nouveau_i2c_port *port = i2c->find(i2c, 2);
628 struct nouveau_i2c_board_info info[] = {
629 {
630 {
631 .type = "sil164",
632 .addr = (dcb->tmdsconf.slave_addr == 0x7 ? 0x3a : 0x38),
633 .platform_data = &(struct sil164_encoder_params) {
634 SIL164_INPUT_EDGE_RISING

--- 88 unchanged lines hidden --- 		627 struct nouveau_i2c_port *port = i2c->find(i2c, 2);
628 struct nouveau_i2c_board_info info[] = {
629 {
630 {
631 .type = "sil164",
632 .addr = (dcb->tmdsconf.slave_addr == 0x7 ? 0x3a : 0x38),
633 .platform_data = &(struct sil164_encoder_params) {
634 SIL164_INPUT_EDGE_RISING

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