crtc.c (4b5098f3597195e9faf17e5a0cfca905d9a04d9f) crtc.c (967e7bde8739fe3b215f7537e8f1f39c044902af)
1/*
2 * Copyright 1993-2003 NVIDIA, Corporation
3 * Copyright 2006 Dave Airlie
4 * Copyright 2007 Maarten Maathuis
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 97 unchanged lines hidden (view full) ---

106 * bits 20-23: (mpll) something to do with post divider?
107 * bits 28-31: related to single stage mode? (bit 8/12)
108 */
109
110static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock)
111{
112 struct drm_device *dev = crtc->dev;
113 struct nouveau_drm *drm = nouveau_drm(dev);
1/*
2 * Copyright 1993-2003 NVIDIA, Corporation
3 * Copyright 2006 Dave Airlie
4 * Copyright 2007 Maarten Maathuis
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 97 unchanged lines hidden (view full) ---

106 * bits 20-23: (mpll) something to do with post divider?
107 * bits 28-31: related to single stage mode? (bit 8/12)
108 */
109
110static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock)
111{
112 struct drm_device *dev = crtc->dev;
113 struct nouveau_drm *drm = nouveau_drm(dev);
114 struct nouveau_bios *bios = nouveau_bios(drm->device);
115 struct nouveau_clock *clk = nouveau_clock(drm->device);
114 struct nouveau_bios *bios = nvkm_bios(&drm->device);
115 struct nouveau_clock *clk = nvkm_clock(&drm->device);
116 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
117 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
118 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
119 struct nouveau_pll_vals *pv = &regp->pllvals;
120 struct nvbios_pll pll_lim;
121
122 if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0,
123 &pll_lim))

--- 7 unchanged lines hidden (view full) ---

131 * output frequency of the first stage for this card is 300MHz, it is
132 * assumed the threshold is given by vco1 maxfreq/2
133 */
134 /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6,
135 * not 8, others unknown), the blob always uses both plls. no problem
136 * has yet been observed in allowing the use a single stage pll on all
137 * nv43 however. the behaviour of single stage use is untested on nv40
138 */
116 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
117 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
118 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
119 struct nouveau_pll_vals *pv = &regp->pllvals;
120 struct nvbios_pll pll_lim;
121
122 if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0,
123 &pll_lim))

--- 7 unchanged lines hidden (view full) ---

131 * output frequency of the first stage for this card is 300MHz, it is
132 * assumed the threshold is given by vco1 maxfreq/2
133 */
134 /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6,
135 * not 8, others unknown), the blob always uses both plls. no problem
136 * has yet been observed in allowing the use a single stage pll on all
137 * nv43 however. the behaviour of single stage use is untested on nv40
138 */
139 if (nv_device(drm->device)->chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2))
139 if (drm->device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2))
140 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2));
141
142
143 if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv))
144 return;
145
146 state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK;
147
148 /* The blob uses this always, so let's do the same */
140 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2));
141
142
143 if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv))
144 return;
145
146 state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK;
147
148 /* The blob uses this always, so let's do the same */
149 if (nv_device(drm->device)->card_type == NV_40)
149 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
150 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE;
151 /* again nv40 and some nv43 act more like nv3x as described above */
150 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE;
151 /* again nv40 and some nv43 act more like nv3x as described above */
152 if (nv_device(drm->device)->chipset < 0x41)
152 if (drm->device.info.chipset < 0x41)
153 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL |
154 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL;
155 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK;
156
157 if (pv->NM2)
158 NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n",
159 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
160 else

--- 109 unchanged lines hidden (view full) ---

270 if (fp_output) {
271 vertStart = vertTotal - 3;
272 vertEnd = vertTotal - 2;
273 vertBlankStart = vertStart;
274 horizStart = horizTotal - 5;
275 horizEnd = horizTotal - 2;
276 horizBlankEnd = horizTotal + 4;
277#if 0
153 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL |
154 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL;
155 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK;
156
157 if (pv->NM2)
158 NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n",
159 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
160 else

--- 109 unchanged lines hidden (view full) ---

270 if (fp_output) {
271 vertStart = vertTotal - 3;
272 vertEnd = vertTotal - 2;
273 vertBlankStart = vertStart;
274 horizStart = horizTotal - 5;
275 horizEnd = horizTotal - 2;
276 horizBlankEnd = horizTotal + 4;
277#if 0
278 if (dev->overlayAdaptor && nv_device(drm->device)->card_type >= NV_10)
278 if (dev->overlayAdaptor && drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
279 /* This reportedly works around some video overlay bandwidth problems */
280 horizTotal += 2;
281#endif
282 }
283
284 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
285 vertTotal |= 1;
286

--- 217 unchanged lines hidden (view full) ---

504 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY;
505 }
506#endif
507
508 /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */
509 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 |
510 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 |
511 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM;
279 /* This reportedly works around some video overlay bandwidth problems */
280 horizTotal += 2;
281#endif
282 }
283
284 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
285 vertTotal |= 1;
286

--- 217 unchanged lines hidden (view full) ---

504 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY;
505 }
506#endif
507
508 /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */
509 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 |
510 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 |
511 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM;
512 if (nv_device(drm->device)->chipset >= 0x11)
512 if (drm->device.info.chipset >= 0x11)
513 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32;
514 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
515 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE;
516
517 /* Unblock some timings */
518 regp->CRTC[NV_CIO_CRE_53] = 0;
519 regp->CRTC[NV_CIO_CRE_54] = 0;
520

--- 24 unchanged lines hidden (view full) ---

545 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
546 if (!nv_crtc->index)
547 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4;
548
549 /* the blob sometimes sets |= 0x10 (which is the same as setting |=
550 * 1 << 30 on 0x60.830), for no apparent reason */
551 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital;
552
513 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32;
514 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
515 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE;
516
517 /* Unblock some timings */
518 regp->CRTC[NV_CIO_CRE_53] = 0;
519 regp->CRTC[NV_CIO_CRE_54] = 0;
520

--- 24 unchanged lines hidden (view full) ---

545 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
546 if (!nv_crtc->index)
547 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4;
548
549 /* the blob sometimes sets |= 0x10 (which is the same as setting |=
550 * 1 << 30 on 0x60.830), for no apparent reason */
551 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital;
552
553 if (nv_device(drm->device)->card_type >= NV_30)
553 if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
554 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;
555
556 regp->crtc_830 = mode->crtc_vdisplay - 3;
557 regp->crtc_834 = mode->crtc_vdisplay - 1;
558
554 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;
555
556 regp->crtc_830 = mode->crtc_vdisplay - 3;
557 regp->crtc_834 = mode->crtc_vdisplay - 1;
558
559 if (nv_device(drm->device)->card_type == NV_40)
559 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
560 /* This is what the blob does */
561 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850);
562
560 /* This is what the blob does */
561 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850);
562
563 if (nv_device(drm->device)->card_type >= NV_30)
563 if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
564 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT);
565
564 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT);
565
566 if (nv_device(drm->device)->card_type >= NV_10)
566 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
567 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC;
568 else
569 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC;
570
571 /* Some misc regs */
567 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC;
568 else
569 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC;
570
571 /* Some misc regs */
572 if (nv_device(drm->device)->card_type == NV_40) {
572 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) {
573 regp->CRTC[NV_CIO_CRE_85] = 0xFF;
574 regp->CRTC[NV_CIO_CRE_86] = 0x1;
575 }
576
577 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->primary->fb->depth + 1) / 8;
578 /* Enable slaved mode (called MODE_TV in nv4ref.h) */
579 if (lvds_output || tmds_output || tv_output)
580 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
581
582 /* Generic PRAMDAC regs */
583
573 regp->CRTC[NV_CIO_CRE_85] = 0xFF;
574 regp->CRTC[NV_CIO_CRE_86] = 0x1;
575 }
576
577 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->primary->fb->depth + 1) / 8;
578 /* Enable slaved mode (called MODE_TV in nv4ref.h) */
579 if (lvds_output || tmds_output || tv_output)
580 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
581
582 /* Generic PRAMDAC regs */
583
584 if (nv_device(drm->device)->card_type >= NV_10)
584 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
585 /* Only bit that bios and blob set. */
586 regp->nv10_cursync = (1 << 25);
587
588 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS |
589 NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL |
590 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON;
591 if (crtc->primary->fb->depth == 16)
592 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
585 /* Only bit that bios and blob set. */
586 regp->nv10_cursync = (1 << 25);
587
588 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS |
589 NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL |
590 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON;
591 if (crtc->primary->fb->depth == 16)
592 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
593 if (nv_device(drm->device)->chipset >= 0x11)
593 if (drm->device.info.chipset >= 0x11)
594 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG;
595
596 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */
597 regp->tv_setup = 0;
598
599 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness);
600
601 /* Some values the blob sets */

--- 46 unchanged lines hidden (view full) ---

648 if (ret)
649 return ret;
650
651 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */
652 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1);
653
654 nv_crtc_mode_set_vga(crtc, adjusted_mode);
655 /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */
594 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG;
595
596 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */
597 regp->tv_setup = 0;
598
599 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness);
600
601 /* Some values the blob sets */

--- 46 unchanged lines hidden (view full) ---

648 if (ret)
649 return ret;
650
651 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */
652 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1);
653
654 nv_crtc_mode_set_vga(crtc, adjusted_mode);
655 /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */
656 if (nv_device(drm->device)->card_type == NV_40)
656 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
657 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
658 nv_crtc_mode_set_regs(crtc, adjusted_mode);
659 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock);
660 return 0;
661}
662
663static void nv_crtc_save(struct drm_crtc *crtc)
664{

--- 44 unchanged lines hidden (view full) ---

709
710 drm_vblank_pre_modeset(dev, nv_crtc->index);
711 funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
712
713 NVBlankScreen(dev, nv_crtc->index, true);
714
715 /* Some more preparation. */
716 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
657 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
658 nv_crtc_mode_set_regs(crtc, adjusted_mode);
659 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock);
660 return 0;
661}
662
663static void nv_crtc_save(struct drm_crtc *crtc)
664{

--- 44 unchanged lines hidden (view full) ---

709
710 drm_vblank_pre_modeset(dev, nv_crtc->index);
711 funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
712
713 NVBlankScreen(dev, nv_crtc->index, true);
714
715 /* Some more preparation. */
716 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
717 if (nv_device(drm->device)->card_type == NV_40) {
717 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) {
718 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900);
719 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000);
720 }
721}
722
723static void nv_crtc_commit(struct drm_crtc *crtc)
724{
725 struct drm_device *dev = crtc->dev;

--- 157 unchanged lines hidden (view full) ---

883 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->bits_per_pixel,
884 &arb_burst, &arb_lwm);
885
886 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst;
887 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff;
888 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
889 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
890
718 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900);
719 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000);
720 }
721}
722
723static void nv_crtc_commit(struct drm_crtc *crtc)
724{
725 struct drm_device *dev = crtc->dev;

--- 157 unchanged lines hidden (view full) ---

883 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->bits_per_pixel,
884 &arb_burst, &arb_lwm);
885
886 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst;
887 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff;
888 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
889 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
890
891 if (nv_device(drm->device)->card_type >= NV_20) {
891 if (drm->device.info.family >= NV_DEVICE_INFO_V0_KELVIN) {
892 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8;
893 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47);
894 }
895
896 return 0;
897}
898
899static int

--- 64 unchanged lines hidden (view full) ---

964 alpha = pixel >> 24;
965 if (alpha > 0 && alpha < 255)
966 pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24);
967
968#ifdef __BIG_ENDIAN
969 {
970 struct nouveau_drm *drm = nouveau_drm(dev);
971
892 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8;
893 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47);
894 }
895
896 return 0;
897}
898
899static int

--- 64 unchanged lines hidden (view full) ---

964 alpha = pixel >> 24;
965 if (alpha > 0 && alpha < 255)
966 pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24);
967
968#ifdef __BIG_ENDIAN
969 {
970 struct nouveau_drm *drm = nouveau_drm(dev);
971
972 if (nv_device(drm->device)->chipset == 0x11) {
972 if (drm->device.info.chipset == 0x11) {
973 pixel = ((pixel & 0x000000ff) << 24) |
974 ((pixel & 0x0000ff00) << 8) |
975 ((pixel & 0x00ff0000) >> 8) |
976 ((pixel & 0xff000000) >> 24);
977 }
978 }
979#endif
980

--- 24 unchanged lines hidden (view full) ---

1005 if (!gem)
1006 return -ENOENT;
1007 cursor = nouveau_gem_object(gem);
1008
1009 ret = nouveau_bo_map(cursor);
1010 if (ret)
1011 goto out;
1012
973 pixel = ((pixel & 0x000000ff) << 24) |
974 ((pixel & 0x0000ff00) << 8) |
975 ((pixel & 0x00ff0000) >> 8) |
976 ((pixel & 0xff000000) >> 24);
977 }
978 }
979#endif
980

--- 24 unchanged lines hidden (view full) ---

1005 if (!gem)
1006 return -ENOENT;
1007 cursor = nouveau_gem_object(gem);
1008
1009 ret = nouveau_bo_map(cursor);
1010 if (ret)
1011 goto out;
1012
1013 if (nv_device(drm->device)->chipset >= 0x11)
1013 if (drm->device.info.chipset >= 0x11)
1014 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
1015 else
1016 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
1017
1018 nouveau_bo_unmap(cursor);
1019 nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset;
1020 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
1021 nv_crtc->cursor.show(nv_crtc, true);

--- 124 unchanged lines hidden --- 		1014 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
1015 else
1016 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
1017
1018 nouveau_bo_unmap(cursor);
1019 nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset;
1020 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
1021 nv_crtc->cursor.show(nv_crtc, true);

--- 124 unchanged lines hidden ---