| arb.c (db2bec187dd68e79d512112df1f6e7a849e7f0ce) | arb.c (967e7bde8739fe3b215f7537e8f1f39c044902af) |
|---|---|
| 1/* 2 * Copyright 1993-2003 NVIDIA, Corporation 3 * Copyright 2007-2009 Stuart Bennett 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, --- 184 unchanged lines hidden (view full) --- 193 fifo->lwm = min_lwm + 10 * (max_lwm - min_lwm) / 100; /* Empirical. */ 194} 195 196static void 197nv04_update_arb(struct drm_device *dev, int VClk, int bpp, 198 int *burst, int *lwm) 199{ 200 struct nouveau_drm *drm = nouveau_drm(dev); | 1/* 2 * Copyright 1993-2003 NVIDIA, Corporation 3 * Copyright 2007-2009 Stuart Bennett 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, --- 184 unchanged lines hidden (view full) --- 193 fifo->lwm = min_lwm + 10 * (max_lwm - min_lwm) / 100; /* Empirical. */ 194} 195 196static void 197nv04_update_arb(struct drm_device *dev, int VClk, int bpp, 198 int *burst, int *lwm) 199{ 200 struct nouveau_drm *drm = nouveau_drm(dev); |
| 201 struct nouveau_object *device = nouveau_drm(dev)->device; | 201 struct nvif_device *device = &nouveau_drm(dev)->device; |
| 202 struct nv_fifo_info fifo_data; 203 struct nv_sim_state sim_data; 204 int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY); 205 int NVClk = nouveau_hw_get_clock(dev, PLL_CORE); 206 uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1); 207 208 sim_data.pclk_khz = VClk; 209 sim_data.mclk_khz = MClk; --- 12 unchanged lines hidden (view full) --- 222 sim_data.mem_page_miss = 10; 223 } else { 224 sim_data.memory_type = nvif_rd32(device, NV04_PFB_CFG0) & 0x1; 225 sim_data.memory_width = (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64; 226 sim_data.mem_latency = cfg1 & 0xf; 227 sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1); 228 } 229 | 202 struct nv_fifo_info fifo_data; 203 struct nv_sim_state sim_data; 204 int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY); 205 int NVClk = nouveau_hw_get_clock(dev, PLL_CORE); 206 uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1); 207 208 sim_data.pclk_khz = VClk; 209 sim_data.mclk_khz = MClk; --- 12 unchanged lines hidden (view full) --- 222 sim_data.mem_page_miss = 10; 223 } else { 224 sim_data.memory_type = nvif_rd32(device, NV04_PFB_CFG0) & 0x1; 225 sim_data.memory_width = (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64; 226 sim_data.mem_latency = cfg1 & 0xf; 227 sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1); 228 } 229 |
| 230 if (nv_device(drm->device)->card_type == NV_04) | 230 if (drm->device.info.family == NV_DEVICE_INFO_V0_TNT) |
| 231 nv04_calc_arb(&fifo_data, &sim_data); 232 else 233 nv10_calc_arb(&fifo_data, &sim_data); 234 235 *burst = ilog2(fifo_data.burst >> 4); 236 *lwm = fifo_data.lwm >> 3; 237} 238 --- 10 unchanged lines hidden (view full) --- 249 *lwm = graphics_lwm >> 3; 250} 251 252void 253nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm) 254{ 255 struct nouveau_drm *drm = nouveau_drm(dev); 256 | 231 nv04_calc_arb(&fifo_data, &sim_data); 232 else 233 nv10_calc_arb(&fifo_data, &sim_data); 234 235 *burst = ilog2(fifo_data.burst >> 4); 236 *lwm = fifo_data.lwm >> 3; 237} 238 --- 10 unchanged lines hidden (view full) --- 249 *lwm = graphics_lwm >> 3; 250} 251 252void 253nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm) 254{ 255 struct nouveau_drm *drm = nouveau_drm(dev); 256 |
| 257 if (nv_device(drm->device)->card_type < NV_20) | 257 if (drm->device.info.family < NV_DEVICE_INFO_V0_KELVIN) |
| 258 nv04_update_arb(dev, vclk, bpp, burst, lwm); 259 else if ((dev->pdev->device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ || 260 (dev->pdev->device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) { 261 *burst = 128; 262 *lwm = 0x0480; 263 } else 264 nv20_update_arb(burst, lwm); 265} | 258 nv04_update_arb(dev, vclk, bpp, burst, lwm); 259 else if ((dev->pdev->device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ || 260 (dev->pdev->device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) { 261 *burst = 128; 262 *lwm = 0x0480; 263 } else 264 nv20_update_arb(burst, lwm); 265} |