arb.c (8dd06ef34b6e2f41b29fbf5fc1663780f2524285) arb.c (4c0d42f7ba7f27054f6e21636850c70d624f3cd2)
1/*
2 * Copyright 1993-2003 NVIDIA, Corporation
3 * Copyright 2007-2009 Stuart Bennett
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

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195{
196 struct nouveau_drm *drm = nouveau_drm(dev);
197 struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
198 struct nv_fifo_info fifo_data;
199 struct nv_sim_state sim_data;
200 int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY);
201 int NVClk = nouveau_hw_get_clock(dev, PLL_CORE);
202 uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1);
1/*
2 * Copyright 1993-2003 NVIDIA, Corporation
3 * Copyright 2007-2009 Stuart Bennett
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

--- 186 unchanged lines hidden (view full) ---

195{
196 struct nouveau_drm *drm = nouveau_drm(dev);
197 struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
198 struct nv_fifo_info fifo_data;
199 struct nv_sim_state sim_data;
200 int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY);
201 int NVClk = nouveau_hw_get_clock(dev, PLL_CORE);
202 uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1);
203 struct pci_dev *pdev = to_pci_dev(dev->dev);
203
204 sim_data.pclk_khz = VClk;
205 sim_data.mclk_khz = MClk;
206 sim_data.nvclk_khz = NVClk;
207 sim_data.bpp = bpp;
208 sim_data.two_heads = nv_two_heads(dev);
204
205 sim_data.pclk_khz = VClk;
206 sim_data.mclk_khz = MClk;
207 sim_data.nvclk_khz = NVClk;
208 sim_data.bpp = bpp;
209 sim_data.two_heads = nv_two_heads(dev);
209 if ((dev->pdev->device & 0xffff) == 0x01a0 /*CHIPSET_NFORCE*/ ||
210 (dev->pdev->device & 0xffff) == 0x01f0 /*CHIPSET_NFORCE2*/) {
210 if ((pdev->device & 0xffff) == 0x01a0 /*CHIPSET_NFORCE*/ ||
211 (pdev->device & 0xffff) == 0x01f0 /*CHIPSET_NFORCE2*/) {
211 uint32_t type;
212 uint32_t type;
212 int domain = pci_domain_nr(dev->pdev->bus);
213 int domain = pci_domain_nr(pdev->bus);
213
214 pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 1),
215 0x7c, &type);
216
217 sim_data.memory_type = (type >> 12) & 1;
218 sim_data.memory_width = 64;
219 sim_data.mem_latency = 3;
220 sim_data.mem_page_miss = 10;

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246 *burst = ilog2(burst_size >> 5);
247 *lwm = graphics_lwm >> 3;
248}
249
250void
251nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm)
252{
253 struct nouveau_drm *drm = nouveau_drm(dev);
214
215 pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 1),
216 0x7c, &type);
217
218 sim_data.memory_type = (type >> 12) & 1;
219 sim_data.memory_width = 64;
220 sim_data.mem_latency = 3;
221 sim_data.mem_page_miss = 10;

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247 *burst = ilog2(burst_size >> 5);
248 *lwm = graphics_lwm >> 3;
249}
250
251void
252nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm)
253{
254 struct nouveau_drm *drm = nouveau_drm(dev);
255 struct pci_dev *pdev = to_pci_dev(dev->dev);
254
255 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN)
256 nv04_update_arb(dev, vclk, bpp, burst, lwm);
256
257 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN)
258 nv04_update_arb(dev, vclk, bpp, burst, lwm);
257 else if ((dev->pdev->device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ ||
258 (dev->pdev->device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) {
259 else if ((pdev->device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ ||
260 (pdev->device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) {
259 *burst = 128;
260 *lwm = 0x0480;
261 } else
262 nv20_update_arb(burst, lwm);
263}
261 *burst = 128;
262 *lwm = 0x0480;
263 } else
264 nv20_update_arb(burst, lwm);
265}