a6xx.xml.h (4b4193256c8d3bc3a5397b5cd9494c2ad386317d) a6xx.xml.h (cc4c26d4ae4e458669d46ff69f16ac0c74f7cd49)
1#ifndef A6XX_XML
2#define A6XX_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
1#ifndef A6XX_XML
2#define A6XX_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
11- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24
24
25Copyright (C) 2013-2020 by the following authors:
25Copyright (C) 2013-2021 by the following authors:
26- Rob Clark <robdclark@gmail.com> (robclark)
27- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
29Permission is hereby granted, free of charge, to any person obtaining
30a copy of this software and associated documentation files (the
31"Software"), to deal in the Software without restriction, including
32without limitation the rights to use, copy, modify, merge, publish,
33distribute, sublicense, and/or sell copies of the Software, and to

--- 129 unchanged lines hidden (view full) ---

163 FMT6_ASTC_8x6 = 199,
164 FMT6_ASTC_8x8 = 200,
165 FMT6_ASTC_10x5 = 201,
166 FMT6_ASTC_10x6 = 202,
167 FMT6_ASTC_10x8 = 203,
168 FMT6_ASTC_10x10 = 204,
169 FMT6_ASTC_12x10 = 205,
170 FMT6_ASTC_12x12 = 206,
26- Rob Clark <robdclark@gmail.com> (robclark)
27- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
29Permission is hereby granted, free of charge, to any person obtaining
30a copy of this software and associated documentation files (the
31"Software"), to deal in the Software without restriction, including
32without limitation the rights to use, copy, modify, merge, publish,
33distribute, sublicense, and/or sell copies of the Software, and to

--- 129 unchanged lines hidden (view full) ---

163 FMT6_ASTC_8x6 = 199,
164 FMT6_ASTC_8x8 = 200,
165 FMT6_ASTC_10x5 = 201,
166 FMT6_ASTC_10x6 = 202,
167 FMT6_ASTC_10x8 = 203,
168 FMT6_ASTC_10x10 = 204,
169 FMT6_ASTC_12x10 = 205,
170 FMT6_ASTC_12x12 = 206,
171 FMT6_S8Z24_UINT = 234,
171 FMT6_Z24_UINT_S8_UINT = 234,
172 FMT6_NONE = 255,
173};
174
175enum a6xx_polygon_mode {
176 POLYMODE6_POINTS = 1,
177 POLYMODE6_LINES = 2,
178 POLYMODE6_TRIANGLES = 3,
179};

--- 722 unchanged lines hidden (view full) ---

902
903enum a6xx_tess_output {
904 TESS_POINTS = 0,
905 TESS_LINES = 1,
906 TESS_CW_TRIS = 2,
907 TESS_CCW_TRIS = 3,
908};
909
172 FMT6_NONE = 255,
173};
174
175enum a6xx_polygon_mode {
176 POLYMODE6_POINTS = 1,
177 POLYMODE6_LINES = 2,
178 POLYMODE6_TRIANGLES = 3,
179};

--- 722 unchanged lines hidden (view full) ---

902
903enum a6xx_tess_output {
904 TESS_POINTS = 0,
905 TESS_LINES = 1,
906 TESS_CW_TRIS = 2,
907 TESS_CCW_TRIS = 3,
908};
909
910enum a6xx_threadsize {
911 THREAD64 = 0,
912 THREAD128 = 1,
913};
914
910enum a6xx_tex_filter {
911 A6XX_TEX_NEAREST = 0,
912 A6XX_TEX_LINEAR = 1,
913 A6XX_TEX_ANISO = 2,
914 A6XX_TEX_CUBIC = 3,
915};
916
917enum a6xx_tex_clamp {

--- 84 unchanged lines hidden (view full) ---

1002#define A6XX_CP_CP2GMU_STATUS_IFPC 0x00000001
1003
1004#define REG_A6XX_CP_HW_FAULT 0x00000821
1005
1006#define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823
1007
1008#define REG_A6XX_CP_PROTECT_STATUS 0x00000824
1009
915enum a6xx_tex_filter {
916 A6XX_TEX_NEAREST = 0,
917 A6XX_TEX_LINEAR = 1,
918 A6XX_TEX_ANISO = 2,
919 A6XX_TEX_CUBIC = 3,
920};
921
922enum a6xx_tex_clamp {

--- 84 unchanged lines hidden (view full) ---

1007#define A6XX_CP_CP2GMU_STATUS_IFPC 0x00000001
1008
1009#define REG_A6XX_CP_HW_FAULT 0x00000821
1010
1011#define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823
1012
1013#define REG_A6XX_CP_PROTECT_STATUS 0x00000824
1014
1010#define REG_A6XX_CP_SQE_INSTR_BASE_LO 0x00000830
1015#define REG_A6XX_CP_SQE_INSTR_BASE 0x00000830
1011
1016
1012#define REG_A6XX_CP_SQE_INSTR_BASE_HI 0x00000831
1013
1014#define REG_A6XX_CP_MISC_CNTL 0x00000840
1015
1016#define REG_A6XX_CP_APRIV_CNTL 0x00000844
1017
1018#define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1
1019#define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK 0x000000ff
1020#define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT 0
1021static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val)

--- 77 unchanged lines hidden (view full) ---

1099#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO 0x000008a5
1100
1101#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI 0x000008a6
1102
1103#define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO 0x000008a7
1104
1105#define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8
1106
1017#define REG_A6XX_CP_MISC_CNTL 0x00000840
1018
1019#define REG_A6XX_CP_APRIV_CNTL 0x00000844
1020
1021#define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1
1022#define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK 0x000000ff
1023#define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT 0
1024static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val)

--- 77 unchanged lines hidden (view full) ---

1102#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO 0x000008a5
1103
1104#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI 0x000008a6
1105
1106#define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO 0x000008a7
1107
1108#define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8
1109
1107#define REG_A6XX_CP_PERFCTR_CP_SEL_0 0x000008d0
1110static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; }
1108
1111
1109#define REG_A6XX_CP_PERFCTR_CP_SEL_1 0x000008d1
1110
1111#define REG_A6XX_CP_PERFCTR_CP_SEL_2 0x000008d2
1112
1113#define REG_A6XX_CP_PERFCTR_CP_SEL_3 0x000008d3
1114
1115#define REG_A6XX_CP_PERFCTR_CP_SEL_4 0x000008d4
1116
1117#define REG_A6XX_CP_PERFCTR_CP_SEL_5 0x000008d5
1118
1119#define REG_A6XX_CP_PERFCTR_CP_SEL_6 0x000008d6
1120
1121#define REG_A6XX_CP_PERFCTR_CP_SEL_7 0x000008d7
1122
1123#define REG_A6XX_CP_PERFCTR_CP_SEL_8 0x000008d8
1124
1125#define REG_A6XX_CP_PERFCTR_CP_SEL_9 0x000008d9
1126
1127#define REG_A6XX_CP_PERFCTR_CP_SEL_10 0x000008da
1128
1129#define REG_A6XX_CP_PERFCTR_CP_SEL_11 0x000008db
1130
1131#define REG_A6XX_CP_PERFCTR_CP_SEL_12 0x000008dc
1132
1133#define REG_A6XX_CP_PERFCTR_CP_SEL_13 0x000008dd
1134
1135#define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900
1136
1137#define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI 0x00000901
1138
1139#define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902
1140
1141#define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903
1142

--- 28 unchanged lines hidden (view full) ---

1171#define REG_A6XX_CP_IB2_BASE_HI 0x0000092c
1172
1173#define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d
1174
1175#define REG_A6XX_CP_SDS_BASE 0x0000092e
1176
1177#define REG_A6XX_CP_SDS_BASE_HI 0x0000092f
1178
1112#define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900
1113
1114#define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI 0x00000901
1115
1116#define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902
1117
1118#define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903
1119

--- 28 unchanged lines hidden (view full) ---

1148#define REG_A6XX_CP_IB2_BASE_HI 0x0000092c
1149
1150#define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d
1151
1152#define REG_A6XX_CP_SDS_BASE 0x0000092e
1153
1154#define REG_A6XX_CP_SDS_BASE_HI 0x0000092f
1155
1179#define REG_A6XX_CP_SDS_REM_SIZE 0x0000092e
1156#define REG_A6XX_CP_SDS_REM_SIZE 0x00000930
1180
1157
1181#define REG_A6XX_CP_BIN_SIZE_ADDRESS 0x00000931
1158#define REG_A6XX_CP_MRB_BASE 0x00000931
1182
1159
1183#define REG_A6XX_CP_BIN_SIZE_ADDRESS_HI 0x00000932
1160#define REG_A6XX_CP_MRB_BASE_HI 0x00000932
1184
1161
1185#define REG_A6XX_CP_BIN_DATA_ADDR 0x00000934
1162#define REG_A6XX_CP_MRB_REM_SIZE 0x00000933
1186
1163
1187#define REG_A6XX_CP_BIN_DATA_ADDR_HI 0x00000935
1164#define REG_A6XX_CP_VSD_BASE 0x00000934
1188
1165
1166#define REG_A6XX_CP_VSD_BASE_HI 0x00000935
1167
1168#define REG_A6XX_CP_MRB_DWORDS 0x00000946
1169
1170#define REG_A6XX_CP_VSD_DWORDS 0x00000947
1171
1189#define REG_A6XX_CP_CSQ_IB1_STAT 0x00000949
1190#define A6XX_CP_CSQ_IB1_STAT_REM__MASK 0xffff0000
1191#define A6XX_CP_CSQ_IB1_STAT_REM__SHIFT 16
1192static inline uint32_t A6XX_CP_CSQ_IB1_STAT_REM(uint32_t val)
1193{
1194 return ((val) << A6XX_CP_CSQ_IB1_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB1_STAT_REM__MASK;
1195}
1196
1197#define REG_A6XX_CP_CSQ_IB2_STAT 0x0000094a
1198#define A6XX_CP_CSQ_IB2_STAT_REM__MASK 0xffff0000
1199#define A6XX_CP_CSQ_IB2_STAT_REM__SHIFT 16
1200static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val)
1201{
1202 return ((val) << A6XX_CP_CSQ_IB2_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB2_STAT_REM__MASK;
1203}
1204
1172#define REG_A6XX_CP_CSQ_IB1_STAT 0x00000949
1173#define A6XX_CP_CSQ_IB1_STAT_REM__MASK 0xffff0000
1174#define A6XX_CP_CSQ_IB1_STAT_REM__SHIFT 16
1175static inline uint32_t A6XX_CP_CSQ_IB1_STAT_REM(uint32_t val)
1176{
1177 return ((val) << A6XX_CP_CSQ_IB1_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB1_STAT_REM__MASK;
1178}
1179
1180#define REG_A6XX_CP_CSQ_IB2_STAT 0x0000094a
1181#define A6XX_CP_CSQ_IB2_STAT_REM__MASK 0xffff0000
1182#define A6XX_CP_CSQ_IB2_STAT_REM__SHIFT 16
1183static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val)
1184{
1185 return ((val) << A6XX_CP_CSQ_IB2_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB2_STAT_REM__MASK;
1186}
1187
1188#define REG_A6XX_CP_MRQ_MRB_STAT 0x0000094c
1189#define A6XX_CP_MRQ_MRB_STAT_REM__MASK 0xffff0000
1190#define A6XX_CP_MRQ_MRB_STAT_REM__SHIFT 16
1191static inline uint32_t A6XX_CP_MRQ_MRB_STAT_REM(uint32_t val)
1192{
1193 return ((val) << A6XX_CP_MRQ_MRB_STAT_REM__SHIFT) & A6XX_CP_MRQ_MRB_STAT_REM__MASK;
1194}
1195
1205#define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980
1206
1207#define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981
1208
1209#define REG_A6XX_CP_AHB_CNTL 0x0000098d
1210
1211#define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00
1212
1213#define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03
1214
1196#define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980
1197
1198#define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981
1199
1200#define REG_A6XX_CP_AHB_CNTL 0x0000098d
1201
1202#define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00
1203
1204#define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03
1205
1206#define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE 0x00000b34
1207
1208#define REG_A6XX_CP_LPAC_SQE_INSTR_BASE 0x00000b82
1209
1215#define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01
1216
1217#define REG_A6XX_RBBM_INT_0_STATUS 0x00000201
1218
1219#define REG_A6XX_RBBM_STATUS 0x00000210
1220#define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000
1221#define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000
1222#define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000

--- 19 unchanged lines hidden (view full) ---

1242#define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002
1243#define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001
1244
1245#define REG_A6XX_RBBM_STATUS3 0x00000213
1246#define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000
1247
1248#define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215
1249
1210#define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01
1211
1212#define REG_A6XX_RBBM_INT_0_STATUS 0x00000201
1213
1214#define REG_A6XX_RBBM_STATUS 0x00000210
1215#define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000
1216#define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000
1217#define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000

--- 19 unchanged lines hidden (view full) ---

1237#define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002
1238#define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001
1239
1240#define REG_A6XX_RBBM_STATUS3 0x00000213
1241#define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000
1242
1243#define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215
1244
1250#define REG_A6XX_RBBM_PERFCTR_CP_0_LO 0x00000400
1245static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; }
1251
1246
1252#define REG_A6XX_RBBM_PERFCTR_CP_0_HI 0x00000401
1247static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; }
1253
1248
1254#define REG_A6XX_RBBM_PERFCTR_CP_1_LO 0x00000402
1249static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; }
1255
1250
1256#define REG_A6XX_RBBM_PERFCTR_CP_1_HI 0x00000403
1251static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; }
1257
1252
1258#define REG_A6XX_RBBM_PERFCTR_CP_2_LO 0x00000404
1253static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; }
1259
1254
1260#define REG_A6XX_RBBM_PERFCTR_CP_2_HI 0x00000405
1255static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; }
1261
1256
1262#define REG_A6XX_RBBM_PERFCTR_CP_3_LO 0x00000406
1257static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; }
1263
1258
1264#define REG_A6XX_RBBM_PERFCTR_CP_3_HI 0x00000407
1259static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; }
1265
1260
1266#define REG_A6XX_RBBM_PERFCTR_CP_4_LO 0x00000408
1261static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; }
1267
1262
1268#define REG_A6XX_RBBM_PERFCTR_CP_4_HI 0x00000409
1263static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; }
1269
1264
1270#define REG_A6XX_RBBM_PERFCTR_CP_5_LO 0x0000040a
1265static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; }
1271
1266
1272#define REG_A6XX_RBBM_PERFCTR_CP_5_HI 0x0000040b
1267static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; }
1273
1268
1274#define REG_A6XX_RBBM_PERFCTR_CP_6_LO 0x0000040c
1269static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; }
1275
1270
1276#define REG_A6XX_RBBM_PERFCTR_CP_6_HI 0x0000040d
1271static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; }
1277
1272
1278#define REG_A6XX_RBBM_PERFCTR_CP_7_LO 0x0000040e
1273static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; }
1279
1274
1280#define REG_A6XX_RBBM_PERFCTR_CP_7_HI 0x0000040f
1275static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; }
1281
1276
1282#define REG_A6XX_RBBM_PERFCTR_CP_8_LO 0x00000410
1283
1284#define REG_A6XX_RBBM_PERFCTR_CP_8_HI 0x00000411
1285
1286#define REG_A6XX_RBBM_PERFCTR_CP_9_LO 0x00000412
1287
1288#define REG_A6XX_RBBM_PERFCTR_CP_9_HI 0x00000413
1289
1290#define REG_A6XX_RBBM_PERFCTR_CP_10_LO 0x00000414
1291
1292#define REG_A6XX_RBBM_PERFCTR_CP_10_HI 0x00000415
1293
1294#define REG_A6XX_RBBM_PERFCTR_CP_11_LO 0x00000416
1295
1296#define REG_A6XX_RBBM_PERFCTR_CP_11_HI 0x00000417
1297
1298#define REG_A6XX_RBBM_PERFCTR_CP_12_LO 0x00000418
1299
1300#define REG_A6XX_RBBM_PERFCTR_CP_12_HI 0x00000419
1301
1302#define REG_A6XX_RBBM_PERFCTR_CP_13_LO 0x0000041a
1303
1304#define REG_A6XX_RBBM_PERFCTR_CP_13_HI 0x0000041b
1305
1306#define REG_A6XX_RBBM_PERFCTR_RBBM_0_LO 0x0000041c
1307
1308#define REG_A6XX_RBBM_PERFCTR_RBBM_0_HI 0x0000041d
1309
1310#define REG_A6XX_RBBM_PERFCTR_RBBM_1_LO 0x0000041e
1311
1312#define REG_A6XX_RBBM_PERFCTR_RBBM_1_HI 0x0000041f
1313
1314#define REG_A6XX_RBBM_PERFCTR_RBBM_2_LO 0x00000420
1315
1316#define REG_A6XX_RBBM_PERFCTR_RBBM_2_HI 0x00000421
1317
1318#define REG_A6XX_RBBM_PERFCTR_RBBM_3_LO 0x00000422
1319
1320#define REG_A6XX_RBBM_PERFCTR_RBBM_3_HI 0x00000423
1321
1322#define REG_A6XX_RBBM_PERFCTR_PC_0_LO 0x00000424
1323
1324#define REG_A6XX_RBBM_PERFCTR_PC_0_HI 0x00000425
1325
1326#define REG_A6XX_RBBM_PERFCTR_PC_1_LO 0x00000426
1327
1328#define REG_A6XX_RBBM_PERFCTR_PC_1_HI 0x00000427
1329
1330#define REG_A6XX_RBBM_PERFCTR_PC_2_LO 0x00000428
1331
1332#define REG_A6XX_RBBM_PERFCTR_PC_2_HI 0x00000429
1333
1334#define REG_A6XX_RBBM_PERFCTR_PC_3_LO 0x0000042a
1335
1336#define REG_A6XX_RBBM_PERFCTR_PC_3_HI 0x0000042b
1337
1338#define REG_A6XX_RBBM_PERFCTR_PC_4_LO 0x0000042c
1339
1340#define REG_A6XX_RBBM_PERFCTR_PC_4_HI 0x0000042d
1341
1342#define REG_A6XX_RBBM_PERFCTR_PC_5_LO 0x0000042e
1343
1344#define REG_A6XX_RBBM_PERFCTR_PC_5_HI 0x0000042f
1345
1346#define REG_A6XX_RBBM_PERFCTR_PC_6_LO 0x00000430
1347
1348#define REG_A6XX_RBBM_PERFCTR_PC_6_HI 0x00000431
1349
1350#define REG_A6XX_RBBM_PERFCTR_PC_7_LO 0x00000432
1351
1352#define REG_A6XX_RBBM_PERFCTR_PC_7_HI 0x00000433
1353
1354#define REG_A6XX_RBBM_PERFCTR_VFD_0_LO 0x00000434
1355
1356#define REG_A6XX_RBBM_PERFCTR_VFD_0_HI 0x00000435
1357
1358#define REG_A6XX_RBBM_PERFCTR_VFD_1_LO 0x00000436
1359
1360#define REG_A6XX_RBBM_PERFCTR_VFD_1_HI 0x00000437
1361
1362#define REG_A6XX_RBBM_PERFCTR_VFD_2_LO 0x00000438
1363
1364#define REG_A6XX_RBBM_PERFCTR_VFD_2_HI 0x00000439
1365
1366#define REG_A6XX_RBBM_PERFCTR_VFD_3_LO 0x0000043a
1367
1368#define REG_A6XX_RBBM_PERFCTR_VFD_3_HI 0x0000043b
1369
1370#define REG_A6XX_RBBM_PERFCTR_VFD_4_LO 0x0000043c
1371
1372#define REG_A6XX_RBBM_PERFCTR_VFD_4_HI 0x0000043d
1373
1374#define REG_A6XX_RBBM_PERFCTR_VFD_5_LO 0x0000043e
1375
1376#define REG_A6XX_RBBM_PERFCTR_VFD_5_HI 0x0000043f
1377
1378#define REG_A6XX_RBBM_PERFCTR_VFD_6_LO 0x00000440
1379
1380#define REG_A6XX_RBBM_PERFCTR_VFD_6_HI 0x00000441
1381
1382#define REG_A6XX_RBBM_PERFCTR_VFD_7_LO 0x00000442
1383
1384#define REG_A6XX_RBBM_PERFCTR_VFD_7_HI 0x00000443
1385
1386#define REG_A6XX_RBBM_PERFCTR_HLSQ_0_LO 0x00000444
1387
1388#define REG_A6XX_RBBM_PERFCTR_HLSQ_0_HI 0x00000445
1389
1390#define REG_A6XX_RBBM_PERFCTR_HLSQ_1_LO 0x00000446
1391
1392#define REG_A6XX_RBBM_PERFCTR_HLSQ_1_HI 0x00000447
1393
1394#define REG_A6XX_RBBM_PERFCTR_HLSQ_2_LO 0x00000448
1395
1396#define REG_A6XX_RBBM_PERFCTR_HLSQ_2_HI 0x00000449
1397
1398#define REG_A6XX_RBBM_PERFCTR_HLSQ_3_LO 0x0000044a
1399
1400#define REG_A6XX_RBBM_PERFCTR_HLSQ_3_HI 0x0000044b
1401
1402#define REG_A6XX_RBBM_PERFCTR_HLSQ_4_LO 0x0000044c
1403
1404#define REG_A6XX_RBBM_PERFCTR_HLSQ_4_HI 0x0000044d
1405
1406#define REG_A6XX_RBBM_PERFCTR_HLSQ_5_LO 0x0000044e
1407
1408#define REG_A6XX_RBBM_PERFCTR_HLSQ_5_HI 0x0000044f
1409
1410#define REG_A6XX_RBBM_PERFCTR_VPC_0_LO 0x00000450
1411
1412#define REG_A6XX_RBBM_PERFCTR_VPC_0_HI 0x00000451
1413
1414#define REG_A6XX_RBBM_PERFCTR_VPC_1_LO 0x00000452
1415
1416#define REG_A6XX_RBBM_PERFCTR_VPC_1_HI 0x00000453
1417
1418#define REG_A6XX_RBBM_PERFCTR_VPC_2_LO 0x00000454
1419
1420#define REG_A6XX_RBBM_PERFCTR_VPC_2_HI 0x00000455
1421
1422#define REG_A6XX_RBBM_PERFCTR_VPC_3_LO 0x00000456
1423
1424#define REG_A6XX_RBBM_PERFCTR_VPC_3_HI 0x00000457
1425
1426#define REG_A6XX_RBBM_PERFCTR_VPC_4_LO 0x00000458
1427
1428#define REG_A6XX_RBBM_PERFCTR_VPC_4_HI 0x00000459
1429
1430#define REG_A6XX_RBBM_PERFCTR_VPC_5_LO 0x0000045a
1431
1432#define REG_A6XX_RBBM_PERFCTR_VPC_5_HI 0x0000045b
1433
1434#define REG_A6XX_RBBM_PERFCTR_CCU_0_LO 0x0000045c
1435
1436#define REG_A6XX_RBBM_PERFCTR_CCU_0_HI 0x0000045d
1437
1438#define REG_A6XX_RBBM_PERFCTR_CCU_1_LO 0x0000045e
1439
1440#define REG_A6XX_RBBM_PERFCTR_CCU_1_HI 0x0000045f
1441
1442#define REG_A6XX_RBBM_PERFCTR_CCU_2_LO 0x00000460
1443
1444#define REG_A6XX_RBBM_PERFCTR_CCU_2_HI 0x00000461
1445
1446#define REG_A6XX_RBBM_PERFCTR_CCU_3_LO 0x00000462
1447
1448#define REG_A6XX_RBBM_PERFCTR_CCU_3_HI 0x00000463
1449
1450#define REG_A6XX_RBBM_PERFCTR_CCU_4_LO 0x00000464
1451
1452#define REG_A6XX_RBBM_PERFCTR_CCU_4_HI 0x00000465
1453
1454#define REG_A6XX_RBBM_PERFCTR_TSE_0_LO 0x00000466
1455
1456#define REG_A6XX_RBBM_PERFCTR_TSE_0_HI 0x00000467
1457
1458#define REG_A6XX_RBBM_PERFCTR_TSE_1_LO 0x00000468
1459
1460#define REG_A6XX_RBBM_PERFCTR_TSE_1_HI 0x00000469
1461
1462#define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a
1463
1464#define REG_A6XX_RBBM_PERFCTR_TSE_2_HI 0x0000046b
1465
1466#define REG_A6XX_RBBM_PERFCTR_TSE_3_LO 0x0000046c
1467
1468#define REG_A6XX_RBBM_PERFCTR_TSE_3_HI 0x0000046d
1469
1470#define REG_A6XX_RBBM_PERFCTR_RAS_0_LO 0x0000046e
1471
1472#define REG_A6XX_RBBM_PERFCTR_RAS_0_HI 0x0000046f
1473
1474#define REG_A6XX_RBBM_PERFCTR_RAS_1_LO 0x00000470
1475
1476#define REG_A6XX_RBBM_PERFCTR_RAS_1_HI 0x00000471
1477
1478#define REG_A6XX_RBBM_PERFCTR_RAS_2_LO 0x00000472
1479
1480#define REG_A6XX_RBBM_PERFCTR_RAS_2_HI 0x00000473
1481
1482#define REG_A6XX_RBBM_PERFCTR_RAS_3_LO 0x00000474
1483
1484#define REG_A6XX_RBBM_PERFCTR_RAS_3_HI 0x00000475
1485
1486#define REG_A6XX_RBBM_PERFCTR_UCHE_0_LO 0x00000476
1487
1488#define REG_A6XX_RBBM_PERFCTR_UCHE_0_HI 0x00000477
1489
1490#define REG_A6XX_RBBM_PERFCTR_UCHE_1_LO 0x00000478
1491
1492#define REG_A6XX_RBBM_PERFCTR_UCHE_1_HI 0x00000479
1493
1494#define REG_A6XX_RBBM_PERFCTR_UCHE_2_LO 0x0000047a
1495
1496#define REG_A6XX_RBBM_PERFCTR_UCHE_2_HI 0x0000047b
1497
1498#define REG_A6XX_RBBM_PERFCTR_UCHE_3_LO 0x0000047c
1499
1500#define REG_A6XX_RBBM_PERFCTR_UCHE_3_HI 0x0000047d
1501
1502#define REG_A6XX_RBBM_PERFCTR_UCHE_4_LO 0x0000047e
1503
1504#define REG_A6XX_RBBM_PERFCTR_UCHE_4_HI 0x0000047f
1505
1506#define REG_A6XX_RBBM_PERFCTR_UCHE_5_LO 0x00000480
1507
1508#define REG_A6XX_RBBM_PERFCTR_UCHE_5_HI 0x00000481
1509
1510#define REG_A6XX_RBBM_PERFCTR_UCHE_6_LO 0x00000482
1511
1512#define REG_A6XX_RBBM_PERFCTR_UCHE_6_HI 0x00000483
1513
1514#define REG_A6XX_RBBM_PERFCTR_UCHE_7_LO 0x00000484
1515
1516#define REG_A6XX_RBBM_PERFCTR_UCHE_7_HI 0x00000485
1517
1518#define REG_A6XX_RBBM_PERFCTR_UCHE_8_LO 0x00000486
1519
1520#define REG_A6XX_RBBM_PERFCTR_UCHE_8_HI 0x00000487
1521
1522#define REG_A6XX_RBBM_PERFCTR_UCHE_9_LO 0x00000488
1523
1524#define REG_A6XX_RBBM_PERFCTR_UCHE_9_HI 0x00000489
1525
1526#define REG_A6XX_RBBM_PERFCTR_UCHE_10_LO 0x0000048a
1527
1528#define REG_A6XX_RBBM_PERFCTR_UCHE_10_HI 0x0000048b
1529
1530#define REG_A6XX_RBBM_PERFCTR_UCHE_11_LO 0x0000048c
1531
1532#define REG_A6XX_RBBM_PERFCTR_UCHE_11_HI 0x0000048d
1533
1534#define REG_A6XX_RBBM_PERFCTR_TP_0_LO 0x0000048e
1535
1536#define REG_A6XX_RBBM_PERFCTR_TP_0_HI 0x0000048f
1537
1538#define REG_A6XX_RBBM_PERFCTR_TP_1_LO 0x00000490
1539
1540#define REG_A6XX_RBBM_PERFCTR_TP_1_HI 0x00000491
1541
1542#define REG_A6XX_RBBM_PERFCTR_TP_2_LO 0x00000492
1543
1544#define REG_A6XX_RBBM_PERFCTR_TP_2_HI 0x00000493
1545
1546#define REG_A6XX_RBBM_PERFCTR_TP_3_LO 0x00000494
1547
1548#define REG_A6XX_RBBM_PERFCTR_TP_3_HI 0x00000495
1549
1550#define REG_A6XX_RBBM_PERFCTR_TP_4_LO 0x00000496
1551
1552#define REG_A6XX_RBBM_PERFCTR_TP_4_HI 0x00000497
1553
1554#define REG_A6XX_RBBM_PERFCTR_TP_5_LO 0x00000498
1555
1556#define REG_A6XX_RBBM_PERFCTR_TP_5_HI 0x00000499
1557
1558#define REG_A6XX_RBBM_PERFCTR_TP_6_LO 0x0000049a
1559
1560#define REG_A6XX_RBBM_PERFCTR_TP_6_HI 0x0000049b
1561
1562#define REG_A6XX_RBBM_PERFCTR_TP_7_LO 0x0000049c
1563
1564#define REG_A6XX_RBBM_PERFCTR_TP_7_HI 0x0000049d
1565
1566#define REG_A6XX_RBBM_PERFCTR_TP_8_LO 0x0000049e
1567
1568#define REG_A6XX_RBBM_PERFCTR_TP_8_HI 0x0000049f
1569
1570#define REG_A6XX_RBBM_PERFCTR_TP_9_LO 0x000004a0
1571
1572#define REG_A6XX_RBBM_PERFCTR_TP_9_HI 0x000004a1
1573
1574#define REG_A6XX_RBBM_PERFCTR_TP_10_LO 0x000004a2
1575
1576#define REG_A6XX_RBBM_PERFCTR_TP_10_HI 0x000004a3
1577
1578#define REG_A6XX_RBBM_PERFCTR_TP_11_LO 0x000004a4
1579
1580#define REG_A6XX_RBBM_PERFCTR_TP_11_HI 0x000004a5
1581
1582#define REG_A6XX_RBBM_PERFCTR_SP_0_LO 0x000004a6
1583
1584#define REG_A6XX_RBBM_PERFCTR_SP_0_HI 0x000004a7
1585
1586#define REG_A6XX_RBBM_PERFCTR_SP_1_LO 0x000004a8
1587
1588#define REG_A6XX_RBBM_PERFCTR_SP_1_HI 0x000004a9
1589
1590#define REG_A6XX_RBBM_PERFCTR_SP_2_LO 0x000004aa
1591
1592#define REG_A6XX_RBBM_PERFCTR_SP_2_HI 0x000004ab
1593
1594#define REG_A6XX_RBBM_PERFCTR_SP_3_LO 0x000004ac
1595
1596#define REG_A6XX_RBBM_PERFCTR_SP_3_HI 0x000004ad
1597
1598#define REG_A6XX_RBBM_PERFCTR_SP_4_LO 0x000004ae
1599
1600#define REG_A6XX_RBBM_PERFCTR_SP_4_HI 0x000004af
1601
1602#define REG_A6XX_RBBM_PERFCTR_SP_5_LO 0x000004b0
1603
1604#define REG_A6XX_RBBM_PERFCTR_SP_5_HI 0x000004b1
1605
1606#define REG_A6XX_RBBM_PERFCTR_SP_6_LO 0x000004b2
1607
1608#define REG_A6XX_RBBM_PERFCTR_SP_6_HI 0x000004b3
1609
1610#define REG_A6XX_RBBM_PERFCTR_SP_7_LO 0x000004b4
1611
1612#define REG_A6XX_RBBM_PERFCTR_SP_7_HI 0x000004b5
1613
1614#define REG_A6XX_RBBM_PERFCTR_SP_8_LO 0x000004b6
1615
1616#define REG_A6XX_RBBM_PERFCTR_SP_8_HI 0x000004b7
1617
1618#define REG_A6XX_RBBM_PERFCTR_SP_9_LO 0x000004b8
1619
1620#define REG_A6XX_RBBM_PERFCTR_SP_9_HI 0x000004b9
1621
1622#define REG_A6XX_RBBM_PERFCTR_SP_10_LO 0x000004ba
1623
1624#define REG_A6XX_RBBM_PERFCTR_SP_10_HI 0x000004bb
1625
1626#define REG_A6XX_RBBM_PERFCTR_SP_11_LO 0x000004bc
1627
1628#define REG_A6XX_RBBM_PERFCTR_SP_11_HI 0x000004bd
1629
1630#define REG_A6XX_RBBM_PERFCTR_SP_12_LO 0x000004be
1631
1632#define REG_A6XX_RBBM_PERFCTR_SP_12_HI 0x000004bf
1633
1634#define REG_A6XX_RBBM_PERFCTR_SP_13_LO 0x000004c0
1635
1636#define REG_A6XX_RBBM_PERFCTR_SP_13_HI 0x000004c1
1637
1638#define REG_A6XX_RBBM_PERFCTR_SP_14_LO 0x000004c2
1639
1640#define REG_A6XX_RBBM_PERFCTR_SP_14_HI 0x000004c3
1641
1642#define REG_A6XX_RBBM_PERFCTR_SP_15_LO 0x000004c4
1643
1644#define REG_A6XX_RBBM_PERFCTR_SP_15_HI 0x000004c5
1645
1646#define REG_A6XX_RBBM_PERFCTR_SP_16_LO 0x000004c6
1647
1648#define REG_A6XX_RBBM_PERFCTR_SP_16_HI 0x000004c7
1649
1650#define REG_A6XX_RBBM_PERFCTR_SP_17_LO 0x000004c8
1651
1652#define REG_A6XX_RBBM_PERFCTR_SP_17_HI 0x000004c9
1653
1654#define REG_A6XX_RBBM_PERFCTR_SP_18_LO 0x000004ca
1655
1656#define REG_A6XX_RBBM_PERFCTR_SP_18_HI 0x000004cb
1657
1658#define REG_A6XX_RBBM_PERFCTR_SP_19_LO 0x000004cc
1659
1660#define REG_A6XX_RBBM_PERFCTR_SP_19_HI 0x000004cd
1661
1662#define REG_A6XX_RBBM_PERFCTR_SP_20_LO 0x000004ce
1663
1664#define REG_A6XX_RBBM_PERFCTR_SP_20_HI 0x000004cf
1665
1666#define REG_A6XX_RBBM_PERFCTR_SP_21_LO 0x000004d0
1667
1668#define REG_A6XX_RBBM_PERFCTR_SP_21_HI 0x000004d1
1669
1670#define REG_A6XX_RBBM_PERFCTR_SP_22_LO 0x000004d2
1671
1672#define REG_A6XX_RBBM_PERFCTR_SP_22_HI 0x000004d3
1673
1674#define REG_A6XX_RBBM_PERFCTR_SP_23_LO 0x000004d4
1675
1676#define REG_A6XX_RBBM_PERFCTR_SP_23_HI 0x000004d5
1677
1678#define REG_A6XX_RBBM_PERFCTR_RB_0_LO 0x000004d6
1679
1680#define REG_A6XX_RBBM_PERFCTR_RB_0_HI 0x000004d7
1681
1682#define REG_A6XX_RBBM_PERFCTR_RB_1_LO 0x000004d8
1683
1684#define REG_A6XX_RBBM_PERFCTR_RB_1_HI 0x000004d9
1685
1686#define REG_A6XX_RBBM_PERFCTR_RB_2_LO 0x000004da
1687
1688#define REG_A6XX_RBBM_PERFCTR_RB_2_HI 0x000004db
1689
1690#define REG_A6XX_RBBM_PERFCTR_RB_3_LO 0x000004dc
1691
1692#define REG_A6XX_RBBM_PERFCTR_RB_3_HI 0x000004dd
1693
1694#define REG_A6XX_RBBM_PERFCTR_RB_4_LO 0x000004de
1695
1696#define REG_A6XX_RBBM_PERFCTR_RB_4_HI 0x000004df
1697
1698#define REG_A6XX_RBBM_PERFCTR_RB_5_LO 0x000004e0
1699
1700#define REG_A6XX_RBBM_PERFCTR_RB_5_HI 0x000004e1
1701
1702#define REG_A6XX_RBBM_PERFCTR_RB_6_LO 0x000004e2
1703
1704#define REG_A6XX_RBBM_PERFCTR_RB_6_HI 0x000004e3
1705
1706#define REG_A6XX_RBBM_PERFCTR_RB_7_LO 0x000004e4
1707
1708#define REG_A6XX_RBBM_PERFCTR_RB_7_HI 0x000004e5
1709
1710#define REG_A6XX_RBBM_PERFCTR_VSC_0_LO 0x000004e6
1711
1712#define REG_A6XX_RBBM_PERFCTR_VSC_0_HI 0x000004e7
1713
1714#define REG_A6XX_RBBM_PERFCTR_VSC_1_LO 0x000004e8
1715
1716#define REG_A6XX_RBBM_PERFCTR_VSC_1_HI 0x000004e9
1717
1718#define REG_A6XX_RBBM_PERFCTR_LRZ_0_LO 0x000004ea
1719
1720#define REG_A6XX_RBBM_PERFCTR_LRZ_0_HI 0x000004eb
1721
1722#define REG_A6XX_RBBM_PERFCTR_LRZ_1_LO 0x000004ec
1723
1724#define REG_A6XX_RBBM_PERFCTR_LRZ_1_HI 0x000004ed
1725
1726#define REG_A6XX_RBBM_PERFCTR_LRZ_2_LO 0x000004ee
1727
1728#define REG_A6XX_RBBM_PERFCTR_LRZ_2_HI 0x000004ef
1729
1730#define REG_A6XX_RBBM_PERFCTR_LRZ_3_LO 0x000004f0
1731
1732#define REG_A6XX_RBBM_PERFCTR_LRZ_3_HI 0x000004f1
1733
1734#define REG_A6XX_RBBM_PERFCTR_CMP_0_LO 0x000004f2
1735
1736#define REG_A6XX_RBBM_PERFCTR_CMP_0_HI 0x000004f3
1737
1738#define REG_A6XX_RBBM_PERFCTR_CMP_1_LO 0x000004f4
1739
1740#define REG_A6XX_RBBM_PERFCTR_CMP_1_HI 0x000004f5
1741
1742#define REG_A6XX_RBBM_PERFCTR_CMP_2_LO 0x000004f6
1743
1744#define REG_A6XX_RBBM_PERFCTR_CMP_2_HI 0x000004f7
1745
1746#define REG_A6XX_RBBM_PERFCTR_CMP_3_LO 0x000004f8
1747
1748#define REG_A6XX_RBBM_PERFCTR_CMP_3_HI 0x000004f9
1749
1750#define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500
1751
1752#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501
1753
1754#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502
1755
1756#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503
1757
1758#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504
1759
1760#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505
1761
1762#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506
1763
1277#define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500
1278
1279#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501
1280
1281#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502
1282
1283#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503
1284
1285#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504
1286
1287#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505
1288
1289#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506
1290
1764#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000507
1291static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; }
1765
1292
1766#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000508
1767
1768#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000509
1769
1770#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000050a
1771
1772#define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b
1773
1774#define REG_A6XX_RBBM_ISDB_CNT 0x00000533
1775
1776#define REG_A6XX_RBBM_PRIMCTR_0_LO 0x00000540
1777
1778#define REG_A6XX_RBBM_PRIMCTR_0_HI 0x00000541
1779

--- 455 unchanged lines hidden (view full) ---

2235{
2236 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
2237}
2238
2239#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f
2240
2241#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630
2242
1293#define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b
1294
1295#define REG_A6XX_RBBM_ISDB_CNT 0x00000533
1296
1297#define REG_A6XX_RBBM_PRIMCTR_0_LO 0x00000540
1298
1299#define REG_A6XX_RBBM_PRIMCTR_0_HI 0x00000541
1300

--- 455 unchanged lines hidden (view full) ---

1756{
1757 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
1758}
1759
1760#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f
1761
1762#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630
1763
2243#define REG_A6XX_VSC_PERFCTR_VSC_SEL_0 0x00000cd8
1764static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; }
2244
1765
2245#define REG_A6XX_VSC_PERFCTR_VSC_SEL_1 0x00000cd9
2246
2247#define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05
2248
2249#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x0000be10
2250
2251#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x0000be11
2252
2253#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x0000be12
2254
2255#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x0000be13
2256
2257#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x0000be14
2258
2259#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x0000be15
2260
2261#define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800
2262
2263#define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000
2264
1766#define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800
1767
1768#define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000
1769
2265#define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601
2266
2267#define REG_A6XX_VFD_PERFCTR_VFD_SEL_0 0x0000a610
2268
2269#define REG_A6XX_VFD_PERFCTR_VFD_SEL_1 0x0000a611
2270
2271#define REG_A6XX_VFD_PERFCTR_VFD_SEL_2 0x0000a612
2272
2273#define REG_A6XX_VFD_PERFCTR_VFD_SEL_3 0x0000a613
2274
2275#define REG_A6XX_VFD_PERFCTR_VFD_SEL_4 0x0000a614
2276
2277#define REG_A6XX_VFD_PERFCTR_VFD_SEL_5 0x0000a615
2278
2279#define REG_A6XX_VFD_PERFCTR_VFD_SEL_6 0x0000a616
2280
2281#define REG_A6XX_VFD_PERFCTR_VFD_SEL_7 0x0000a617
2282
2283#define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00
2284
2285#define REG_A6XX_UCHE_MODE_CNTL 0x00000e01
2286
2287#define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05
2288
2289#define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06
2290

--- 20 unchanged lines hidden (view full) ---

2311#define REG_A6XX_UCHE_CLIENT_PF 0x00000e19
2312#define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff
2313#define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0
2314static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
2315{
2316 return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK;
2317}
2318
1770#define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00
1771
1772#define REG_A6XX_UCHE_MODE_CNTL 0x00000e01
1773
1774#define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05
1775
1776#define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06
1777

--- 20 unchanged lines hidden (view full) ---

1798#define REG_A6XX_UCHE_CLIENT_PF 0x00000e19
1799#define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff
1800#define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0
1801static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
1802{
1803 return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK;
1804}
1805
2319#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e1c
1806static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; }
2320
1807
2321#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e1d
1808#define REG_A6XX_UCHE_CMDQ_CONFIG 0x00000e3c
2322
1809
2323#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e1e
2324
2325#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e1f
2326
2327#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e20
2328
2329#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e21
2330
2331#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e22
2332
2333#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e23
2334
2335#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_8 0x00000e24
2336
2337#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_9 0x00000e25
2338
2339#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_10 0x00000e26
2340
2341#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_11 0x00000e27
2342
2343#define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01
2344
2345#define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02
2346
2347#define REG_A6XX_SP_PERFCTR_SP_SEL_0 0x0000ae10
2348
2349#define REG_A6XX_SP_PERFCTR_SP_SEL_1 0x0000ae11
2350
2351#define REG_A6XX_SP_PERFCTR_SP_SEL_2 0x0000ae12
2352
2353#define REG_A6XX_SP_PERFCTR_SP_SEL_3 0x0000ae13
2354
2355#define REG_A6XX_SP_PERFCTR_SP_SEL_4 0x0000ae14
2356
2357#define REG_A6XX_SP_PERFCTR_SP_SEL_5 0x0000ae15
2358
2359#define REG_A6XX_SP_PERFCTR_SP_SEL_6 0x0000ae16
2360
2361#define REG_A6XX_SP_PERFCTR_SP_SEL_7 0x0000ae17
2362
2363#define REG_A6XX_SP_PERFCTR_SP_SEL_8 0x0000ae18
2364
2365#define REG_A6XX_SP_PERFCTR_SP_SEL_9 0x0000ae19
2366
2367#define REG_A6XX_SP_PERFCTR_SP_SEL_10 0x0000ae1a
2368
2369#define REG_A6XX_SP_PERFCTR_SP_SEL_11 0x0000ae1b
2370
2371#define REG_A6XX_SP_PERFCTR_SP_SEL_12 0x0000ae1c
2372
2373#define REG_A6XX_SP_PERFCTR_SP_SEL_13 0x0000ae1d
2374
2375#define REG_A6XX_SP_PERFCTR_SP_SEL_14 0x0000ae1e
2376
2377#define REG_A6XX_SP_PERFCTR_SP_SEL_15 0x0000ae1f
2378
2379#define REG_A6XX_SP_PERFCTR_SP_SEL_16 0x0000ae20
2380
2381#define REG_A6XX_SP_PERFCTR_SP_SEL_17 0x0000ae21
2382
2383#define REG_A6XX_SP_PERFCTR_SP_SEL_18 0x0000ae22
2384
2385#define REG_A6XX_SP_PERFCTR_SP_SEL_19 0x0000ae23
2386
2387#define REG_A6XX_SP_PERFCTR_SP_SEL_20 0x0000ae24
2388
2389#define REG_A6XX_SP_PERFCTR_SP_SEL_21 0x0000ae25
2390
2391#define REG_A6XX_SP_PERFCTR_SP_SEL_22 0x0000ae26
2392
2393#define REG_A6XX_SP_PERFCTR_SP_SEL_23 0x0000ae27
2394
2395#define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601
2396
2397#define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604
2398
2399#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608
2400
2401#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609
2402
2403#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a
2404
2405#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b
2406
2407#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c
2408
2409#define REG_A6XX_TPL1_PERFCTR_TP_SEL_0 0x0000b610
2410
2411#define REG_A6XX_TPL1_PERFCTR_TP_SEL_1 0x0000b611
2412
2413#define REG_A6XX_TPL1_PERFCTR_TP_SEL_2 0x0000b612
2414
2415#define REG_A6XX_TPL1_PERFCTR_TP_SEL_3 0x0000b613
2416
2417#define REG_A6XX_TPL1_PERFCTR_TP_SEL_4 0x0000b614
2418
2419#define REG_A6XX_TPL1_PERFCTR_TP_SEL_5 0x0000b615
2420
2421#define REG_A6XX_TPL1_PERFCTR_TP_SEL_6 0x0000b616
2422
2423#define REG_A6XX_TPL1_PERFCTR_TP_SEL_7 0x0000b617
2424
2425#define REG_A6XX_TPL1_PERFCTR_TP_SEL_8 0x0000b618
2426
2427#define REG_A6XX_TPL1_PERFCTR_TP_SEL_9 0x0000b619
2428
2429#define REG_A6XX_TPL1_PERFCTR_TP_SEL_10 0x0000b61a
2430
2431#define REG_A6XX_TPL1_PERFCTR_TP_SEL_11 0x0000b61b
2432
2433#define REG_A6XX_VBIF_VERSION 0x00003000
2434
2435#define REG_A6XX_VBIF_CLKON 0x00003001
2436#define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002
2437
2438#define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
2439
2440#define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080

--- 61 unchanged lines hidden (view full) ---

2502#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
2503
2504#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
2505
2506#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
2507
2508#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
2509
1810#define REG_A6XX_VBIF_VERSION 0x00003000
1811
1812#define REG_A6XX_VBIF_CLKON 0x00003001
1813#define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002
1814
1815#define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
1816
1817#define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080

--- 61 unchanged lines hidden (view full) ---

1879#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
1880
1881#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
1882
1883#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
1884
1885#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
1886
1887#define REG_A6XX_GBIF_SCACHE_CNTL0 0x00003c01
1888
2510#define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02
2511
2512#define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03
2513
2514#define REG_A6XX_GBIF_QSB_SIDE1 0x00003c04
2515
2516#define REG_A6XX_GBIF_QSB_SIDE2 0x00003c05
2517

--- 32 unchanged lines hidden (view full) ---

2550#define REG_A6XX_GBIF_PWR_CNT_LOW2 0x00003cce
2551
2552#define REG_A6XX_GBIF_PWR_CNT_HIGH0 0x00003ccf
2553
2554#define REG_A6XX_GBIF_PWR_CNT_HIGH1 0x00003cd0
2555
2556#define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1
2557
1889#define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02
1890
1891#define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03
1892
1893#define REG_A6XX_GBIF_QSB_SIDE1 0x00003c04
1894
1895#define REG_A6XX_GBIF_QSB_SIDE2 0x00003c05
1896

--- 32 unchanged lines hidden (view full) ---

1929#define REG_A6XX_GBIF_PWR_CNT_LOW2 0x00003cce
1930
1931#define REG_A6XX_GBIF_PWR_CNT_HIGH0 0x00003ccf
1932
1933#define REG_A6XX_GBIF_PWR_CNT_HIGH1 0x00003cd0
1934
1935#define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1
1936
2558#define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1
2559#define A6XX_SP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
2560#define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00007fff
2561#define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0
2562static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
2563{
2564 return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK;
2565}
2566#define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x7fff0000
2567#define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16
2568static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
2569{
2570 return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
2571}
2572
2573#define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307
2574#define A6XX_SP_TP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
2575#define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00007fff
2576#define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0
2577static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
2578{
2579 return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK;
2580}
2581#define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x7fff0000
2582#define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16
2583static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
2584{
2585 return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
2586}
2587
2588#define REG_A6XX_VSC_BIN_SIZE 0x00000c02
2589#define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
2590#define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
2591static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
2592{
2593 return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK;
2594}
2595#define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00
2596#define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8
2597static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
2598{
2599 return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
2600}
2601
1937#define REG_A6XX_VSC_BIN_SIZE 0x00000c02
1938#define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
1939#define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
1940static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
1941{
1942 return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK;
1943}
1944#define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00
1945#define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8
1946static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
1947{
1948 return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
1949}
1950
2602#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_LO 0x00000c03
2603
2604#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_HI 0x00000c04
2605
2606#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03
2607
2608#define REG_A6XX_VSC_BIN_COUNT 0x00000c06
2609#define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe
2610#define A6XX_VSC_BIN_COUNT_NX__SHIFT 1
2611static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val)
2612{
2613 return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK;

--- 28 unchanged lines hidden (view full) ---

2642}
2643#define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000
2644#define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26
2645static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
2646{
2647 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;
2648}
2649
1951#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03
1952
1953#define REG_A6XX_VSC_BIN_COUNT 0x00000c06
1954#define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe
1955#define A6XX_VSC_BIN_COUNT_NX__SHIFT 1
1956static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val)
1957{
1958 return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK;

--- 28 unchanged lines hidden (view full) ---

1987}
1988#define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000
1989#define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26
1990static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
1991{
1992 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;
1993}
1994
2650#define REG_A6XX_VSC_PRIM_STRM_ADDRESS_LO 0x00000c30
2651
2652#define REG_A6XX_VSC_PRIM_STRM_ADDRESS_HI 0x00000c31
2653
2654#define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30
2655
2656#define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32
2657
2658#define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33
2659
1995#define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30
1996
1997#define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32
1998
1999#define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33
2000
2660#define REG_A6XX_VSC_DRAW_STRM_ADDRESS_LO 0x00000c34
2661
2662#define REG_A6XX_VSC_DRAW_STRM_ADDRESS_HI 0x00000c35
2663
2664#define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34
2665
2666#define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36
2667
2668#define REG_A6XX_VSC_DRAW_STRM_LIMIT 0x00000c37
2669
2670static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
2671

--- 172 unchanged lines hidden (view full) ---

2844#define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
2845#define A6XX_GRAS_SU_CNTL_UNK12__MASK 0x00001000
2846#define A6XX_GRAS_SU_CNTL_UNK12__SHIFT 12
2847static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val)
2848{
2849 return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK;
2850}
2851#define A6XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
2001#define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34
2002
2003#define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36
2004
2005#define REG_A6XX_VSC_DRAW_STRM_LIMIT 0x00000c37
2006
2007static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
2008

--- 172 unchanged lines hidden (view full) ---

2181#define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
2182#define A6XX_GRAS_SU_CNTL_UNK12__MASK 0x00001000
2183#define A6XX_GRAS_SU_CNTL_UNK12__SHIFT 12
2184static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val)
2185{
2186 return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK;
2187}
2188#define A6XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
2852#define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x007f8000
2189#define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x00018000
2853#define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15
2854static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val)
2855{
2856 return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK;
2857}
2190#define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15
2191static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val)
2192{
2193 return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK;
2194}
2195#define A6XX_GRAS_SU_CNTL_UNK17 0x00020000
2196#define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00040000
2197#define A6XX_GRAS_SU_CNTL_UNK19__MASK 0x00780000
2198#define A6XX_GRAS_SU_CNTL_UNK19__SHIFT 19
2199static inline uint32_t A6XX_GRAS_SU_CNTL_UNK19(uint32_t val)
2200{
2201 return ((val) << A6XX_GRAS_SU_CNTL_UNK19__SHIFT) & A6XX_GRAS_SU_CNTL_UNK19__MASK;
2202}
2858
2859#define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091
2860#define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
2861#define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
2862static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2863{
2864 return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2865}

--- 334 unchanged lines hidden (view full) ---

3200}
3201
3202#define REG_A6XX_GRAS_LRZ_CNTL 0x00008100
3203#define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
3204#define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
3205#define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004
3206#define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008
3207#define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010
2203
2204#define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091
2205#define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
2206#define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
2207static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2208{
2209 return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2210}

--- 334 unchanged lines hidden (view full) ---

2545}
2546
2547#define REG_A6XX_GRAS_LRZ_CNTL 0x00008100
2548#define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
2549#define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
2550#define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004
2551#define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008
2552#define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010
3208#define A6XX_GRAS_LRZ_CNTL_UNK5__MASK 0x000003e0
3209#define A6XX_GRAS_LRZ_CNTL_UNK5__SHIFT 5
3210static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK5(uint32_t val)
2553#define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE 0x00000020
2554#define A6XX_GRAS_LRZ_CNTL_UNK6__MASK 0x000003c0
2555#define A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT 6
2556static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK6(uint32_t val)
3211{
2557{
3212 return ((val) << A6XX_GRAS_LRZ_CNTL_UNK5__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK5__MASK;
2558 return ((val) << A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK6__MASK;
3213}
3214
3215#define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101
3216
3217#define REG_A6XX_GRAS_2D_BLIT_INFO 0x00008102
3218#define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK 0x000000ff
3219#define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT 0
3220static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_format val)
3221{
3222 return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK;
3223}
3224
2559}
2560
2561#define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101
2562
2563#define REG_A6XX_GRAS_2D_BLIT_INFO 0x00008102
2564#define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK 0x000000ff
2565#define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT 0
2566static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_format val)
2567{
2568 return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK;
2569}
2570
3225#define REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO 0x00008103
3226
3227#define REG_A6XX_GRAS_LRZ_BUFFER_BASE_HI 0x00008104
3228
3229#define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103
3230#define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff
3231#define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT 0
3232static inline uint32_t A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val)
3233{
3234 return ((val) << A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_BUFFER_BASE__MASK;
3235}
3236

--- 6 unchanged lines hidden (view full) ---

3243}
3244#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffffc00
3245#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 10
3246static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
3247{
3248 return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
3249}
3250
2571#define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103
2572#define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff
2573#define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT 0
2574static inline uint32_t A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val)
2575{
2576 return ((val) << A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_BUFFER_BASE__MASK;
2577}
2578

--- 6 unchanged lines hidden (view full) ---

2585}
2586#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffffc00
2587#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 10
2588static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
2589{
2590 return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
2591}
2592
3251#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x00008106
3252
3253#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x00008107
3254
3255#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106
3256#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff
3257#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT 0
3258static inline uint32_t A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val)
3259{
3260 return ((val) << A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK;
3261}
3262

--- 138 unchanged lines hidden (view full) ---

3401{
3402 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK;
3403}
3404
3405#define REG_A6XX_GRAS_UNKNOWN_8600 0x00008600
3406
3407#define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601
3408
2593#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106
2594#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff
2595#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT 0
2596static inline uint32_t A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val)
2597{
2598 return ((val) << A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK;
2599}
2600

--- 138 unchanged lines hidden (view full) ---

2739{
2740 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK;
2741}
2742
2743#define REG_A6XX_GRAS_UNKNOWN_8600 0x00008600
2744
2745#define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601
2746
3409#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_0 0x00008610
2747static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; }
3410
2748
3411#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_1 0x00008611
2749static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; }
3412
2750
3413#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_2 0x00008612
2751static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; }
3414
2752
3415#define REG_A6XX_GRAS_PERFCTR_TSE_SEL_3 0x00008613
3416
3417#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_0 0x00008614
3418
3419#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_1 0x00008615
3420
3421#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_2 0x00008616
3422
3423#define REG_A6XX_GRAS_PERFCTR_RAS_SEL_3 0x00008617
3424
3425#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_0 0x00008618
3426
3427#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_1 0x00008619
3428
3429#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_2 0x0000861a
3430
3431#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_3 0x0000861b
3432
3433#define REG_A6XX_RB_BIN_CONTROL 0x00008800
3434#define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f
3435#define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0
3436static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val)
3437{
3438 return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK;
3439}
3440#define A6XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00

--- 443 unchanged lines hidden (view full) ---

3884static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; }
3885#define A6XX_RB_MRT_ARRAY_PITCH__MASK 0x1fffffff
3886#define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0
3887static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val)
3888{
3889 return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK;
3890}
3891
2753#define REG_A6XX_RB_BIN_CONTROL 0x00008800
2754#define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f
2755#define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0
2756static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val)
2757{
2758 return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK;
2759}
2760#define A6XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00

--- 443 unchanged lines hidden (view full) ---

3204static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; }
3205#define A6XX_RB_MRT_ARRAY_PITCH__MASK 0x1fffffff
3206#define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0
3207static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val)
3208{
3209 return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK;
3210}
3211
3892static inline uint32_t REG_A6XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x00008825 + 0x8*i0; }
3893
3894static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; }
3895
3896static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; }
3897#define A6XX_RB_MRT_BASE__MASK 0xffffffff
3898#define A6XX_RB_MRT_BASE__SHIFT 0
3899static inline uint32_t A6XX_RB_MRT_BASE(uint32_t val)
3900{
3901 return ((val) << A6XX_RB_MRT_BASE__SHIFT) & A6XX_RB_MRT_BASE__MASK;
3902}
3903

--- 116 unchanged lines hidden (view full) ---

4020#define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874
4021#define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0x0fffffff
4022#define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
4023static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
4024{
4025 return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
4026}
4027
3212static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; }
3213#define A6XX_RB_MRT_BASE__MASK 0xffffffff
3214#define A6XX_RB_MRT_BASE__SHIFT 0
3215static inline uint32_t A6XX_RB_MRT_BASE(uint32_t val)
3216{
3217 return ((val) << A6XX_RB_MRT_BASE__SHIFT) & A6XX_RB_MRT_BASE__MASK;
3218}
3219

--- 116 unchanged lines hidden (view full) ---

3336#define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874
3337#define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0x0fffffff
3338#define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
3339static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
3340{
3341 return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
3342}
3343
4028#define REG_A6XX_RB_DEPTH_BUFFER_BASE_LO 0x00008875
4029
4030#define REG_A6XX_RB_DEPTH_BUFFER_BASE_HI 0x00008876
4031
4032#define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875
4033#define A6XX_RB_DEPTH_BUFFER_BASE__MASK 0xffffffff
4034#define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT 0
4035static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val)
4036{
4037 return ((val) << A6XX_RB_DEPTH_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE__MASK;
4038}
4039

--- 89 unchanged lines hidden (view full) ---

4129#define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883
4130#define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0x00ffffff
4131#define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0
4132static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val)
4133{
4134 return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK;
4135}
4136
3344#define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875
3345#define A6XX_RB_DEPTH_BUFFER_BASE__MASK 0xffffffff
3346#define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT 0
3347static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val)
3348{
3349 return ((val) << A6XX_RB_DEPTH_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE__MASK;
3350}
3351

--- 89 unchanged lines hidden (view full) ---

3441#define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883
3442#define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0x00ffffff
3443#define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0
3444static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val)
3445{
3446 return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK;
3447}
3448
4137#define REG_A6XX_RB_STENCIL_BUFFER_BASE_LO 0x00008884
4138
4139#define REG_A6XX_RB_STENCIL_BUFFER_BASE_HI 0x00008885
4140
4141#define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884
4142#define A6XX_RB_STENCIL_BUFFER_BASE__MASK 0xffffffff
4143#define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT 0
4144static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val)
4145{
4146 return ((val) << A6XX_RB_STENCIL_BUFFER_BASE__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE__MASK;
4147}
4148

--- 201 unchanged lines hidden (view full) ---

4350#define REG_A6XX_RB_BLIT_DST 0x000088d8
4351#define A6XX_RB_BLIT_DST__MASK 0xffffffff
4352#define A6XX_RB_BLIT_DST__SHIFT 0
4353static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val)
4354{
4355 return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK;
4356}
4357
3449#define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884
3450#define A6XX_RB_STENCIL_BUFFER_BASE__MASK 0xffffffff
3451#define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT 0
3452static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val)
3453{
3454 return ((val) << A6XX_RB_STENCIL_BUFFER_BASE__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE__MASK;
3455}
3456

--- 201 unchanged lines hidden (view full) ---

3658#define REG_A6XX_RB_BLIT_DST 0x000088d8
3659#define A6XX_RB_BLIT_DST__MASK 0xffffffff
3660#define A6XX_RB_BLIT_DST__SHIFT 0
3661static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val)
3662{
3663 return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK;
3664}
3665
4358#define REG_A6XX_RB_BLIT_DST_LO 0x000088d8
4359
4360#define REG_A6XX_RB_BLIT_DST_HI 0x000088d9
4361
4362#define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da
4363#define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff
4364#define A6XX_RB_BLIT_DST_PITCH__SHIFT 0
4365static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val)
4366{
4367 return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK;
4368}
4369

--- 8 unchanged lines hidden (view full) ---

4378#define REG_A6XX_RB_BLIT_FLAG_DST 0x000088dc
4379#define A6XX_RB_BLIT_FLAG_DST__MASK 0xffffffff
4380#define A6XX_RB_BLIT_FLAG_DST__SHIFT 0
4381static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val)
4382{
4383 return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK;
4384}
4385
3666#define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da
3667#define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff
3668#define A6XX_RB_BLIT_DST_PITCH__SHIFT 0
3669static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val)
3670{
3671 return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK;
3672}
3673

--- 8 unchanged lines hidden (view full) ---

3682#define REG_A6XX_RB_BLIT_FLAG_DST 0x000088dc
3683#define A6XX_RB_BLIT_FLAG_DST__MASK 0xffffffff
3684#define A6XX_RB_BLIT_FLAG_DST__SHIFT 0
3685static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val)
3686{
3687 return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK;
3688}
3689
4386#define REG_A6XX_RB_BLIT_FLAG_DST_LO 0x000088dc
4387
4388#define REG_A6XX_RB_BLIT_FLAG_DST_HI 0x000088dd
4389
4390#define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de
4391#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff
4392#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0
4393static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val)
4394{
4395 return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK;
4396}
4397#define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x0ffff800

--- 9 unchanged lines hidden (view full) ---

4407
4408#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1
4409
4410#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2
4411
4412#define REG_A6XX_RB_BLIT_INFO 0x000088e3
4413#define A6XX_RB_BLIT_INFO_UNK0 0x00000001
4414#define A6XX_RB_BLIT_INFO_GMEM 0x00000002
3690#define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de
3691#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff
3692#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0
3693static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val)
3694{
3695 return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK;
3696}
3697#define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x0ffff800

--- 9 unchanged lines hidden (view full) ---

3707
3708#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1
3709
3710#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2
3711
3712#define REG_A6XX_RB_BLIT_INFO 0x000088e3
3713#define A6XX_RB_BLIT_INFO_UNK0 0x00000001
3714#define A6XX_RB_BLIT_INFO_GMEM 0x00000002
4415#define A6XX_RB_BLIT_INFO_INTEGER 0x00000004
3715#define A6XX_RB_BLIT_INFO_SAMPLE_0 0x00000004
4416#define A6XX_RB_BLIT_INFO_DEPTH 0x00000008
4417#define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0
4418#define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4
4419static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val)
4420{
4421 return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK;
4422}
4423#define A6XX_RB_BLIT_INFO_UNK8__MASK 0x00000300

--- 30 unchanged lines hidden (view full) ---

4454#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
4455static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
4456{
4457 return ((val >> 7) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
4458}
4459
4460#define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4
4461
3716#define A6XX_RB_BLIT_INFO_DEPTH 0x00000008
3717#define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0
3718#define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4
3719static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val)
3720{
3721 return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK;
3722}
3723#define A6XX_RB_BLIT_INFO_UNK8__MASK 0x00000300

--- 30 unchanged lines hidden (view full) ---

3754#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
3755static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
3756{
3757 return ((val >> 7) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
3758}
3759
3760#define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4
3761
4462#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x00008900
4463
4464#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x00008901
4465
4466#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900
4467#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK 0xffffffff
4468#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT 0
4469static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val)
4470{
4471 return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK;
4472}
4473

--- 14 unchanged lines hidden (view full) ---

4488#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
4489static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
4490{
4491 return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
4492}
4493
4494static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }
4495
3762#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900
3763#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK 0xffffffff
3764#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT 0
3765static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val)
3766{
3767 return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK;
3768}
3769

--- 14 unchanged lines hidden (view full) ---

3784#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
3785static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
3786{
3787 return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
3788}
3789
3790static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }
3791
4496static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x00008903 + 0x3*i0; }
4497
4498static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i0; }
4499
4500static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; }
4501#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK 0xffffffff
4502#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT 0
4503static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val)
4504{
4505 return ((val) << A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK;
4506}
4507

--- 6 unchanged lines hidden (view full) ---

4514}
4515#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffff800
4516#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
4517static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
4518{
4519 return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
4520}
4521
3792static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; }
3793#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK 0xffffffff
3794#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT 0
3795static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val)
3796{
3797 return ((val) << A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK;
3798}
3799

--- 6 unchanged lines hidden (view full) ---

3806}
3807#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffff800
3808#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
3809static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
3810{
3811 return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
3812}
3813
4522#define REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO 0x00008927
4523
4524#define REG_A6XX_RB_SAMPLE_COUNT_ADDR_HI 0x00008928
4525
4526#define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927
4527#define A6XX_RB_SAMPLE_COUNT_ADDR__MASK 0xffffffff
4528#define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT 0
4529static inline uint32_t A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val)
4530{
4531 return ((val) << A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT) & A6XX_RB_SAMPLE_COUNT_ADDR__MASK;
4532}
4533

--- 69 unchanged lines hidden (view full) ---

4603#define A6XX_RB_2D_DST_INFO_SRGB 0x00002000
4604#define A6XX_RB_2D_DST_INFO_SAMPLES__MASK 0x0000c000
4605#define A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT 14
4606static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
4607{
4608 return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK;
4609}
4610#define A6XX_RB_2D_DST_INFO_FILTER 0x00010000
3814#define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927
3815#define A6XX_RB_SAMPLE_COUNT_ADDR__MASK 0xffffffff
3816#define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT 0
3817static inline uint32_t A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val)
3818{
3819 return ((val) << A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT) & A6XX_RB_SAMPLE_COUNT_ADDR__MASK;
3820}
3821

--- 69 unchanged lines hidden (view full) ---

3891#define A6XX_RB_2D_DST_INFO_SRGB 0x00002000
3892#define A6XX_RB_2D_DST_INFO_SAMPLES__MASK 0x0000c000
3893#define A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT 14
3894static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
3895{
3896 return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK;
3897}
3898#define A6XX_RB_2D_DST_INFO_FILTER 0x00010000
3899#define A6XX_RB_2D_DST_INFO_UNK17 0x00020000
4611#define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000
3900#define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000
3901#define A6XX_RB_2D_DST_INFO_UNK19 0x00080000
4612#define A6XX_RB_2D_DST_INFO_UNK20 0x00100000
3902#define A6XX_RB_2D_DST_INFO_UNK20 0x00100000
3903#define A6XX_RB_2D_DST_INFO_UNK21 0x00200000
4613#define A6XX_RB_2D_DST_INFO_UNK22 0x00400000
3904#define A6XX_RB_2D_DST_INFO_UNK22 0x00400000
3905#define A6XX_RB_2D_DST_INFO_UNK23__MASK 0x07800000
3906#define A6XX_RB_2D_DST_INFO_UNK23__SHIFT 23
3907static inline uint32_t A6XX_RB_2D_DST_INFO_UNK23(uint32_t val)
3908{
3909 return ((val) << A6XX_RB_2D_DST_INFO_UNK23__SHIFT) & A6XX_RB_2D_DST_INFO_UNK23__MASK;
3910}
3911#define A6XX_RB_2D_DST_INFO_UNK28 0x10000000
4614
3912
4615#define REG_A6XX_RB_2D_DST_LO 0x00008c18
4616
4617#define REG_A6XX_RB_2D_DST_HI 0x00008c19
4618
4619#define REG_A6XX_RB_2D_DST 0x00008c18
4620#define A6XX_RB_2D_DST__MASK 0xffffffff
4621#define A6XX_RB_2D_DST__SHIFT 0
4622static inline uint32_t A6XX_RB_2D_DST(uint32_t val)
4623{
4624 return ((val) << A6XX_RB_2D_DST__SHIFT) & A6XX_RB_2D_DST__MASK;
4625}
4626

--- 24 unchanged lines hidden (view full) ---

4651#define REG_A6XX_RB_2D_DST_PLANE2 0x00008c1e
4652#define A6XX_RB_2D_DST_PLANE2__MASK 0xffffffff
4653#define A6XX_RB_2D_DST_PLANE2__SHIFT 0
4654static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val)
4655{
4656 return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK;
4657}
4658
3913#define REG_A6XX_RB_2D_DST 0x00008c18
3914#define A6XX_RB_2D_DST__MASK 0xffffffff
3915#define A6XX_RB_2D_DST__SHIFT 0
3916static inline uint32_t A6XX_RB_2D_DST(uint32_t val)
3917{
3918 return ((val) << A6XX_RB_2D_DST__SHIFT) & A6XX_RB_2D_DST__MASK;
3919}
3920

--- 24 unchanged lines hidden (view full) ---

3945#define REG_A6XX_RB_2D_DST_PLANE2 0x00008c1e
3946#define A6XX_RB_2D_DST_PLANE2__MASK 0xffffffff
3947#define A6XX_RB_2D_DST_PLANE2__SHIFT 0
3948static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val)
3949{
3950 return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK;
3951}
3952
4659#define REG_A6XX_RB_2D_DST_FLAGS_LO 0x00008c20
4660
4661#define REG_A6XX_RB_2D_DST_FLAGS_HI 0x00008c21
4662
4663#define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20
4664#define A6XX_RB_2D_DST_FLAGS__MASK 0xffffffff
4665#define A6XX_RB_2D_DST_FLAGS__SHIFT 0
4666static inline uint32_t A6XX_RB_2D_DST_FLAGS(uint32_t val)
4667{
4668 return ((val) << A6XX_RB_2D_DST_FLAGS__SHIFT) & A6XX_RB_2D_DST_FLAGS__MASK;
4669}
4670

--- 64 unchanged lines hidden (view full) ---

4735#define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR 0x00000800
4736#define A6XX_RB_NC_MODE_CNTL_UNK12__MASK 0x00003000
4737#define A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT 12
4738static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val)
4739{
4740 return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK;
4741}
4742
3953#define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20
3954#define A6XX_RB_2D_DST_FLAGS__MASK 0xffffffff
3955#define A6XX_RB_2D_DST_FLAGS__SHIFT 0
3956static inline uint32_t A6XX_RB_2D_DST_FLAGS(uint32_t val)
3957{
3958 return ((val) << A6XX_RB_2D_DST_FLAGS__SHIFT) & A6XX_RB_2D_DST_FLAGS__MASK;
3959}
3960

--- 64 unchanged lines hidden (view full) ---

4025#define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR 0x00000800
4026#define A6XX_RB_NC_MODE_CNTL_UNK12__MASK 0x00003000
4027#define A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT 12
4028static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val)
4029{
4030 return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK;
4031}
4032
4743#define REG_A6XX_RB_PERFCTR_RB_SEL_0 0x00008e10
4033static inline uint32_t REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) { return 0x00008e10 + 0x1*i0; }
4744
4034
4745#define REG_A6XX_RB_PERFCTR_RB_SEL_1 0x00008e11
4035static inline uint32_t REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) { return 0x00008e18 + 0x1*i0; }
4746
4036
4747#define REG_A6XX_RB_PERFCTR_RB_SEL_2 0x00008e12
4748
4749#define REG_A6XX_RB_PERFCTR_RB_SEL_3 0x00008e13
4750
4751#define REG_A6XX_RB_PERFCTR_RB_SEL_4 0x00008e14
4752
4753#define REG_A6XX_RB_PERFCTR_RB_SEL_5 0x00008e15
4754
4755#define REG_A6XX_RB_PERFCTR_RB_SEL_6 0x00008e16
4756
4757#define REG_A6XX_RB_PERFCTR_RB_SEL_7 0x00008e17
4758
4759#define REG_A6XX_RB_PERFCTR_CCU_SEL_0 0x00008e18
4760
4761#define REG_A6XX_RB_PERFCTR_CCU_SEL_1 0x00008e19
4762
4763#define REG_A6XX_RB_PERFCTR_CCU_SEL_2 0x00008e1a
4764
4765#define REG_A6XX_RB_PERFCTR_CCU_SEL_3 0x00008e1b
4766
4767#define REG_A6XX_RB_PERFCTR_CCU_SEL_4 0x00008e1c
4768
4769#define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28
4770
4037#define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28
4038
4771#define REG_A6XX_RB_PERFCTR_CMP_SEL_0 0x00008e2c
4039static inline uint32_t REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) { return 0x00008e2c + 0x1*i0; }
4772
4040
4773#define REG_A6XX_RB_PERFCTR_CMP_SEL_1 0x00008e2d
4774
4775#define REG_A6XX_RB_PERFCTR_CMP_SEL_2 0x00008e2e
4776
4777#define REG_A6XX_RB_PERFCTR_CMP_SEL_3 0x00008e2f
4778
4779#define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b
4780
4781#define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d
4782
4783#define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50
4784
4785#define REG_A6XX_RB_UNKNOWN_8E51 0x00008e51
4786#define A6XX_RB_UNKNOWN_8E51__MASK 0xffffffff

--- 103 unchanged lines hidden (view full) ---

4890#define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00
4891#define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT 8
4892static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val)
4893{
4894 return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK;
4895}
4896
4897#define REG_A6XX_VPC_UNKNOWN_9107 0x00009107
4041#define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b
4042
4043#define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d
4044
4045#define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50
4046
4047#define REG_A6XX_RB_UNKNOWN_8E51 0x00008e51
4048#define A6XX_RB_UNKNOWN_8E51__MASK 0xffffffff

--- 103 unchanged lines hidden (view full) ---

4152#define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00
4153#define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT 8
4154static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val)
4155{
4156 return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK;
4157}
4158
4159#define REG_A6XX_VPC_UNKNOWN_9107 0x00009107
4160#define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD 0x00000001
4161#define A6XX_VPC_UNKNOWN_9107_UNK2 0x00000004
4898
4899#define REG_A6XX_VPC_POLYGON_MODE 0x00009108
4900#define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003
4901#define A6XX_VPC_POLYGON_MODE_MODE__SHIFT 0
4902static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
4903{
4904 return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK;
4905}

--- 10 unchanged lines hidden (view full) ---

4916
4917#define REG_A6XX_VPC_UNKNOWN_9211 0x00009211
4918
4919static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; }
4920
4921static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }
4922
4923#define REG_A6XX_VPC_SO_CNTL 0x00009216
4162
4163#define REG_A6XX_VPC_POLYGON_MODE 0x00009108
4164#define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003
4165#define A6XX_VPC_POLYGON_MODE_MODE__SHIFT 0
4166static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
4167{
4168 return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK;
4169}

--- 10 unchanged lines hidden (view full) ---

4180
4181#define REG_A6XX_VPC_UNKNOWN_9211 0x00009211
4182
4183static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; }
4184
4185static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }
4186
4187#define REG_A6XX_VPC_SO_CNTL 0x00009216
4924#define A6XX_VPC_SO_CNTL_UNK0__MASK 0x000000ff
4925#define A6XX_VPC_SO_CNTL_UNK0__SHIFT 0
4926static inline uint32_t A6XX_VPC_SO_CNTL_UNK0(uint32_t val)
4188#define A6XX_VPC_SO_CNTL_ADDR__MASK 0x000000ff
4189#define A6XX_VPC_SO_CNTL_ADDR__SHIFT 0
4190static inline uint32_t A6XX_VPC_SO_CNTL_ADDR(uint32_t val)
4927{
4191{
4928 return ((val) << A6XX_VPC_SO_CNTL_UNK0__SHIFT) & A6XX_VPC_SO_CNTL_UNK0__MASK;
4192 return ((val) << A6XX_VPC_SO_CNTL_ADDR__SHIFT) & A6XX_VPC_SO_CNTL_ADDR__MASK;
4929}
4193}
4930#define A6XX_VPC_SO_CNTL_ENABLE 0x00010000
4194#define A6XX_VPC_SO_CNTL_RESET 0x00010000
4931
4932#define REG_A6XX_VPC_SO_PROG 0x00009217
4933#define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
4934#define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0
4935static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val)
4936{
4937 return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK;
4938}

--- 13 unchanged lines hidden (view full) ---

4952#define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000
4953#define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14
4954static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val)
4955{
4956 return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK;
4957}
4958#define A6XX_VPC_SO_PROG_B_EN 0x00800000
4959
4195
4196#define REG_A6XX_VPC_SO_PROG 0x00009217
4197#define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
4198#define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0
4199static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val)
4200{
4201 return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK;
4202}

--- 13 unchanged lines hidden (view full) ---

4216#define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000
4217#define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14
4218static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val)
4219{
4220 return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK;
4221}
4222#define A6XX_VPC_SO_PROG_B_EN 0x00800000
4223
4960#define REG_A6XX_VPC_SO_STREAM_COUNTS_LO 0x00009218
4961
4962#define REG_A6XX_VPC_SO_STREAM_COUNTS_HI 0x00009219
4963
4964#define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218
4965#define A6XX_VPC_SO_STREAM_COUNTS__MASK 0xffffffff
4966#define A6XX_VPC_SO_STREAM_COUNTS__SHIFT 0
4967static inline uint32_t A6XX_VPC_SO_STREAM_COUNTS(uint32_t val)
4968{
4969 return ((val) << A6XX_VPC_SO_STREAM_COUNTS__SHIFT) & A6XX_VPC_SO_STREAM_COUNTS__MASK;
4970}
4971
4972static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4973
4974static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4975#define A6XX_VPC_SO_BUFFER_BASE__MASK 0xffffffff
4976#define A6XX_VPC_SO_BUFFER_BASE__SHIFT 0
4977static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val)
4978{
4979 return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK;
4980}
4981
4224#define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218
4225#define A6XX_VPC_SO_STREAM_COUNTS__MASK 0xffffffff
4226#define A6XX_VPC_SO_STREAM_COUNTS__SHIFT 0
4227static inline uint32_t A6XX_VPC_SO_STREAM_COUNTS(uint32_t val)
4228{
4229 return ((val) << A6XX_VPC_SO_STREAM_COUNTS__SHIFT) & A6XX_VPC_SO_STREAM_COUNTS__MASK;
4230}
4231
4232static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4233
4234static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4235#define A6XX_VPC_SO_BUFFER_BASE__MASK 0xffffffff
4236#define A6XX_VPC_SO_BUFFER_BASE__SHIFT 0
4237static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val)
4238{
4239 return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK;
4240}
4241
4982static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4983
4984static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; }
4985
4986static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }
4987#define A6XX_VPC_SO_BUFFER_SIZE__MASK 0xfffffffc
4988#define A6XX_VPC_SO_BUFFER_SIZE__SHIFT 2
4989static inline uint32_t A6XX_VPC_SO_BUFFER_SIZE(uint32_t val)
4990{
4991 return ((val >> 2) << A6XX_VPC_SO_BUFFER_SIZE__SHIFT) & A6XX_VPC_SO_BUFFER_SIZE__MASK;
4992}
4993

--- 10 unchanged lines hidden (view full) ---

5004static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; }
5005#define A6XX_VPC_SO_FLUSH_BASE__MASK 0xffffffff
5006#define A6XX_VPC_SO_FLUSH_BASE__SHIFT 0
5007static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val)
5008{
5009 return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK;
5010}
5011
4242static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }
4243#define A6XX_VPC_SO_BUFFER_SIZE__MASK 0xfffffffc
4244#define A6XX_VPC_SO_BUFFER_SIZE__SHIFT 2
4245static inline uint32_t A6XX_VPC_SO_BUFFER_SIZE(uint32_t val)
4246{
4247 return ((val >> 2) << A6XX_VPC_SO_BUFFER_SIZE__SHIFT) & A6XX_VPC_SO_BUFFER_SIZE__MASK;
4248}
4249

--- 10 unchanged lines hidden (view full) ---

4260static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; }
4261#define A6XX_VPC_SO_FLUSH_BASE__MASK 0xffffffff
4262#define A6XX_VPC_SO_FLUSH_BASE__SHIFT 0
4263static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val)
4264{
4265 return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK;
4266}
4267
5012static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; }
5013
5014static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; }
5015
5016#define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236
5017#define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001
5018
5019#define REG_A6XX_VPC_UNKNOWN_9300 0x00009300
5020
5021#define REG_A6XX_VPC_VS_PACK 0x00009301
5022#define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK 0x000000ff
5023#define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT 0

--- 8 unchanged lines hidden (view full) ---

5032 return ((val) << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK;
5033}
5034#define A6XX_VPC_VS_PACK_PSIZELOC__MASK 0x00ff0000
5035#define A6XX_VPC_VS_PACK_PSIZELOC__SHIFT 16
5036static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val)
5037{
5038 return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK;
5039}
4268#define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236
4269#define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001
4270
4271#define REG_A6XX_VPC_UNKNOWN_9300 0x00009300
4272
4273#define REG_A6XX_VPC_VS_PACK 0x00009301
4274#define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK 0x000000ff
4275#define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT 0

--- 8 unchanged lines hidden (view full) ---

4284 return ((val) << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK;
4285}
4286#define A6XX_VPC_VS_PACK_PSIZELOC__MASK 0x00ff0000
4287#define A6XX_VPC_VS_PACK_PSIZELOC__SHIFT 16
4288static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val)
4289{
4290 return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK;
4291}
5040#define A6XX_VPC_VS_PACK_UNK24__MASK 0x0f000000
5041#define A6XX_VPC_VS_PACK_UNK24__SHIFT 24
5042static inline uint32_t A6XX_VPC_VS_PACK_UNK24(uint32_t val)
4292#define A6XX_VPC_VS_PACK_EXTRAPOS__MASK 0x0f000000
4293#define A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT 24
4294static inline uint32_t A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val)
5043{
4295{
5044 return ((val) << A6XX_VPC_VS_PACK_UNK24__SHIFT) & A6XX_VPC_VS_PACK_UNK24__MASK;
4296 return ((val) << A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_VS_PACK_EXTRAPOS__MASK;
5045}
5046
5047#define REG_A6XX_VPC_GS_PACK 0x00009302
5048#define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK 0x000000ff
5049#define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT 0
5050static inline uint32_t A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val)
5051{
5052 return ((val) << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK;

--- 5 unchanged lines hidden (view full) ---

5058 return ((val) << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK;
5059}
5060#define A6XX_VPC_GS_PACK_PSIZELOC__MASK 0x00ff0000
5061#define A6XX_VPC_GS_PACK_PSIZELOC__SHIFT 16
5062static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val)
5063{
5064 return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK;
5065}
4297}
4298
4299#define REG_A6XX_VPC_GS_PACK 0x00009302
4300#define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK 0x000000ff
4301#define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT 0
4302static inline uint32_t A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val)
4303{
4304 return ((val) << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK;

--- 5 unchanged lines hidden (view full) ---

4310 return ((val) << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK;
4311}
4312#define A6XX_VPC_GS_PACK_PSIZELOC__MASK 0x00ff0000
4313#define A6XX_VPC_GS_PACK_PSIZELOC__SHIFT 16
4314static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val)
4315{
4316 return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK;
4317}
5066#define A6XX_VPC_GS_PACK_UNK24__MASK 0x0f000000
5067#define A6XX_VPC_GS_PACK_UNK24__SHIFT 24
5068static inline uint32_t A6XX_VPC_GS_PACK_UNK24(uint32_t val)
4318#define A6XX_VPC_GS_PACK_EXTRAPOS__MASK 0x0f000000
4319#define A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT 24
4320static inline uint32_t A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val)
5069{
4321{
5070 return ((val) << A6XX_VPC_GS_PACK_UNK24__SHIFT) & A6XX_VPC_GS_PACK_UNK24__MASK;
4322 return ((val) << A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_GS_PACK_EXTRAPOS__MASK;
5071}
5072
5073#define REG_A6XX_VPC_DS_PACK 0x00009303
5074#define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK 0x000000ff
5075#define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT 0
5076static inline uint32_t A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val)
5077{
5078 return ((val) << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK;

--- 5 unchanged lines hidden (view full) ---

5084 return ((val) << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK;
5085}
5086#define A6XX_VPC_DS_PACK_PSIZELOC__MASK 0x00ff0000
5087#define A6XX_VPC_DS_PACK_PSIZELOC__SHIFT 16
5088static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val)
5089{
5090 return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK;
5091}
4323}
4324
4325#define REG_A6XX_VPC_DS_PACK 0x00009303
4326#define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK 0x000000ff
4327#define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT 0
4328static inline uint32_t A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val)
4329{
4330 return ((val) << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK;

--- 5 unchanged lines hidden (view full) ---

4336 return ((val) << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK;
4337}
4338#define A6XX_VPC_DS_PACK_PSIZELOC__MASK 0x00ff0000
4339#define A6XX_VPC_DS_PACK_PSIZELOC__SHIFT 16
4340static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val)
4341{
4342 return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK;
4343}
5092#define A6XX_VPC_DS_PACK_UNK24__MASK 0x0f000000
5093#define A6XX_VPC_DS_PACK_UNK24__SHIFT 24
5094static inline uint32_t A6XX_VPC_DS_PACK_UNK24(uint32_t val)
4344#define A6XX_VPC_DS_PACK_EXTRAPOS__MASK 0x0f000000
4345#define A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT 24
4346static inline uint32_t A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val)
5095{
4347{
5096 return ((val) << A6XX_VPC_DS_PACK_UNK24__SHIFT) & A6XX_VPC_DS_PACK_UNK24__MASK;
4348 return ((val) << A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_DS_PACK_EXTRAPOS__MASK;
5097}
5098
5099#define REG_A6XX_VPC_CNTL_0 0x00009304
5100#define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff
5101#define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0
5102static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)
5103{
5104 return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK;
5105}
5106#define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK 0x0000ff00
5107#define A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT 8
5108static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val)
5109{
5110 return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK;
5111}
5112#define A6XX_VPC_CNTL_0_VARYING 0x00010000
4349}
4350
4351#define REG_A6XX_VPC_CNTL_0 0x00009304
4352#define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff
4353#define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0
4354static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)
4355{
4356 return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK;
4357}
4358#define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK 0x0000ff00
4359#define A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT 8
4360static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val)
4361{
4362 return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK;
4363}
4364#define A6XX_VPC_CNTL_0_VARYING 0x00010000
5113#define A6XX_VPC_CNTL_0_UNKLOC__MASK 0xff000000
5114#define A6XX_VPC_CNTL_0_UNKLOC__SHIFT 24
5115static inline uint32_t A6XX_VPC_CNTL_0_UNKLOC(uint32_t val)
4365#define A6XX_VPC_CNTL_0_VIEWIDLOC__MASK 0xff000000
4366#define A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT 24
4367static inline uint32_t A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val)
5116{
4368{
5117 return ((val) << A6XX_VPC_CNTL_0_UNKLOC__SHIFT) & A6XX_VPC_CNTL_0_UNKLOC__MASK;
4369 return ((val) << A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT) & A6XX_VPC_CNTL_0_VIEWIDLOC__MASK;
5118}
5119
4370}
4371
5120#define REG_A6XX_VPC_SO_BUF_CNTL 0x00009305
5121#define A6XX_VPC_SO_BUF_CNTL_BUF0 0x00000001
5122#define A6XX_VPC_SO_BUF_CNTL_BUF1 0x00000008
5123#define A6XX_VPC_SO_BUF_CNTL_BUF2 0x00000040
5124#define A6XX_VPC_SO_BUF_CNTL_BUF3 0x00000200
5125#define A6XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000
5126#define A6XX_VPC_SO_BUF_CNTL_UNK16__MASK 0x000f0000
5127#define A6XX_VPC_SO_BUF_CNTL_UNK16__SHIFT 16
5128static inline uint32_t A6XX_VPC_SO_BUF_CNTL_UNK16(uint32_t val)
4372#define REG_A6XX_VPC_SO_STREAM_CNTL 0x00009305
4373#define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK 0x00000007
4374#define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT 0
4375static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val)
5129{
4376{
5130 return ((val) << A6XX_VPC_SO_BUF_CNTL_UNK16__SHIFT) & A6XX_VPC_SO_BUF_CNTL_UNK16__MASK;
4377 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK;
5131}
4378}
4379#define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK 0x00000038
4380#define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT 3
4381static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val)
4382{
4383 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK;
4384}
4385#define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK 0x000001c0
4386#define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT 6
4387static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val)
4388{
4389 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK;
4390}
4391#define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK 0x00000e00
4392#define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT 9
4393static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val)
4394{
4395 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK;
4396}
4397#define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000
4398#define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15
4399static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val)
4400{
4401 return ((val) << A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK;
4402}
5132
5133#define REG_A6XX_VPC_SO_DISABLE 0x00009306
5134#define A6XX_VPC_SO_DISABLE_DISABLE 0x00000001
5135
5136#define REG_A6XX_VPC_UNKNOWN_9600 0x00009600
5137
5138#define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601
5139
5140#define REG_A6XX_VPC_UNKNOWN_9602 0x00009602
5141
5142#define REG_A6XX_VPC_UNKNOWN_9603 0x00009603
5143
4403
4404#define REG_A6XX_VPC_SO_DISABLE 0x00009306
4405#define A6XX_VPC_SO_DISABLE_DISABLE 0x00000001
4406
4407#define REG_A6XX_VPC_UNKNOWN_9600 0x00009600
4408
4409#define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601
4410
4411#define REG_A6XX_VPC_UNKNOWN_9602 0x00009602
4412
4413#define REG_A6XX_VPC_UNKNOWN_9603 0x00009603
4414
5144#define REG_A6XX_VPC_PERFCTR_VPC_SEL_0 0x00009604
4415static inline uint32_t REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x00009604 + 0x1*i0; }
5145
4416
5146#define REG_A6XX_VPC_PERFCTR_VPC_SEL_1 0x00009605
5147
5148#define REG_A6XX_VPC_PERFCTR_VPC_SEL_2 0x00009606
5149
5150#define REG_A6XX_VPC_PERFCTR_VPC_SEL_3 0x00009607
5151
5152#define REG_A6XX_VPC_PERFCTR_VPC_SEL_4 0x00009608
5153
5154#define REG_A6XX_VPC_PERFCTR_VPC_SEL_5 0x00009609
5155
5156#define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800
5157
4417#define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800
4418
5158#define REG_A6XX_PC_UNKNOWN_9801 0x00009801
5159#define A6XX_PC_UNKNOWN_9801_UNK0__MASK 0x000007ff
5160#define A6XX_PC_UNKNOWN_9801_UNK0__SHIFT 0
5161static inline uint32_t A6XX_PC_UNKNOWN_9801_UNK0(uint32_t val)
4419#define REG_A6XX_PC_HS_INPUT_SIZE 0x00009801
4420#define A6XX_PC_HS_INPUT_SIZE_SIZE__MASK 0x000007ff
4421#define A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT 0
4422static inline uint32_t A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val)
5162{
4423{
5163 return ((val) << A6XX_PC_UNKNOWN_9801_UNK0__SHIFT) & A6XX_PC_UNKNOWN_9801_UNK0__MASK;
4424 return ((val) << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK;
5164}
4425}
5165#define A6XX_PC_UNKNOWN_9801_UNK13__MASK 0x00002000
5166#define A6XX_PC_UNKNOWN_9801_UNK13__SHIFT 13
5167static inline uint32_t A6XX_PC_UNKNOWN_9801_UNK13(uint32_t val)
4426#define A6XX_PC_HS_INPUT_SIZE_UNK13__MASK 0x00002000
4427#define A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT 13
4428static inline uint32_t A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val)
5168{
4429{
5169 return ((val) << A6XX_PC_UNKNOWN_9801_UNK13__SHIFT) & A6XX_PC_UNKNOWN_9801_UNK13__MASK;
4430 return ((val) << A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT) & A6XX_PC_HS_INPUT_SIZE_UNK13__MASK;
5170}
5171
5172#define REG_A6XX_PC_TESS_CNTL 0x00009802
5173#define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003
5174#define A6XX_PC_TESS_CNTL_SPACING__SHIFT 0
5175static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val)
5176{
5177 return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK;

--- 38 unchanged lines hidden (view full) ---

5216}
5217#define A6XX_PC_EVENT_CMD_EVENT__MASK 0x0000007f
5218#define A6XX_PC_EVENT_CMD_EVENT__SHIFT 0
5219static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val)
5220{
5221 return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK;
5222}
5223
4431}
4432
4433#define REG_A6XX_PC_TESS_CNTL 0x00009802
4434#define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003
4435#define A6XX_PC_TESS_CNTL_SPACING__SHIFT 0
4436static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val)
4437{
4438 return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK;

--- 38 unchanged lines hidden (view full) ---

4477}
4478#define A6XX_PC_EVENT_CMD_EVENT__MASK 0x0000007f
4479#define A6XX_PC_EVENT_CMD_EVENT__SHIFT 0
4480static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val)
4481{
4482 return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK;
4483}
4484
4485#define REG_A6XX_PC_MARKER 0x00009880
4486
5224#define REG_A6XX_PC_POLYGON_MODE 0x00009981
5225#define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003
5226#define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0
5227static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
5228{
5229 return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK;
5230}
5231
4487#define REG_A6XX_PC_POLYGON_MODE 0x00009981
4488#define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003
4489#define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0
4490static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
4491{
4492 return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK;
4493}
4494
5232#define REG_A6XX_PC_UNKNOWN_9980 0x00009980
4495#define REG_A6XX_PC_RASTER_CNTL 0x00009980
4496#define A6XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003
4497#define A6XX_PC_RASTER_CNTL_STREAM__SHIFT 0
4498static inline uint32_t A6XX_PC_RASTER_CNTL_STREAM(uint32_t val)
4499{
4500 return ((val) << A6XX_PC_RASTER_CNTL_STREAM__SHIFT) & A6XX_PC_RASTER_CNTL_STREAM__MASK;
4501}
4502#define A6XX_PC_RASTER_CNTL_DISCARD 0x00000004
5233
5234#define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00
5235#define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001
5236#define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002
5237#define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN 0x00000004
5238#define A6XX_PC_PRIMITIVE_CNTL_0_UNK3 0x00000008
5239
5240#define REG_A6XX_PC_VS_OUT_CNTL 0x00009b01

--- 81 unchanged lines hidden (view full) ---

5322#define REG_A6XX_PC_PRIMITIVE_CNTL_6 0x00009b06
5323#define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK 0x000007ff
5324#define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT 0
5325static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val)
5326{
5327 return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK;
5328}
5329
4503
4504#define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00
4505#define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001
4506#define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002
4507#define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN 0x00000004
4508#define A6XX_PC_PRIMITIVE_CNTL_0_UNK3 0x00000008
4509
4510#define REG_A6XX_PC_VS_OUT_CNTL 0x00009b01

--- 81 unchanged lines hidden (view full) ---

4592#define REG_A6XX_PC_PRIMITIVE_CNTL_6 0x00009b06
4593#define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK 0x000007ff
4594#define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT 0
4595static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val)
4596{
4597 return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK;
4598}
4599
5330#define REG_A6XX_PC_UNKNOWN_9B07 0x00009b07
4600#define REG_A6XX_PC_MULTIVIEW_CNTL 0x00009b07
4601#define A6XX_PC_MULTIVIEW_CNTL_ENABLE 0x00000001
4602#define A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002
4603#define A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c
4604#define A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT 2
4605static inline uint32_t A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val)
4606{
4607 return ((val) << A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK;
4608}
5331
4609
5332#define REG_A6XX_PC_UNKNOWN_9B08 0x00009b08
4610#define REG_A6XX_PC_MULTIVIEW_MASK 0x00009b08
5333
5334#define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00
5335#define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f
5336#define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT 0
5337static inline uint32_t A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
5338{
5339 return ((val) << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK;
5340}
5341#define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00
5342#define A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT 8
5343static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val)
5344{
5345 return ((val) << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK;
5346}
5347
5348#define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00
5349
5350#define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01
5351
4611
4612#define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00
4613#define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f
4614#define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT 0
4615static inline uint32_t A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
4616{
4617 return ((val) << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK;
4618}
4619#define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00
4620#define A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT 8
4621static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val)
4622{
4623 return ((val) << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK;
4624}
4625
4626#define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00
4627
4628#define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01
4629
5352#define REG_A6XX_PC_TESSFACTOR_ADDR_LO 0x00009e08
4630#define REG_A6XX_PC_DRAW_INDX_BASE 0x00009e04
5353
4631
5354#define REG_A6XX_PC_TESSFACTOR_ADDR_HI 0x00009e09
4632#define REG_A6XX_PC_DRAW_FIRST_INDX 0x00009e06
5355
4633
4634#define REG_A6XX_PC_DRAW_MAX_INDICES 0x00009e07
4635
5356#define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08
5357#define A6XX_PC_TESSFACTOR_ADDR__MASK 0xffffffff
5358#define A6XX_PC_TESSFACTOR_ADDR__SHIFT 0
5359static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val)
5360{
5361 return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK;
5362}
5363
4636#define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08
4637#define A6XX_PC_TESSFACTOR_ADDR__MASK 0xffffffff
4638#define A6XX_PC_TESSFACTOR_ADDR__SHIFT 0
4639static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val)
4640{
4641 return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK;
4642}
4643
4644#define REG_A6XX_PC_DRAW_INITIATOR 0x00009e0b
4645#define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f
4646#define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0
4647static inline uint32_t A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
4648{
4649 return ((val) << A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK;
4650}
4651#define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0
4652#define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6
4653static inline uint32_t A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
4654{
4655 return ((val) << A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK;
4656}
4657#define A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK 0x00000300
4658#define A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT 8
4659static inline uint32_t A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
4660{
4661 return ((val) << A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT) & A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK;
4662}
4663#define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000c00
4664#define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT 10
4665static inline uint32_t A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val)
4666{
4667 return ((val) << A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK;
4668}
4669#define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK 0x00003000
4670#define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT 12
4671static inline uint32_t A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val)
4672{
4673 return ((val) << A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK;
4674}
4675#define A6XX_PC_DRAW_INITIATOR_GS_ENABLE 0x00010000
4676#define A6XX_PC_DRAW_INITIATOR_TESS_ENABLE 0x00020000
4677
4678#define REG_A6XX_PC_DRAW_NUM_INSTANCES 0x00009e0c
4679
4680#define REG_A6XX_PC_DRAW_NUM_INDICES 0x00009e0d
4681
5364#define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11
5365#define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK 0x0000ffff
5366#define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT 0
5367static inline uint32_t A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val)
5368{
5369 return ((val) << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK;
5370}
5371#define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK 0x003f0000

--- 20 unchanged lines hidden (view full) ---

5392#define REG_A6XX_PC_BIN_DRAW_STRM 0x00009e14
5393#define A6XX_PC_BIN_DRAW_STRM__MASK 0xffffffff
5394#define A6XX_PC_BIN_DRAW_STRM__SHIFT 0
5395static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val)
5396{
5397 return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK;
5398}
5399
4682#define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11
4683#define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK 0x0000ffff
4684#define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT 0
4685static inline uint32_t A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val)
4686{
4687 return ((val) << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK;
4688}
4689#define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK 0x003f0000

--- 20 unchanged lines hidden (view full) ---

4710#define REG_A6XX_PC_BIN_DRAW_STRM 0x00009e14
4711#define A6XX_PC_BIN_DRAW_STRM__MASK 0xffffffff
4712#define A6XX_PC_BIN_DRAW_STRM__SHIFT 0
4713static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val)
4714{
4715 return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK;
4716}
4717
5400#define REG_A6XX_PC_PERFCTR_PC_SEL_0 0x00009e34
4718#define REG_A6XX_PC_VISIBILITY_OVERRIDE 0x00009e1c
4719#define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE 0x00000001
5401
4720
5402#define REG_A6XX_PC_PERFCTR_PC_SEL_1 0x00009e35
4721static inline uint32_t REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e34 + 0x1*i0; }
5403
4722
5404#define REG_A6XX_PC_PERFCTR_PC_SEL_2 0x00009e36
5405
5406#define REG_A6XX_PC_PERFCTR_PC_SEL_3 0x00009e37
5407
5408#define REG_A6XX_PC_PERFCTR_PC_SEL_4 0x00009e38
5409
5410#define REG_A6XX_PC_PERFCTR_PC_SEL_5 0x00009e39
5411
5412#define REG_A6XX_PC_PERFCTR_PC_SEL_6 0x00009e3a
5413
5414#define REG_A6XX_PC_PERFCTR_PC_SEL_7 0x00009e3b
5415
5416#define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72
5417
5418#define REG_A6XX_VFD_CONTROL_0 0x0000a000
5419#define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK 0x0000003f
5420#define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT 0
5421static inline uint32_t A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val)
5422{
5423 return ((val) << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK;

--- 19 unchanged lines hidden (view full) ---

5443 return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK;
5444}
5445#define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000
5446#define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16
5447static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
5448{
5449 return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
5450}
4723#define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72
4724
4725#define REG_A6XX_VFD_CONTROL_0 0x0000a000
4726#define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK 0x0000003f
4727#define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT 0
4728static inline uint32_t A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val)
4729{
4730 return ((val) << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK;

--- 19 unchanged lines hidden (view full) ---

4750 return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK;
4751}
4752#define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000
4753#define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16
4754static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
4755{
4756 return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
4757}
4758#define A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK 0xff000000
4759#define A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT 24
4760static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val)
4761{
4762 return ((val) << A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK;
4763}
5451
5452#define REG_A6XX_VFD_CONTROL_2 0x0000a002
5453#define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK 0x000000ff
5454#define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT 0
5455static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSPATCHID(uint32_t val)
5456{
5457 return ((val) << A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK;
5458}
5459#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK 0x0000ff00
5460#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT 8
5461static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val)
5462{
5463 return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK;
5464}
5465
5466#define REG_A6XX_VFD_CONTROL_3 0x0000a003
4764
4765#define REG_A6XX_VFD_CONTROL_2 0x0000a002
4766#define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK 0x000000ff
4767#define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT 0
4768static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSPATCHID(uint32_t val)
4769{
4770 return ((val) << A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK;
4771}
4772#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK 0x0000ff00
4773#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT 8
4774static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val)
4775{
4776 return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK;
4777}
4778
4779#define REG_A6XX_VFD_CONTROL_3 0x0000a003
4780#define A6XX_VFD_CONTROL_3_UNK0__MASK 0x000000ff
4781#define A6XX_VFD_CONTROL_3_UNK0__SHIFT 0
4782static inline uint32_t A6XX_VFD_CONTROL_3_UNK0(uint32_t val)
4783{
4784 return ((val) << A6XX_VFD_CONTROL_3_UNK0__SHIFT) & A6XX_VFD_CONTROL_3_UNK0__MASK;
4785}
5467#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK 0x0000ff00
5468#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT 8
5469static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPATCHID(uint32_t val)
5470{
5471 return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK;
5472}
5473#define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
5474#define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16

--- 4 unchanged lines hidden (view full) ---

5479#define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
5480#define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
5481static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
5482{
5483 return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK;
5484}
5485
5486#define REG_A6XX_VFD_CONTROL_4 0x0000a004
4786#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK 0x0000ff00
4787#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT 8
4788static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPATCHID(uint32_t val)
4789{
4790 return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK;
4791}
4792#define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
4793#define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16

--- 4 unchanged lines hidden (view full) ---

4798#define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
4799#define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
4800static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
4801{
4802 return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK;
4803}
4804
4805#define REG_A6XX_VFD_CONTROL_4 0x0000a004
4806#define A6XX_VFD_CONTROL_4_UNK0__MASK 0x000000ff
4807#define A6XX_VFD_CONTROL_4_UNK0__SHIFT 0
4808static inline uint32_t A6XX_VFD_CONTROL_4_UNK0(uint32_t val)
4809{
4810 return ((val) << A6XX_VFD_CONTROL_4_UNK0__SHIFT) & A6XX_VFD_CONTROL_4_UNK0__MASK;
4811}
5487
5488#define REG_A6XX_VFD_CONTROL_5 0x0000a005
5489#define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK 0x000000ff
5490#define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT 0
5491static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val)
5492{
5493 return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK;
5494}
4812
4813#define REG_A6XX_VFD_CONTROL_5 0x0000a005
4814#define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK 0x000000ff
4815#define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT 0
4816static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val)
4817{
4818 return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK;
4819}
4820#define A6XX_VFD_CONTROL_5_UNK8__MASK 0x0000ff00
4821#define A6XX_VFD_CONTROL_5_UNK8__SHIFT 8
4822static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val)
4823{
4824 return ((val) << A6XX_VFD_CONTROL_5_UNK8__SHIFT) & A6XX_VFD_CONTROL_5_UNK8__MASK;
4825}
5495
5496#define REG_A6XX_VFD_CONTROL_6 0x0000a006
5497#define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001
5498
5499#define REG_A6XX_VFD_MODE_CNTL 0x0000a007
5500#define A6XX_VFD_MODE_CNTL_BINNING_PASS 0x00000001
4826
4827#define REG_A6XX_VFD_CONTROL_6 0x0000a006
4828#define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001
4829
4830#define REG_A6XX_VFD_MODE_CNTL 0x0000a007
4831#define A6XX_VFD_MODE_CNTL_BINNING_PASS 0x00000001
4832#define A6XX_VFD_MODE_CNTL_UNK1 0x00000002
4833#define A6XX_VFD_MODE_CNTL_UNK2 0x00000004
5501
4834
5502#define REG_A6XX_VFD_UNKNOWN_A008 0x0000a008
4835#define REG_A6XX_VFD_MULTIVIEW_CNTL 0x0000a008
4836#define A6XX_VFD_MULTIVIEW_CNTL_ENABLE 0x00000001
4837#define A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002
4838#define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c
4839#define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT 2
4840static inline uint32_t A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val)
4841{
4842 return ((val) << A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK;
4843}
5503
5504#define REG_A6XX_VFD_ADD_OFFSET 0x0000a009
5505#define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001
5506#define A6XX_VFD_ADD_OFFSET_INSTANCE 0x00000002
5507
5508#define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e
5509
5510#define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f
5511
5512static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
5513
5514static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
4844
4845#define REG_A6XX_VFD_ADD_OFFSET 0x0000a009
4846#define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001
4847#define A6XX_VFD_ADD_OFFSET_INSTANCE 0x00000002
4848
4849#define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e
4850
4851#define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f
4852
4853static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
4854
4855static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
4856#define A6XX_VFD_FETCH_BASE__MASK 0xffffffff
4857#define A6XX_VFD_FETCH_BASE__SHIFT 0
4858static inline uint32_t A6XX_VFD_FETCH_BASE(uint32_t val)
4859{
4860 return ((val) << A6XX_VFD_FETCH_BASE__SHIFT) & A6XX_VFD_FETCH_BASE__MASK;
4861}
5515
4862
5516static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
5517
5518static inline uint32_t REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000a011 + 0x4*i0; }
5519
5520static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }
5521
5522static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; }
5523
5524static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
5525
5526static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
5527#define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f

--- 39 unchanged lines hidden (view full) ---

5567#define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4
5568static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
5569{
5570 return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
5571}
5572
5573#define REG_A6XX_SP_UNKNOWN_A0F8 0x0000a0f8
5574
4863static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }
4864
4865static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; }
4866
4867static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
4868
4869static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
4870#define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f

--- 39 unchanged lines hidden (view full) ---

4910#define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4
4911static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
4912{
4913 return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
4914}
4915
4916#define REG_A6XX_SP_UNKNOWN_A0F8 0x0000a0f8
4917
4918#define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601
4919
4920static inline uint32_t REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; }
4921
5575#define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800
4922#define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800
4923#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000
4924#define A6XX_SP_VS_CTRL_REG0_UNK21 0x00200000
4925#define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
4926#define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
4927static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
4928{
4929 return ((val) << A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
4930}
5576#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5577#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5578static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5579{
5580 return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5581}
5582#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5583#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
5584static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5585{
5586 return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5587}
4931#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
4932#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
4933static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4934{
4935 return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4936}
4937#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
4938#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
4939static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4940{
4941 return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4942}
4943#define A6XX_SP_VS_CTRL_REG0_UNK13 0x00002000
5588#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5589#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5590static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5591{
5592 return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
5593}
4944#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
4945#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14
4946static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4947{
4948 return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
4949}
5594#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5595#define A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
5596static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5597{
5598 return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
5599}
5600#define A6XX_SP_VS_CTRL_REG0_VARYING 0x00400000
5601#define A6XX_SP_VS_CTRL_REG0_DIFF_FINE 0x00800000
5602#define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x04000000
5603#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x80000000
5604
5605#define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801
5606
5607#define REG_A6XX_SP_VS_PRIMITIVE_CNTL 0x0000a802
5608#define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
5609#define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT 0
5610static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val)
5611{
5612 return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK;
5613}
4950
4951#define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801
4952
4953#define REG_A6XX_SP_VS_PRIMITIVE_CNTL 0x0000a802
4954#define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
4955#define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT 0
4956static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val)
4957{
4958 return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK;
4959}
4960#define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0
4961#define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6
4962static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
4963{
4964 return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
4965}
5614
5615static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
5616
5617static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
5618#define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
5619#define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
5620static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
5621{

--- 41 unchanged lines hidden (view full) ---

5663}
5664#define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
5665#define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
5666static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
5667{
5668 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
5669}
5670
4966
4967static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
4968
4969static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
4970#define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
4971#define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
4972static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
4973{

--- 41 unchanged lines hidden (view full) ---

5015}
5016#define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
5017#define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
5018static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
5019{
5020 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
5021}
5022
5671#define REG_A6XX_SP_UNKNOWN_A81B 0x0000a81b
5023#define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET 0x0000a81b
5672
5024
5673#define REG_A6XX_SP_VS_OBJ_START_LO 0x0000a81c
5025#define REG_A6XX_SP_VS_OBJ_START 0x0000a81c
5026#define A6XX_SP_VS_OBJ_START__MASK 0xffffffff
5027#define A6XX_SP_VS_OBJ_START__SHIFT 0
5028static inline uint32_t A6XX_SP_VS_OBJ_START(uint32_t val)
5029{
5030 return ((val) << A6XX_SP_VS_OBJ_START__SHIFT) & A6XX_SP_VS_OBJ_START__MASK;
5031}
5674
5032
5675#define REG_A6XX_SP_VS_OBJ_START_HI 0x0000a81d
5033#define REG_A6XX_SP_VS_PVT_MEM_PARAM 0x0000a81e
5034#define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5035#define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
5036static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5037{
5038 return ((val >> 9) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5039}
5040#define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5041#define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
5042static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5043{
5044 return ((val) << A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5045}
5676
5046
5047#define REG_A6XX_SP_VS_PVT_MEM_ADDR 0x0000a81f
5048#define A6XX_SP_VS_PVT_MEM_ADDR__MASK 0xffffffff
5049#define A6XX_SP_VS_PVT_MEM_ADDR__SHIFT 0
5050static inline uint32_t A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val)
5051{
5052 return ((val) << A6XX_SP_VS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_VS_PVT_MEM_ADDR__MASK;
5053}
5054
5055#define REG_A6XX_SP_VS_PVT_MEM_SIZE 0x0000a821
5056#define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5057#define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
5058static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5059{
5060 return ((val >> 12) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5061}
5062#define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5063
5677#define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822
5678
5679#define REG_A6XX_SP_VS_CONFIG 0x0000a823
5680#define A6XX_SP_VS_CONFIG_BINDLESS_TEX 0x00000001
5681#define A6XX_SP_VS_CONFIG_BINDLESS_SAMP 0x00000002
5682#define A6XX_SP_VS_CONFIG_BINDLESS_IBO 0x00000004
5683#define A6XX_SP_VS_CONFIG_BINDLESS_UBO 0x00000008
5684#define A6XX_SP_VS_CONFIG_ENABLED 0x00000100

--- 4 unchanged lines hidden (view full) ---

5689 return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK;
5690}
5691#define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x003e0000
5692#define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17
5693static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val)
5694{
5695 return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK;
5696}
5064#define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822
5065
5066#define REG_A6XX_SP_VS_CONFIG 0x0000a823
5067#define A6XX_SP_VS_CONFIG_BINDLESS_TEX 0x00000001
5068#define A6XX_SP_VS_CONFIG_BINDLESS_SAMP 0x00000002
5069#define A6XX_SP_VS_CONFIG_BINDLESS_IBO 0x00000004
5070#define A6XX_SP_VS_CONFIG_BINDLESS_UBO 0x00000008
5071#define A6XX_SP_VS_CONFIG_ENABLED 0x00000100

--- 4 unchanged lines hidden (view full) ---

5076 return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK;
5077}
5078#define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x003e0000
5079#define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17
5080static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val)
5081{
5082 return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK;
5083}
5697#define A6XX_SP_VS_CONFIG_NIBO__MASK 0x3fc00000
5084#define A6XX_SP_VS_CONFIG_NIBO__MASK 0x1fc00000
5698#define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22
5699static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val)
5700{
5701 return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK;
5702}
5703
5704#define REG_A6XX_SP_VS_INSTRLEN 0x0000a824
5705
5085#define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22
5086static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val)
5087{
5088 return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK;
5089}
5090
5091#define REG_A6XX_SP_VS_INSTRLEN 0x0000a824
5092
5093#define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET 0x0000a825
5094#define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
5095#define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
5096static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
5097{
5098 return ((val >> 11) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__MASK;
5099}
5100
5706#define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830
5101#define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830
5102#define A6XX_SP_HS_CTRL_REG0_UNK20 0x00100000
5103#define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK 0x00000001
5104#define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT 0
5105static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5106{
5107 return ((val) << A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK;
5108}
5707#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5708#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5709static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5710{
5711 return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5712}
5713#define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5714#define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
5715static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5716{
5717 return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5718}
5109#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5110#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5111static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5112{
5113 return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5114}
5115#define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5116#define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
5117static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5118{
5119 return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5120}
5121#define A6XX_SP_HS_CTRL_REG0_UNK13 0x00002000
5719#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5720#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5721static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5722{
5723 return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
5724}
5122#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5123#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5124static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5125{
5126 return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
5127}
5725#define A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5726#define A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT 20
5727static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5128
5129#define REG_A6XX_SP_HS_WAVE_INPUT_SIZE 0x0000a831
5130
5131#define REG_A6XX_SP_HS_BRANCH_COND 0x0000a832
5132
5133#define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET 0x0000a833
5134
5135#define REG_A6XX_SP_HS_OBJ_START 0x0000a834
5136#define A6XX_SP_HS_OBJ_START__MASK 0xffffffff
5137#define A6XX_SP_HS_OBJ_START__SHIFT 0
5138static inline uint32_t A6XX_SP_HS_OBJ_START(uint32_t val)
5728{
5139{
5729 return ((val) << A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK;
5140 return ((val) << A6XX_SP_HS_OBJ_START__SHIFT) & A6XX_SP_HS_OBJ_START__MASK;
5730}
5141}
5731#define A6XX_SP_HS_CTRL_REG0_VARYING 0x00400000
5732#define A6XX_SP_HS_CTRL_REG0_DIFF_FINE 0x00800000
5733#define A6XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x04000000
5734#define A6XX_SP_HS_CTRL_REG0_MERGEDREGS 0x80000000
5735
5142
5736#define REG_A6XX_SP_HS_UNKNOWN_A831 0x0000a831
5143#define REG_A6XX_SP_HS_PVT_MEM_PARAM 0x0000a836
5144#define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5145#define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
5146static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5147{
5148 return ((val >> 9) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5149}
5150#define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5151#define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
5152static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5153{
5154 return ((val) << A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5155}
5737
5156
5738#define REG_A6XX_SP_HS_UNKNOWN_A833 0x0000a833
5157#define REG_A6XX_SP_HS_PVT_MEM_ADDR 0x0000a837
5158#define A6XX_SP_HS_PVT_MEM_ADDR__MASK 0xffffffff
5159#define A6XX_SP_HS_PVT_MEM_ADDR__SHIFT 0
5160static inline uint32_t A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val)
5161{
5162 return ((val) << A6XX_SP_HS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_HS_PVT_MEM_ADDR__MASK;
5163}
5739
5164
5740#define REG_A6XX_SP_HS_OBJ_START_LO 0x0000a834
5165#define REG_A6XX_SP_HS_PVT_MEM_SIZE 0x0000a839
5166#define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5167#define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
5168static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5169{
5170 return ((val >> 12) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5171}
5172#define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5741
5173
5742#define REG_A6XX_SP_HS_OBJ_START_HI 0x0000a835
5743
5744#define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a
5745
5746#define REG_A6XX_SP_HS_CONFIG 0x0000a83b
5747#define A6XX_SP_HS_CONFIG_BINDLESS_TEX 0x00000001
5748#define A6XX_SP_HS_CONFIG_BINDLESS_SAMP 0x00000002
5749#define A6XX_SP_HS_CONFIG_BINDLESS_IBO 0x00000004
5750#define A6XX_SP_HS_CONFIG_BINDLESS_UBO 0x00000008
5751#define A6XX_SP_HS_CONFIG_ENABLED 0x00000100

--- 4 unchanged lines hidden (view full) ---

5756 return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK;
5757}
5758#define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x003e0000
5759#define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17
5760static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val)
5761{
5762 return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK;
5763}
5174#define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a
5175
5176#define REG_A6XX_SP_HS_CONFIG 0x0000a83b
5177#define A6XX_SP_HS_CONFIG_BINDLESS_TEX 0x00000001
5178#define A6XX_SP_HS_CONFIG_BINDLESS_SAMP 0x00000002
5179#define A6XX_SP_HS_CONFIG_BINDLESS_IBO 0x00000004
5180#define A6XX_SP_HS_CONFIG_BINDLESS_UBO 0x00000008
5181#define A6XX_SP_HS_CONFIG_ENABLED 0x00000100

--- 4 unchanged lines hidden (view full) ---

5186 return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK;
5187}
5188#define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x003e0000
5189#define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17
5190static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val)
5191{
5192 return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK;
5193}
5764#define A6XX_SP_HS_CONFIG_NIBO__MASK 0x3fc00000
5194#define A6XX_SP_HS_CONFIG_NIBO__MASK 0x1fc00000
5765#define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22
5766static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val)
5767{
5768 return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK;
5769}
5770
5771#define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c
5772
5195#define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22
5196static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val)
5197{
5198 return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK;
5199}
5200
5201#define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c
5202
5203#define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET 0x0000a83d
5204#define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
5205#define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
5206static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
5207{
5208 return ((val >> 11) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__MASK;
5209}
5210
5773#define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840
5211#define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840
5212#define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x00100000
5213#define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK 0x00000001
5214#define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT 0
5215static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5216{
5217 return ((val) << A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK;
5218}
5774#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5775#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5776static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5777{
5778 return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5779}
5780#define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5781#define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
5782static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5783{
5784 return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5785}
5219#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5220#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5221static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5222{
5223 return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5224}
5225#define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5226#define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
5227static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5228{
5229 return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5230}
5231#define A6XX_SP_DS_CTRL_REG0_UNK13 0x00002000
5786#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5787#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5788static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5789{
5790 return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
5791}
5232#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5233#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5234static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5235{
5236 return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
5237}
5792#define A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5793#define A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT 20
5794static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5795{
5796 return ((val) << A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK;
5797}
5798#define A6XX_SP_DS_CTRL_REG0_VARYING 0x00400000
5799#define A6XX_SP_DS_CTRL_REG0_DIFF_FINE 0x00800000
5800#define A6XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x04000000
5801#define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x80000000
5802
5238
5239#define REG_A6XX_SP_DS_BRANCH_COND 0x0000a841
5240
5803#define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842
5804#define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
5805#define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT 0
5806static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val)
5807{
5808 return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK;
5809}
5241#define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842
5242#define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
5243#define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT 0
5244static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val)
5245{
5246 return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK;
5247}
5248#define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0
5249#define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6
5250static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
5251{
5252 return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
5253}
5810
5811static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
5812
5813static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
5814#define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff
5815#define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
5816static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
5817{

--- 41 unchanged lines hidden (view full) ---

5859}
5860#define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
5861#define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
5862static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
5863{
5864 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
5865}
5866
5254
5255static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
5256
5257static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
5258#define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff
5259#define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
5260static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
5261{

--- 41 unchanged lines hidden (view full) ---

5303}
5304#define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
5305#define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
5306static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
5307{
5308 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
5309}
5310
5867#define REG_A6XX_SP_DS_UNKNOWN_A85B 0x0000a85b
5311#define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET 0x0000a85b
5868
5312
5869#define REG_A6XX_SP_DS_OBJ_START_LO 0x0000a85c
5313#define REG_A6XX_SP_DS_OBJ_START 0x0000a85c
5314#define A6XX_SP_DS_OBJ_START__MASK 0xffffffff
5315#define A6XX_SP_DS_OBJ_START__SHIFT 0
5316static inline uint32_t A6XX_SP_DS_OBJ_START(uint32_t val)
5317{
5318 return ((val) << A6XX_SP_DS_OBJ_START__SHIFT) & A6XX_SP_DS_OBJ_START__MASK;
5319}
5870
5320
5871#define REG_A6XX_SP_DS_OBJ_START_HI 0x0000a85d
5321#define REG_A6XX_SP_DS_PVT_MEM_PARAM 0x0000a85e
5322#define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5323#define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
5324static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5325{
5326 return ((val >> 9) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5327}
5328#define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5329#define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
5330static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5331{
5332 return ((val) << A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5333}
5872
5334
5335#define REG_A6XX_SP_DS_PVT_MEM_ADDR 0x0000a85f
5336#define A6XX_SP_DS_PVT_MEM_ADDR__MASK 0xffffffff
5337#define A6XX_SP_DS_PVT_MEM_ADDR__SHIFT 0
5338static inline uint32_t A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val)
5339{
5340 return ((val) << A6XX_SP_DS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_DS_PVT_MEM_ADDR__MASK;
5341}
5342
5343#define REG_A6XX_SP_DS_PVT_MEM_SIZE 0x0000a861
5344#define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5345#define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
5346static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5347{
5348 return ((val >> 12) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5349}
5350#define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5351
5873#define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862
5874
5875#define REG_A6XX_SP_DS_CONFIG 0x0000a863
5876#define A6XX_SP_DS_CONFIG_BINDLESS_TEX 0x00000001
5877#define A6XX_SP_DS_CONFIG_BINDLESS_SAMP 0x00000002
5878#define A6XX_SP_DS_CONFIG_BINDLESS_IBO 0x00000004
5879#define A6XX_SP_DS_CONFIG_BINDLESS_UBO 0x00000008
5880#define A6XX_SP_DS_CONFIG_ENABLED 0x00000100

--- 4 unchanged lines hidden (view full) ---

5885 return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK;
5886}
5887#define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x003e0000
5888#define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17
5889static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val)
5890{
5891 return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK;
5892}
5352#define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862
5353
5354#define REG_A6XX_SP_DS_CONFIG 0x0000a863
5355#define A6XX_SP_DS_CONFIG_BINDLESS_TEX 0x00000001
5356#define A6XX_SP_DS_CONFIG_BINDLESS_SAMP 0x00000002
5357#define A6XX_SP_DS_CONFIG_BINDLESS_IBO 0x00000004
5358#define A6XX_SP_DS_CONFIG_BINDLESS_UBO 0x00000008
5359#define A6XX_SP_DS_CONFIG_ENABLED 0x00000100

--- 4 unchanged lines hidden (view full) ---

5364 return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK;
5365}
5366#define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x003e0000
5367#define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17
5368static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val)
5369{
5370 return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK;
5371}
5893#define A6XX_SP_DS_CONFIG_NIBO__MASK 0x3fc00000
5372#define A6XX_SP_DS_CONFIG_NIBO__MASK 0x1fc00000
5894#define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22
5895static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val)
5896{
5897 return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK;
5898}
5899
5900#define REG_A6XX_SP_DS_INSTRLEN 0x0000a864
5901
5373#define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22
5374static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val)
5375{
5376 return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK;
5377}
5378
5379#define REG_A6XX_SP_DS_INSTRLEN 0x0000a864
5380
5381#define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET 0x0000a865
5382#define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
5383#define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
5384static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
5385{
5386 return ((val >> 11) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__MASK;
5387}
5388
5902#define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870
5389#define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870
5390#define A6XX_SP_GS_CTRL_REG0_UNK20 0x00100000
5391#define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK 0x00000001
5392#define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT 0
5393static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5394{
5395 return ((val) << A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK;
5396}
5903#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5904#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5905static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5906{
5907 return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5908}
5909#define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5910#define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
5911static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5912{
5913 return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5914}
5397#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5398#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5399static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5400{
5401 return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5402}
5403#define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5404#define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
5405static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5406{
5407 return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5408}
5409#define A6XX_SP_GS_CTRL_REG0_UNK13 0x00002000
5915#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5916#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5917static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5918{
5919 return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
5920}
5410#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5411#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5412static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5413{
5414 return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
5415}
5921#define A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5922#define A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT 20
5923static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5924{
5925 return ((val) << A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK;
5926}
5927#define A6XX_SP_GS_CTRL_REG0_VARYING 0x00400000
5928#define A6XX_SP_GS_CTRL_REG0_DIFF_FINE 0x00800000
5929#define A6XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x04000000
5930#define A6XX_SP_GS_CTRL_REG0_MERGEDREGS 0x80000000
5931
5932#define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871
5933
5934#define REG_A6XX_SP_GS_BRANCH_COND 0x0000a872
5935
5936#define REG_A6XX_SP_GS_PRIMITIVE_CNTL 0x0000a873
5937#define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
5938#define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT 0

--- 59 unchanged lines hidden (view full) ---

5998}
5999#define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
6000#define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24
6001static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
6002{
6003 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
6004}
6005
5416
5417#define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871
5418
5419#define REG_A6XX_SP_GS_BRANCH_COND 0x0000a872
5420
5421#define REG_A6XX_SP_GS_PRIMITIVE_CNTL 0x0000a873
5422#define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
5423#define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT 0

--- 59 unchanged lines hidden (view full) ---

5483}
5484#define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
5485#define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24
5486static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
5487{
5488 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
5489}
5490
6006#define REG_A6XX_SP_GS_OBJ_START_LO 0x0000a88d
5491#define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET 0x0000a88c
6007
5492
6008#define REG_A6XX_SP_GS_OBJ_START_HI 0x0000a88e
5493#define REG_A6XX_SP_GS_OBJ_START 0x0000a88d
5494#define A6XX_SP_GS_OBJ_START__MASK 0xffffffff
5495#define A6XX_SP_GS_OBJ_START__SHIFT 0
5496static inline uint32_t A6XX_SP_GS_OBJ_START(uint32_t val)
5497{
5498 return ((val) << A6XX_SP_GS_OBJ_START__SHIFT) & A6XX_SP_GS_OBJ_START__MASK;
5499}
6009
5500
5501#define REG_A6XX_SP_GS_PVT_MEM_PARAM 0x0000a88f
5502#define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5503#define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
5504static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5505{
5506 return ((val >> 9) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5507}
5508#define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5509#define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
5510static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5511{
5512 return ((val) << A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5513}
5514
5515#define REG_A6XX_SP_GS_PVT_MEM_ADDR 0x0000a890
5516#define A6XX_SP_GS_PVT_MEM_ADDR__MASK 0xffffffff
5517#define A6XX_SP_GS_PVT_MEM_ADDR__SHIFT 0
5518static inline uint32_t A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val)
5519{
5520 return ((val) << A6XX_SP_GS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_GS_PVT_MEM_ADDR__MASK;
5521}
5522
5523#define REG_A6XX_SP_GS_PVT_MEM_SIZE 0x0000a892
5524#define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5525#define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
5526static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5527{
5528 return ((val >> 12) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5529}
5530#define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5531
6010#define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893
6011
6012#define REG_A6XX_SP_GS_CONFIG 0x0000a894
6013#define A6XX_SP_GS_CONFIG_BINDLESS_TEX 0x00000001
6014#define A6XX_SP_GS_CONFIG_BINDLESS_SAMP 0x00000002
6015#define A6XX_SP_GS_CONFIG_BINDLESS_IBO 0x00000004
6016#define A6XX_SP_GS_CONFIG_BINDLESS_UBO 0x00000008
6017#define A6XX_SP_GS_CONFIG_ENABLED 0x00000100

--- 4 unchanged lines hidden (view full) ---

6022 return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK;
6023}
6024#define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x003e0000
6025#define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17
6026static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val)
6027{
6028 return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK;
6029}
5532#define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893
5533
5534#define REG_A6XX_SP_GS_CONFIG 0x0000a894
5535#define A6XX_SP_GS_CONFIG_BINDLESS_TEX 0x00000001
5536#define A6XX_SP_GS_CONFIG_BINDLESS_SAMP 0x00000002
5537#define A6XX_SP_GS_CONFIG_BINDLESS_IBO 0x00000004
5538#define A6XX_SP_GS_CONFIG_BINDLESS_UBO 0x00000008
5539#define A6XX_SP_GS_CONFIG_ENABLED 0x00000100

--- 4 unchanged lines hidden (view full) ---

5544 return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK;
5545}
5546#define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x003e0000
5547#define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17
5548static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val)
5549{
5550 return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK;
5551}
6030#define A6XX_SP_GS_CONFIG_NIBO__MASK 0x3fc00000
5552#define A6XX_SP_GS_CONFIG_NIBO__MASK 0x1fc00000
6031#define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22
6032static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val)
6033{
6034 return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK;
6035}
6036
6037#define REG_A6XX_SP_GS_INSTRLEN 0x0000a895
6038
5553#define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22
5554static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val)
5555{
5556 return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK;
5557}
5558
5559#define REG_A6XX_SP_GS_INSTRLEN 0x0000a895
5560
6039#define REG_A6XX_SP_VS_TEX_SAMP_LO 0x0000a8a0
5561#define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET 0x0000a896
5562#define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
5563#define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
5564static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
5565{
5566 return ((val >> 11) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__MASK;
5567}
6040
5568
6041#define REG_A6XX_SP_VS_TEX_SAMP_HI 0x0000a8a1
5569#define REG_A6XX_SP_VS_TEX_SAMP 0x0000a8a0
5570#define A6XX_SP_VS_TEX_SAMP__MASK 0xffffffff
5571#define A6XX_SP_VS_TEX_SAMP__SHIFT 0
5572static inline uint32_t A6XX_SP_VS_TEX_SAMP(uint32_t val)
5573{
5574 return ((val) << A6XX_SP_VS_TEX_SAMP__SHIFT) & A6XX_SP_VS_TEX_SAMP__MASK;
5575}
6042
5576
6043#define REG_A6XX_SP_HS_TEX_SAMP_LO 0x0000a8a2
5577#define REG_A6XX_SP_HS_TEX_SAMP 0x0000a8a2
5578#define A6XX_SP_HS_TEX_SAMP__MASK 0xffffffff
5579#define A6XX_SP_HS_TEX_SAMP__SHIFT 0
5580static inline uint32_t A6XX_SP_HS_TEX_SAMP(uint32_t val)
5581{
5582 return ((val) << A6XX_SP_HS_TEX_SAMP__SHIFT) & A6XX_SP_HS_TEX_SAMP__MASK;
5583}
6044
5584
6045#define REG_A6XX_SP_HS_TEX_SAMP_HI 0x0000a8a3
5585#define REG_A6XX_SP_DS_TEX_SAMP 0x0000a8a4
5586#define A6XX_SP_DS_TEX_SAMP__MASK 0xffffffff
5587#define A6XX_SP_DS_TEX_SAMP__SHIFT 0
5588static inline uint32_t A6XX_SP_DS_TEX_SAMP(uint32_t val)
5589{
5590 return ((val) << A6XX_SP_DS_TEX_SAMP__SHIFT) & A6XX_SP_DS_TEX_SAMP__MASK;
5591}
6046
5592
6047#define REG_A6XX_SP_DS_TEX_SAMP_LO 0x0000a8a4
5593#define REG_A6XX_SP_GS_TEX_SAMP 0x0000a8a6
5594#define A6XX_SP_GS_TEX_SAMP__MASK 0xffffffff
5595#define A6XX_SP_GS_TEX_SAMP__SHIFT 0
5596static inline uint32_t A6XX_SP_GS_TEX_SAMP(uint32_t val)
5597{
5598 return ((val) << A6XX_SP_GS_TEX_SAMP__SHIFT) & A6XX_SP_GS_TEX_SAMP__MASK;
5599}
6048
5600
6049#define REG_A6XX_SP_DS_TEX_SAMP_HI 0x0000a8a5
5601#define REG_A6XX_SP_VS_TEX_CONST 0x0000a8a8
5602#define A6XX_SP_VS_TEX_CONST__MASK 0xffffffff
5603#define A6XX_SP_VS_TEX_CONST__SHIFT 0
5604static inline uint32_t A6XX_SP_VS_TEX_CONST(uint32_t val)
5605{
5606 return ((val) << A6XX_SP_VS_TEX_CONST__SHIFT) & A6XX_SP_VS_TEX_CONST__MASK;
5607}
6050
5608
6051#define REG_A6XX_SP_GS_TEX_SAMP_LO 0x0000a8a6
5609#define REG_A6XX_SP_HS_TEX_CONST 0x0000a8aa
5610#define A6XX_SP_HS_TEX_CONST__MASK 0xffffffff
5611#define A6XX_SP_HS_TEX_CONST__SHIFT 0
5612static inline uint32_t A6XX_SP_HS_TEX_CONST(uint32_t val)
5613{
5614 return ((val) << A6XX_SP_HS_TEX_CONST__SHIFT) & A6XX_SP_HS_TEX_CONST__MASK;
5615}
6052
5616
6053#define REG_A6XX_SP_GS_TEX_SAMP_HI 0x0000a8a7
5617#define REG_A6XX_SP_DS_TEX_CONST 0x0000a8ac
5618#define A6XX_SP_DS_TEX_CONST__MASK 0xffffffff
5619#define A6XX_SP_DS_TEX_CONST__SHIFT 0
5620static inline uint32_t A6XX_SP_DS_TEX_CONST(uint32_t val)
5621{
5622 return ((val) << A6XX_SP_DS_TEX_CONST__SHIFT) & A6XX_SP_DS_TEX_CONST__MASK;
5623}
6054
5624
6055#define REG_A6XX_SP_VS_TEX_CONST_LO 0x0000a8a8
5625#define REG_A6XX_SP_GS_TEX_CONST 0x0000a8ae
5626#define A6XX_SP_GS_TEX_CONST__MASK 0xffffffff
5627#define A6XX_SP_GS_TEX_CONST__SHIFT 0
5628static inline uint32_t A6XX_SP_GS_TEX_CONST(uint32_t val)
5629{
5630 return ((val) << A6XX_SP_GS_TEX_CONST__SHIFT) & A6XX_SP_GS_TEX_CONST__MASK;
5631}
6056
5632
6057#define REG_A6XX_SP_VS_TEX_CONST_HI 0x0000a8a9
6058
6059#define REG_A6XX_SP_HS_TEX_CONST_LO 0x0000a8aa
6060
6061#define REG_A6XX_SP_HS_TEX_CONST_HI 0x0000a8ab
6062
6063#define REG_A6XX_SP_DS_TEX_CONST_LO 0x0000a8ac
6064
6065#define REG_A6XX_SP_DS_TEX_CONST_HI 0x0000a8ad
6066
6067#define REG_A6XX_SP_GS_TEX_CONST_LO 0x0000a8ae
6068
6069#define REG_A6XX_SP_GS_TEX_CONST_HI 0x0000a8af
6070
6071#define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980
5633#define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980
5634#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5635#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
5636static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
5637{
5638 return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
5639}
5640#define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000
5641#define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000
5642#define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000
5643#define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000
5644#define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000
5645#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000
5646#define A6XX_SP_FS_CTRL_REG0_UNK27__MASK 0x18000000
5647#define A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT 27
5648static inline uint32_t A6XX_SP_FS_CTRL_REG0_UNK27(uint32_t val)
5649{
5650 return ((val) << A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT) & A6XX_SP_FS_CTRL_REG0_UNK27__MASK;
5651}
5652#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000
5653#define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
5654#define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
5655static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5656{
5657 return ((val) << A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
5658}
6072#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
6073#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
6074static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
6075{
6076 return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
6077}
6078#define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
6079#define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
6080static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
6081{
6082 return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
6083}
5659#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5660#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5661static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5662{
5663 return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5664}
5665#define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5666#define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
5667static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5668{
5669 return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5670}
5671#define A6XX_SP_FS_CTRL_REG0_UNK13 0x00002000
6084#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
6085#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14
6086static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
6087{
6088 return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
6089}
5672#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5673#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5674static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5675{
5676 return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
5677}
6090#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
6091#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
6092static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
6093{
6094 return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
6095}
6096#define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000
6097#define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000
6098#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000
6099#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000
6100
6101#define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981
6102
5678
5679#define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981
5680
6103#define REG_A6XX_SP_UNKNOWN_A982 0x0000a982
5681#define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET 0x0000a982
6104
5682
6105#define REG_A6XX_SP_FS_OBJ_START_LO 0x0000a983
5683#define REG_A6XX_SP_FS_OBJ_START 0x0000a983
5684#define A6XX_SP_FS_OBJ_START__MASK 0xffffffff
5685#define A6XX_SP_FS_OBJ_START__SHIFT 0
5686static inline uint32_t A6XX_SP_FS_OBJ_START(uint32_t val)
5687{
5688 return ((val) << A6XX_SP_FS_OBJ_START__SHIFT) & A6XX_SP_FS_OBJ_START__MASK;
5689}
6106
5690
6107#define REG_A6XX_SP_FS_OBJ_START_HI 0x0000a984
5691#define REG_A6XX_SP_FS_PVT_MEM_PARAM 0x0000a985
5692#define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5693#define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
5694static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5695{
5696 return ((val >> 9) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5697}
5698#define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5699#define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
5700static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5701{
5702 return ((val) << A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5703}
6108
5704
5705#define REG_A6XX_SP_FS_PVT_MEM_ADDR 0x0000a986
5706#define A6XX_SP_FS_PVT_MEM_ADDR__MASK 0xffffffff
5707#define A6XX_SP_FS_PVT_MEM_ADDR__SHIFT 0
5708static inline uint32_t A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val)
5709{
5710 return ((val) << A6XX_SP_FS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_FS_PVT_MEM_ADDR__MASK;
5711}
5712
5713#define REG_A6XX_SP_FS_PVT_MEM_SIZE 0x0000a988
5714#define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5715#define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
5716static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5717{
5718 return ((val >> 12) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5719}
5720#define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5721
6109#define REG_A6XX_SP_BLEND_CNTL 0x0000a989
5722#define REG_A6XX_SP_BLEND_CNTL 0x0000a989
6110#define A6XX_SP_BLEND_CNTL_ENABLED 0x00000001
5723#define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
5724#define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
5725static inline uint32_t A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
5726{
5727 return ((val) << A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;
5728}
6111#define A6XX_SP_BLEND_CNTL_UNK8 0x00000100
6112#define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200
6113#define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
6114
6115#define REG_A6XX_SP_SRGB_CNTL 0x0000a98a
6116#define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001
6117#define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002
6118#define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004

--- 77 unchanged lines hidden (view full) ---

6196#define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d
6197#define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
6198#define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0
6199static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val)
6200{
6201 return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK;
6202}
6203
5729#define A6XX_SP_BLEND_CNTL_UNK8 0x00000100
5730#define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200
5731#define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
5732
5733#define REG_A6XX_SP_SRGB_CNTL 0x0000a98a
5734#define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001
5735#define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002
5736#define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004

--- 77 unchanged lines hidden (view full) ---

5814#define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d
5815#define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
5816#define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0
5817static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val)
5818{
5819 return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK;
5820}
5821
5822static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
5823
5824static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
5825#define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
5826#define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
5827static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
5828{
5829 return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK;
5830}
5831#define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
5832
6204static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
6205
6206static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
6207#define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
6208#define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
6209static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val)
6210{
6211 return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
6212}
6213#define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100
6214#define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200
5833static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
5834
5835static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
5836#define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
5837#define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
5838static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val)
5839{
5840 return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
5841}
5842#define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100
5843#define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200
5844#define A6XX_SP_FS_MRT_REG_UNK10 0x00000400
6215
6216#define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e
6217#define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007
6218#define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT 0
6219static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val)
6220{
6221 return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK;
6222}
6223#define A6XX_SP_FS_PREFETCH_CNTL_UNK3 0x00000008
6224#define A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK 0x00000ff0
6225#define A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT 4
6226static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK4(uint32_t val)
6227{
6228 return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK;
6229}
5845
5846#define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e
5847#define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007
5848#define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT 0
5849static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val)
5850{
5851 return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK;
5852}
5853#define A6XX_SP_FS_PREFETCH_CNTL_UNK3 0x00000008
5854#define A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK 0x00000ff0
5855#define A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT 4
5856static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK4(uint32_t val)
5857{
5858 return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK;
5859}
5860#define A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK 0x00007000
5861#define A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT 12
5862static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK12(uint32_t val)
5863{
5864 return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK;
5865}
6230
6231static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
6232
6233static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
6234#define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f
6235#define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0
6236static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val)
6237{

--- 29 unchanged lines hidden (view full) ---

6267static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(uint32_t val)
6268{
6269 return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK;
6270}
6271
6272static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
6273
6274static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
5866
5867static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
5868
5869static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
5870#define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f
5871#define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0
5872static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val)
5873{

--- 29 unchanged lines hidden (view full) ---

5903static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(uint32_t val)
5904{
5905 return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK;
5906}
5907
5908static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
5909
5910static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
6275#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x000000ff
5911#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x0000ffff
6276#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0
6277static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val)
6278{
6279 return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK;
6280}
5912#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0
5913static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val)
5914{
5915 return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK;
5916}
6281#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0x00ff0000
5917#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0xffff0000
6282#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16
6283static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val)
6284{
6285 return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK;
6286}
6287
6288#define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7
6289
6290#define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8
6291
5918#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16
5919static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val)
5920{
5921 return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK;
5922}
5923
5924#define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7
5925
5926#define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8
5927
6292#define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1
6293#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__MASK 0x00000001
6294#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__SHIFT 0
6295static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K(uint32_t val)
5928#define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET 0x0000a9a9
5929#define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
5930#define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
5931static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
6296{
5932{
6297 return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__MASK;
5933 return ((val >> 11) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__MASK;
6298}
6299
5934}
5935
6300#define REG_A6XX_SP_CS_UNKNOWN_A9B3 0x0000a9b3
6301
6302#define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba
6303
6304#define REG_A6XX_SP_FS_TEX_SAMP_LO 0x0000a9e0
6305
6306#define REG_A6XX_SP_FS_TEX_SAMP_HI 0x0000a9e1
6307
6308#define REG_A6XX_SP_CS_TEX_SAMP_LO 0x0000a9e2
6309
6310#define REG_A6XX_SP_CS_TEX_SAMP_HI 0x0000a9e3
6311
6312#define REG_A6XX_SP_FS_TEX_CONST_LO 0x0000a9e4
6313
6314#define REG_A6XX_SP_FS_TEX_CONST_HI 0x0000a9e5
6315
6316#define REG_A6XX_SP_CS_TEX_CONST_LO 0x0000a9e6
6317
6318#define REG_A6XX_SP_CS_TEX_CONST_HI 0x0000a9e7
6319
6320static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6321
6322static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6323
6324static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
6325
6326static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
6327#define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
6328#define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
6329static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
5936#define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0
5937#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5938#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20
5939static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
6330{
5940{
6331 return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK;
5941 return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
6332}
5942}
6333#define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
6334
6335#define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0
5943#define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000
5944#define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000
5945#define A6XX_SP_CS_CTRL_REG0_SEPARATEPROLOG 0x00800000
5946#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000
5947#define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001
5948#define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0
5949static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5950{
5951 return ((val) << A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK;
5952}
6336#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
6337#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
6338static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
6339{
6340 return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
6341}
6342#define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
6343#define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
6344static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
6345{
6346 return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
6347}
5953#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5954#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5955static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5956{
5957 return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5958}
5959#define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5960#define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
5961static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5962{
5963 return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5964}
5965#define A6XX_SP_CS_CTRL_REG0_UNK13 0x00002000
6348#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
6349#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14
6350static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
6351{
6352 return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
6353}
5966#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5967#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5968static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5969{
5970 return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
5971}
6354#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000
6355#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20
6356static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
5972
5973#define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1
5974#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK 0x0000001f
5975#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT 0
5976static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val)
6357{
5977{
6358 return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
5978 return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK;
6359}
5979}
6360#define A6XX_SP_CS_CTRL_REG0_VARYING 0x00400000
6361#define A6XX_SP_CS_CTRL_REG0_DIFF_FINE 0x00800000
6362#define A6XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x04000000
6363#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000
5980#define A6XX_SP_CS_UNKNOWN_A9B1_UNK5 0x00000020
5981#define A6XX_SP_CS_UNKNOWN_A9B1_UNK6 0x00000040
6364
5982
6365#define REG_A6XX_SP_CS_OBJ_START_LO 0x0000a9b4
5983#define REG_A6XX_SP_CS_BRANCH_COND 0x0000a9b2
6366
5984
6367#define REG_A6XX_SP_CS_OBJ_START_HI 0x0000a9b5
5985#define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET 0x0000a9b3
6368
5986
5987#define REG_A6XX_SP_CS_OBJ_START 0x0000a9b4
5988#define A6XX_SP_CS_OBJ_START__MASK 0xffffffff
5989#define A6XX_SP_CS_OBJ_START__SHIFT 0
5990static inline uint32_t A6XX_SP_CS_OBJ_START(uint32_t val)
5991{
5992 return ((val) << A6XX_SP_CS_OBJ_START__SHIFT) & A6XX_SP_CS_OBJ_START__MASK;
5993}
5994
5995#define REG_A6XX_SP_CS_PVT_MEM_PARAM 0x0000a9b6
5996#define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5997#define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
5998static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5999{
6000 return ((val >> 9) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
6001}
6002#define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
6003#define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
6004static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
6005{
6006 return ((val) << A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
6007}
6008
6009#define REG_A6XX_SP_CS_PVT_MEM_ADDR 0x0000a9b7
6010#define A6XX_SP_CS_PVT_MEM_ADDR__MASK 0xffffffff
6011#define A6XX_SP_CS_PVT_MEM_ADDR__SHIFT 0
6012static inline uint32_t A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val)
6013{
6014 return ((val) << A6XX_SP_CS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_CS_PVT_MEM_ADDR__MASK;
6015}
6016
6017#define REG_A6XX_SP_CS_PVT_MEM_SIZE 0x0000a9b9
6018#define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
6019#define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
6020static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
6021{
6022 return ((val >> 12) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
6023}
6024#define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
6025
6026#define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba
6027
6369#define REG_A6XX_SP_CS_CONFIG 0x0000a9bb
6370#define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001
6371#define A6XX_SP_CS_CONFIG_BINDLESS_SAMP 0x00000002
6372#define A6XX_SP_CS_CONFIG_BINDLESS_IBO 0x00000004
6373#define A6XX_SP_CS_CONFIG_BINDLESS_UBO 0x00000008
6374#define A6XX_SP_CS_CONFIG_ENABLED 0x00000100
6375#define A6XX_SP_CS_CONFIG_NTEX__MASK 0x0001fe00
6376#define A6XX_SP_CS_CONFIG_NTEX__SHIFT 9
6377static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val)
6378{
6379 return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK;
6380}
6381#define A6XX_SP_CS_CONFIG_NSAMP__MASK 0x003e0000
6382#define A6XX_SP_CS_CONFIG_NSAMP__SHIFT 17
6383static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val)
6384{
6385 return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK;
6386}
6028#define REG_A6XX_SP_CS_CONFIG 0x0000a9bb
6029#define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001
6030#define A6XX_SP_CS_CONFIG_BINDLESS_SAMP 0x00000002
6031#define A6XX_SP_CS_CONFIG_BINDLESS_IBO 0x00000004
6032#define A6XX_SP_CS_CONFIG_BINDLESS_UBO 0x00000008
6033#define A6XX_SP_CS_CONFIG_ENABLED 0x00000100
6034#define A6XX_SP_CS_CONFIG_NTEX__MASK 0x0001fe00
6035#define A6XX_SP_CS_CONFIG_NTEX__SHIFT 9
6036static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val)
6037{
6038 return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK;
6039}
6040#define A6XX_SP_CS_CONFIG_NSAMP__MASK 0x003e0000
6041#define A6XX_SP_CS_CONFIG_NSAMP__SHIFT 17
6042static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val)
6043{
6044 return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK;
6045}
6387#define A6XX_SP_CS_CONFIG_NIBO__MASK 0x3fc00000
6046#define A6XX_SP_CS_CONFIG_NIBO__MASK 0x1fc00000
6388#define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22
6389static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val)
6390{
6391 return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK;
6392}
6393
6394#define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc
6395
6047#define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22
6048static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val)
6049{
6050 return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK;
6051}
6052
6053#define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc
6054
6396#define REG_A6XX_SP_CS_IBO_LO 0x0000a9f2
6055#define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET 0x0000a9bd
6056#define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
6057#define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
6058static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
6059{
6060 return ((val >> 11) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__MASK;
6061}
6397
6062
6398#define REG_A6XX_SP_CS_IBO_HI 0x0000a9f3
6063#define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0
6064#define A6XX_SP_FS_TEX_SAMP__MASK 0xffffffff
6065#define A6XX_SP_FS_TEX_SAMP__SHIFT 0
6066static inline uint32_t A6XX_SP_FS_TEX_SAMP(uint32_t val)
6067{
6068 return ((val) << A6XX_SP_FS_TEX_SAMP__SHIFT) & A6XX_SP_FS_TEX_SAMP__MASK;
6069}
6399
6070
6071#define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2
6072#define A6XX_SP_CS_TEX_SAMP__MASK 0xffffffff
6073#define A6XX_SP_CS_TEX_SAMP__SHIFT 0
6074static inline uint32_t A6XX_SP_CS_TEX_SAMP(uint32_t val)
6075{
6076 return ((val) << A6XX_SP_CS_TEX_SAMP__SHIFT) & A6XX_SP_CS_TEX_SAMP__MASK;
6077}
6078
6079#define REG_A6XX_SP_FS_TEX_CONST 0x0000a9e4
6080#define A6XX_SP_FS_TEX_CONST__MASK 0xffffffff
6081#define A6XX_SP_FS_TEX_CONST__SHIFT 0
6082static inline uint32_t A6XX_SP_FS_TEX_CONST(uint32_t val)
6083{
6084 return ((val) << A6XX_SP_FS_TEX_CONST__SHIFT) & A6XX_SP_FS_TEX_CONST__MASK;
6085}
6086
6087#define REG_A6XX_SP_CS_TEX_CONST 0x0000a9e6
6088#define A6XX_SP_CS_TEX_CONST__MASK 0xffffffff
6089#define A6XX_SP_CS_TEX_CONST__SHIFT 0
6090static inline uint32_t A6XX_SP_CS_TEX_CONST(uint32_t val)
6091{
6092 return ((val) << A6XX_SP_CS_TEX_CONST__SHIFT) & A6XX_SP_CS_TEX_CONST__MASK;
6093}
6094
6095static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6096
6097static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6098
6099#define REG_A6XX_SP_CS_IBO 0x0000a9f2
6100#define A6XX_SP_CS_IBO__MASK 0xffffffff
6101#define A6XX_SP_CS_IBO__SHIFT 0
6102static inline uint32_t A6XX_SP_CS_IBO(uint32_t val)
6103{
6104 return ((val) << A6XX_SP_CS_IBO__SHIFT) & A6XX_SP_CS_IBO__MASK;
6105}
6106
6400#define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00
6401
6107#define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00
6108
6402#define REG_A6XX_SP_UNKNOWN_AB00 0x0000ab00
6109#define REG_A6XX_SP_MODE_CONTROL 0x0000ab00
6110#define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE 0x00000001
6111#define A6XX_SP_MODE_CONTROL_UNK1 0x00000002
6112#define A6XX_SP_MODE_CONTROL_UNK2 0x00000004
6113#define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE 0x00000008
6403
6404#define REG_A6XX_SP_FS_CONFIG 0x0000ab04
6405#define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001
6406#define A6XX_SP_FS_CONFIG_BINDLESS_SAMP 0x00000002
6407#define A6XX_SP_FS_CONFIG_BINDLESS_IBO 0x00000004
6408#define A6XX_SP_FS_CONFIG_BINDLESS_UBO 0x00000008
6409#define A6XX_SP_FS_CONFIG_ENABLED 0x00000100
6410#define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00
6411#define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9
6412static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val)
6413{
6414 return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK;
6415}
6416#define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x003e0000
6417#define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17
6418static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
6419{
6420 return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK;
6421}
6114
6115#define REG_A6XX_SP_FS_CONFIG 0x0000ab04
6116#define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001
6117#define A6XX_SP_FS_CONFIG_BINDLESS_SAMP 0x00000002
6118#define A6XX_SP_FS_CONFIG_BINDLESS_IBO 0x00000004
6119#define A6XX_SP_FS_CONFIG_BINDLESS_UBO 0x00000008
6120#define A6XX_SP_FS_CONFIG_ENABLED 0x00000100
6121#define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00
6122#define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9
6123static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val)
6124{
6125 return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK;
6126}
6127#define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x003e0000
6128#define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17
6129static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
6130{
6131 return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK;
6132}
6422#define A6XX_SP_FS_CONFIG_NIBO__MASK 0x3fc00000
6133#define A6XX_SP_FS_CONFIG_NIBO__MASK 0x1fc00000
6423#define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22
6424static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val)
6425{
6426 return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK;
6427}
6428
6429#define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05
6430
6431static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
6432
6433static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
6434
6134#define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22
6135static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val)
6136{
6137 return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK;
6138}
6139
6140#define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05
6141
6142static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
6143
6144static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
6145
6435#define REG_A6XX_SP_IBO_LO 0x0000ab1a
6146#define REG_A6XX_SP_IBO 0x0000ab1a
6147#define A6XX_SP_IBO__MASK 0xffffffff
6148#define A6XX_SP_IBO__SHIFT 0
6149static inline uint32_t A6XX_SP_IBO(uint32_t val)
6150{
6151 return ((val) << A6XX_SP_IBO__SHIFT) & A6XX_SP_IBO__MASK;
6152}
6436
6153
6437#define REG_A6XX_SP_IBO_HI 0x0000ab1b
6438
6439#define REG_A6XX_SP_IBO_COUNT 0x0000ab20
6440
6441#define REG_A6XX_SP_2D_DST_FORMAT 0x0000acc0
6442#define A6XX_SP_2D_DST_FORMAT_NORM 0x00000001
6443#define A6XX_SP_2D_DST_FORMAT_SINT 0x00000002
6444#define A6XX_SP_2D_DST_FORMAT_UINT 0x00000004
6445#define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8
6446#define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3

--- 6 unchanged lines hidden (view full) ---

6453#define A6XX_SP_2D_DST_FORMAT_MASK__SHIFT 12
6454static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val)
6455{
6456 return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK;
6457}
6458
6459#define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00
6460
6154#define REG_A6XX_SP_IBO_COUNT 0x0000ab20
6155
6156#define REG_A6XX_SP_2D_DST_FORMAT 0x0000acc0
6157#define A6XX_SP_2D_DST_FORMAT_NORM 0x00000001
6158#define A6XX_SP_2D_DST_FORMAT_SINT 0x00000002
6159#define A6XX_SP_2D_DST_FORMAT_UINT 0x00000004
6160#define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8
6161#define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3

--- 6 unchanged lines hidden (view full) ---

6168#define A6XX_SP_2D_DST_FORMAT_MASK__SHIFT 12
6169static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val)
6170{
6171 return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK;
6172}
6173
6174#define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00
6175
6176#define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01
6177
6178#define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02
6179
6461#define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03
6462
6180#define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03
6181
6463#define REG_A6XX_SP_UNKNOWN_AE04 0x0000ae04
6182#define REG_A6XX_SP_FLOAT_CNTL 0x0000ae04
6183#define A6XX_SP_FLOAT_CNTL_F16_NO_INF 0x00000008
6464
6184
6465#define REG_A6XX_SP_UNKNOWN_AE0F 0x0000ae0f
6185#define REG_A6XX_SP_PERFCTR_ENABLE 0x0000ae0f
6186#define A6XX_SP_PERFCTR_ENABLE_VS 0x00000001
6187#define A6XX_SP_PERFCTR_ENABLE_HS 0x00000002
6188#define A6XX_SP_PERFCTR_ENABLE_DS 0x00000004
6189#define A6XX_SP_PERFCTR_ENABLE_GS 0x00000008
6190#define A6XX_SP_PERFCTR_ENABLE_FS 0x00000010
6191#define A6XX_SP_PERFCTR_ENABLE_CS 0x00000020
6466
6192
6193static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; }
6194
6467#define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180
6195#define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180
6196#define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff
6197#define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0
6198static inline uint32_t A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)
6199{
6200 return ((val) << A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK;
6201}
6468
6469#define REG_A6XX_SP_UNKNOWN_B182 0x0000b182
6470
6471#define REG_A6XX_SP_UNKNOWN_B183 0x0000b183
6472
6202
6203#define REG_A6XX_SP_UNKNOWN_B182 0x0000b182
6204
6205#define REG_A6XX_SP_UNKNOWN_B183 0x0000b183
6206
6207#define REG_A6XX_SP_UNKNOWN_B190 0x0000b190
6208
6209#define REG_A6XX_SP_UNKNOWN_B191 0x0000b191
6210
6473#define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300
6474#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
6475#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
6476static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
6477{
6478 return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
6479}
6211#define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300
6212#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
6213#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
6214static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
6215{
6216 return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
6217}
6218#define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK 0x0000000c
6219#define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT 2
6220static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val)
6221{
6222 return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK;
6223}
6480
6481#define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301
6482#define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
6483#define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
6484static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
6485{
6486 return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
6487}
6488#define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
6489
6490#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302
6224
6225#define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301
6226#define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
6227#define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
6228static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
6229{
6230 return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
6231}
6232#define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
6233
6234#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302
6235#define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff
6236#define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0
6237static inline uint32_t A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)
6238{
6239 return ((val) << A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK;
6240}
6491
6241
6492#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000b302
6493
6494#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000b303
6495
6496#define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304
6497#define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001
6498#define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
6499
6500#define REG_A6XX_SP_TP_SAMPLE_LOCATION_0 0x0000b305
6501#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
6502#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
6503static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)

--- 88 unchanged lines hidden (view full) ---

6592}
6593#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
6594#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
6595static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
6596{
6597 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
6598}
6599
6242#define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304
6243#define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001
6244#define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
6245
6246#define REG_A6XX_SP_TP_SAMPLE_LOCATION_0 0x0000b305
6247#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
6248#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
6249static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)

--- 88 unchanged lines hidden (view full) ---

6338}
6339#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
6340#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
6341static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
6342{
6343 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
6344}
6345
6346#define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307
6347#define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00003fff
6348#define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0
6349static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
6350{
6351 return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK;
6352}
6353#define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x3fff0000
6354#define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16
6355static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
6356{
6357 return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
6358}
6359
6600#define REG_A6XX_SP_TP_UNKNOWN_B309 0x0000b309
6601
6602#define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0
6603#define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
6604#define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
6605static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val)
6606{
6607 return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK;

--- 14 unchanged lines hidden (view full) ---

6622#define A6XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000
6623#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000
6624#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14
6625static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val)
6626{
6627 return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK;
6628}
6629#define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000
6360#define REG_A6XX_SP_TP_UNKNOWN_B309 0x0000b309
6361
6362#define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0
6363#define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
6364#define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
6365static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val)
6366{
6367 return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK;

--- 14 unchanged lines hidden (view full) ---

6382#define A6XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000
6383#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000
6384#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14
6385static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val)
6386{
6387 return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK;
6388}
6389#define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000
6390#define A6XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000
6630#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000
6391#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000
6392#define A6XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000
6631#define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000
6393#define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000
6394#define A6XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000
6632#define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000
6395#define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000
6396#define A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000
6397#define A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23
6398static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val)
6399{
6400 return ((val) << A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK;
6401}
6402#define A6XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000
6633
6634#define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1
6635#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff
6636#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0
6637static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val)
6638{
6639 return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK;
6640}
6641#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000
6642#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15
6643static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val)
6644{
6645 return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK;
6646}
6647
6403
6404#define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1
6405#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff
6406#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0
6407static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val)
6408{
6409 return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK;
6410}
6411#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000
6412#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15
6413static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val)
6414{
6415 return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK;
6416}
6417
6648#define REG_A6XX_SP_PS_2D_SRC_LO 0x0000b4c2
6649
6650#define REG_A6XX_SP_PS_2D_SRC_HI 0x0000b4c3
6651
6652#define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2
6418#define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2
6419#define A6XX_SP_PS_2D_SRC__MASK 0xffffffff
6420#define A6XX_SP_PS_2D_SRC__SHIFT 0
6421static inline uint32_t A6XX_SP_PS_2D_SRC(uint32_t val)
6422{
6423 return ((val) << A6XX_SP_PS_2D_SRC__SHIFT) & A6XX_SP_PS_2D_SRC__MASK;
6424}
6653
6654#define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4
6425
6426#define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4
6655#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x01fffe00
6427#define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff
6428#define A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0
6429static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val)
6430{
6431 return ((val) << A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK;
6432}
6433#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00
6656#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9
6657static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
6658{
6659 return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;
6660}
6661
6434#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9
6435static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
6436{
6437 return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;
6438}
6439
6662#define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO 0x0000b4ca
6440#define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5
6441#define A6XX_SP_PS_2D_SRC_PLANE1__MASK 0xffffffff
6442#define A6XX_SP_PS_2D_SRC_PLANE1__SHIFT 0
6443static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val)
6444{
6445 return ((val) << A6XX_SP_PS_2D_SRC_PLANE1__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE1__MASK;
6446}
6663
6447
6664#define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI 0x0000b4cb
6448#define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b4c7
6449#define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff
6450#define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0
6451static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val)
6452{
6453 return ((val >> 6) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK;
6454}
6665
6455
6456#define REG_A6XX_SP_PS_2D_SRC_PLANE2 0x0000b4c8
6457#define A6XX_SP_PS_2D_SRC_PLANE2__MASK 0xffffffff
6458#define A6XX_SP_PS_2D_SRC_PLANE2__SHIFT 0
6459static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val)
6460{
6461 return ((val) << A6XX_SP_PS_2D_SRC_PLANE2__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE2__MASK;
6462}
6463
6666#define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca
6464#define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca
6465#define A6XX_SP_PS_2D_SRC_FLAGS__MASK 0xffffffff
6466#define A6XX_SP_PS_2D_SRC_FLAGS__SHIFT 0
6467static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val)
6468{
6469 return ((val) << A6XX_SP_PS_2D_SRC_FLAGS__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS__MASK;
6470}
6667
6668#define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc
6471
6472#define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc
6669#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK 0x000007ff
6670#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT 0
6671static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH(uint32_t val)
6473#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff
6474#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0
6475static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val)
6672{
6476{
6673 return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK;
6477 return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK;
6674}
6478}
6675#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK 0x003ff800
6676#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT 11
6677static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH(uint32_t val)
6479
6480#define REG_A6XX_SP_PS_UNKNOWN_B4CD 0x0000b4cd
6481
6482#define REG_A6XX_SP_PS_UNKNOWN_B4CE 0x0000b4ce
6483
6484#define REG_A6XX_SP_PS_UNKNOWN_B4CF 0x0000b4cf
6485
6486#define REG_A6XX_SP_PS_UNKNOWN_B4D0 0x0000b4d0
6487
6488#define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1
6489#define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff
6490#define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0
6491static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
6678{
6492{
6679 return ((val >> 7) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK;
6493 return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK;
6680}
6494}
6495#define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000
6496#define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16
6497static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
6498{
6499 return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
6500}
6681
6501
6682#define REG_A6XX_SP_UNKNOWN_B600 0x0000b600
6502#define REG_A6XX_TPL1_UNKNOWN_B600 0x0000b600
6683
6503
6684#define REG_A6XX_SP_UNKNOWN_B605 0x0000b605
6504#define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601
6685
6505
6506#define REG_A6XX_TPL1_UNKNOWN_B602 0x0000b602
6507
6508#define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604
6509#define A6XX_TPL1_NC_MODE_CNTL_MODE 0x00000001
6510#define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006
6511#define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT 1
6512static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val)
6513{
6514 return ((val) << A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK;
6515}
6516#define A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008
6517#define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000010
6518#define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT 4
6519static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val)
6520{
6521 return ((val) << A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK;
6522}
6523#define A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK 0x000000c0
6524#define A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT 6
6525static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val)
6526{
6527 return ((val) << A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK;
6528}
6529
6530#define REG_A6XX_TPL1_UNKNOWN_B605 0x0000b605
6531
6532#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608
6533
6534#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609
6535
6536#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a
6537
6538#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b
6539
6540#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c
6541
6542static inline uint32_t REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) { return 0x0000b610 + 0x1*i0; }
6543
6686#define REG_A6XX_HLSQ_VS_CNTL 0x0000b800
6687#define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff
6688#define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0
6689static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)
6690{
6691 return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK;
6692}
6693#define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100

--- 23 unchanged lines hidden (view full) ---

6717{
6718 return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
6719}
6720#define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100
6721
6722#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820
6723
6724#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821
6544#define REG_A6XX_HLSQ_VS_CNTL 0x0000b800
6545#define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff
6546#define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0
6547static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)
6548{
6549 return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK;
6550}
6551#define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100

--- 23 unchanged lines hidden (view full) ---

6575{
6576 return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
6577}
6578#define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100
6579
6580#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820
6581
6582#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821
6583#define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK 0xffffffff
6584#define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT 0
6585static inline uint32_t A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val)
6586{
6587 return ((val) << A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK;
6588}
6725
6726#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823
6727
6589
6590#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823
6591
6728#define REG_A6XX_HLSQ_UNKNOWN_B980 0x0000b980
6592#define REG_A6XX_HLSQ_FS_CNTL_0 0x0000b980
6593#define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001
6594#define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0
6595static inline uint32_t A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val)
6596{
6597 return ((val) << A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK;
6598}
6599#define A6XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002
6600#define A6XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc
6601#define A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2
6602static inline uint32_t A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val)
6603{
6604 return ((val) << A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A6XX_HLSQ_FS_CNTL_0_UNK2__MASK;
6605}
6729
6606
6607#define REG_A6XX_HLSQ_UNKNOWN_B981 0x0000b981
6608
6730#define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982
6731
6732#define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983
6733#define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
6734#define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
6735static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
6736{
6737 return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;

--- 65 unchanged lines hidden (view full) ---

6803#define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
6804#define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
6805static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
6806{
6807 return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
6808}
6809
6810#define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986
6609#define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982
6610
6611#define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983
6612#define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
6613#define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
6614static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
6615{
6616 return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;

--- 65 unchanged lines hidden (view full) ---

6682#define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
6683#define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
6684static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
6685{
6686 return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
6687}
6688
6689#define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986
6690#define A6XX_HLSQ_CONTROL_5_REG_UNK0__MASK 0x000000ff
6691#define A6XX_HLSQ_CONTROL_5_REG_UNK0__SHIFT 0
6692static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_UNK0(uint32_t val)
6693{
6694 return ((val) << A6XX_HLSQ_CONTROL_5_REG_UNK0__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_UNK0__MASK;
6695}
6696#define A6XX_HLSQ_CONTROL_5_REG_UNK8__MASK 0x0000ff00
6697#define A6XX_HLSQ_CONTROL_5_REG_UNK8__SHIFT 8
6698static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_UNK8(uint32_t val)
6699{
6700 return ((val) << A6XX_HLSQ_CONTROL_5_REG_UNK8__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_UNK8__MASK;
6701}
6811
6812#define REG_A6XX_HLSQ_CS_CNTL 0x0000b987
6813#define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff
6814#define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0
6815static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val)
6816{
6817 return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK;
6818}

--- 75 unchanged lines hidden (view full) ---

6894
6895#define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997
6896#define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
6897#define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0
6898static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
6899{
6900 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
6901}
6702
6703#define REG_A6XX_HLSQ_CS_CNTL 0x0000b987
6704#define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff
6705#define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0
6706static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val)
6707{
6708 return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK;
6709}

--- 75 unchanged lines hidden (view full) ---

6785
6786#define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997
6787#define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
6788#define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0
6789static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
6790{
6791 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
6792}
6902#define A6XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00
6903#define A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8
6904static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)
6793#define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00
6794#define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT 8
6795static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val)
6905{
6796{
6906 return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK0__MASK;
6797 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK;
6907}
6798}
6908#define A6XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000
6909#define A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16
6910static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)
6799#define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000
6800#define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16
6801static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val)
6911{
6802{
6912 return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK1__MASK;
6803 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK;
6913}
6914#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
6915#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
6916static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
6917{
6918 return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
6919}
6920
6804}
6805#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
6806#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
6807static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
6808{
6809 return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
6810}
6811
6921#define REG_A6XX_HLSQ_CS_UNKNOWN_B998 0x0000b998
6812#define REG_A6XX_HLSQ_CS_CNTL_1 0x0000b998
6813#define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff
6814#define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0
6815static inline uint32_t A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)
6816{
6817 return ((val) << A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK;
6818}
6819#define A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE 0x00000100
6820#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200
6821#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9
6822static inline uint32_t A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)
6823{
6824 return ((val) << A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK;
6825}
6826#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400
6922
6923#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999
6924
6925#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a
6926
6927#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b
6928
6929#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0
6930
6931#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1
6827
6828#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999
6829
6830#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a
6831
6832#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b
6833
6834#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0
6835
6836#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1
6837#define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK 0xffffffff
6838#define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT 0
6839static inline uint32_t A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val)
6840{
6841 return ((val) << A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK;
6842}
6932
6933#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3
6934
6935static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
6936
6937static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
6938
6939#define REG_A6XX_HLSQ_DRAW_CMD 0x0000bb00

--- 81 unchanged lines hidden (view full) ---

7021}
7022
7023#define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00
7024
7025#define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01
7026
7027#define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04
7028
6843
6844#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3
6845
6846static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
6847
6848static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
6849
6850#define REG_A6XX_HLSQ_DRAW_CMD 0x0000bb00

--- 81 unchanged lines hidden (view full) ---

6932}
6933
6934#define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00
6935
6936#define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01
6937
6938#define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04
6939
6940#define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05
6941
6942#define REG_A6XX_HLSQ_UNKNOWN_BE08 0x0000be08
6943
6944static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; }
6945
7029#define REG_A6XX_CP_EVENT_START 0x0000d600
7030#define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff
7031#define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0
7032static inline uint32_t A6XX_CP_EVENT_START_STATE_ID(uint32_t val)
7033{
7034 return ((val) << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK;
7035}
7036

--- 93 unchanged lines hidden (view full) ---

7130#define REG_A6XX_TEX_SAMP_2 0x00000002
7131#define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK 0x00000003
7132#define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT 0
7133static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val)
7134{
7135 return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK;
7136}
7137#define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020
6946#define REG_A6XX_CP_EVENT_START 0x0000d600
6947#define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff
6948#define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0
6949static inline uint32_t A6XX_CP_EVENT_START_STATE_ID(uint32_t val)
6950{
6951 return ((val) << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK;
6952}
6953

--- 93 unchanged lines hidden (view full) ---

7047#define REG_A6XX_TEX_SAMP_2 0x00000002
7048#define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK 0x00000003
7049#define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT 0
7050static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val)
7051{
7052 return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK;
7053}
7054#define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020
7138#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xffffff80
7139#define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 7
7140static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
7055#define A6XX_TEX_SAMP_2_BCOLOR__MASK 0xffffff80
7056#define A6XX_TEX_SAMP_2_BCOLOR__SHIFT 7
7057static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR(uint32_t val)
7141{
7058{
7142 return ((val >> 7) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
7059 return ((val) << A6XX_TEX_SAMP_2_BCOLOR__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR__MASK;
7143}
7144
7145#define REG_A6XX_TEX_SAMP_3 0x00000003
7146
7147#define REG_A6XX_TEX_CONST_0 0x00000000
7148#define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
7149#define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0
7150static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val)

--- 539 unchanged lines hidden --- 		7060}
7061
7062#define REG_A6XX_TEX_SAMP_3 0x00000003
7063
7064#define REG_A6XX_TEX_CONST_0 0x00000000
7065#define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
7066#define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0
7067static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val)

--- 539 unchanged lines hidden ---