a5xx.xml.h (d0034a7a4ac7fae708146ac0059b9c47a1543f0d) a5xx.xml.h (cc4c26d4ae4e458669d46ff69f16ac0c74f7cd49)
1#ifndef A5XX_XML
2#define A5XX_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
1#ifndef A5XX_XML
2#define A5XX_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
11- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24
24
25Copyright (C) 2013-2020 by the following authors:
25Copyright (C) 2013-2021 by the following authors:
26- Rob Clark <robdclark@gmail.com> (robclark)
27- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
29Permission is hereby granted, free of charge, to any person obtaining
30a copy of this software and associated documentation files (the
31"Software"), to deal in the Software without restriction, including
32without limitation the rights to use, copy, modify, merge, publish,
33distribute, sublicense, and/or sell copies of the Software, and to

--- 1982 unchanged lines hidden (view full) ---

2016#define A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT 1
2017static inline uint32_t A5XX_RBBM_STATUS_CP_ME_BUSY(uint32_t val)
2018{
2019 return ((val) << A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_ME_BUSY__MASK;
2020}
2021#define A5XX_RBBM_STATUS_HI_BUSY 0x00000001
2022
2023#define REG_A5XX_RBBM_STATUS3 0x00000530
26- Rob Clark <robdclark@gmail.com> (robclark)
27- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
29Permission is hereby granted, free of charge, to any person obtaining
30a copy of this software and associated documentation files (the
31"Software"), to deal in the Software without restriction, including
32without limitation the rights to use, copy, modify, merge, publish,
33distribute, sublicense, and/or sell copies of the Software, and to

--- 1982 unchanged lines hidden (view full) ---

2016#define A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT 1
2017static inline uint32_t A5XX_RBBM_STATUS_CP_ME_BUSY(uint32_t val)
2018{
2019 return ((val) << A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_ME_BUSY__MASK;
2020}
2021#define A5XX_RBBM_STATUS_HI_BUSY 0x00000001
2022
2023#define REG_A5XX_RBBM_STATUS3 0x00000530
2024#define A5XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000
2024
2025#define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1
2026
2027#define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS 0x000004f0
2028
2029#define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS 0x000004f1
2030
2031#define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS 0x000004f3

--- 314 unchanged lines hidden (view full) ---

2346
2347#define REG_A5XX_VFD_PERFCTR_VFD_SEL_5 0x00000e55
2348
2349#define REG_A5XX_VFD_PERFCTR_VFD_SEL_6 0x00000e56
2350
2351#define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57
2352
2353#define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60
2025
2026#define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1
2027
2028#define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS 0x000004f0
2029
2030#define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS 0x000004f1
2031
2032#define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS 0x000004f3

--- 314 unchanged lines hidden (view full) ---

2347
2348#define REG_A5XX_VFD_PERFCTR_VFD_SEL_5 0x00000e55
2349
2350#define REG_A5XX_VFD_PERFCTR_VFD_SEL_6 0x00000e56
2351
2352#define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57
2353
2354#define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60
2355#define A5XX_VPC_DBG_ECO_CNTL_ALLFLATOPTDIS 0x00000400
2354
2355#define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61
2356
2357#define REG_A5XX_VPC_MODE_CNTL 0x00000e62
2358#define A5XX_VPC_MODE_CNTL_BINNING_PASS 0x00000001
2359
2360#define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64
2361

--- 441 unchanged lines hidden (view full) ---

2803
2804#define REG_A5XX_GPU_CS_ENABLE_REG 0x0000c520
2805
2806#define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557
2807
2808#define REG_A5XX_GRAS_CL_CNTL 0x0000e000
2809#define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040
2810
2356
2357#define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61
2358
2359#define REG_A5XX_VPC_MODE_CNTL 0x00000e62
2360#define A5XX_VPC_MODE_CNTL_BINNING_PASS 0x00000001
2361
2362#define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64
2363

--- 441 unchanged lines hidden (view full) ---

2805
2806#define REG_A5XX_GPU_CS_ENABLE_REG 0x0000c520
2807
2808#define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557
2809
2810#define REG_A5XX_GRAS_CL_CNTL 0x0000e000
2811#define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040
2812
2811#define REG_A5XX_UNKNOWN_E001 0x0000e001
2813#define REG_A5XX_GRAS_VS_CL_CNTL 0x0000e001
2814#define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
2815#define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0
2816static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)
2817{
2818 return ((val) << A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK;
2819}
2820#define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
2821#define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8
2822static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
2823{
2824 return ((val) << A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK;
2825}
2812
2813#define REG_A5XX_UNKNOWN_E004 0x0000e004
2814
2815#define REG_A5XX_GRAS_CNTL 0x0000e005
2816#define A5XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001
2817#define A5XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002
2818#define A5XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004
2819#define A5XX_GRAS_CNTL_SIZE 0x00000008

--- 520 unchanged lines hidden (view full) ---

3340static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val)
3341{
3342 return ((val) << A5XX_RB_BLEND_RED_SINT__SHIFT) & A5XX_RB_BLEND_RED_SINT__MASK;
3343}
3344#define A5XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
3345#define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16
3346static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val)
3347{
2826
2827#define REG_A5XX_UNKNOWN_E004 0x0000e004
2828
2829#define REG_A5XX_GRAS_CNTL 0x0000e005
2830#define A5XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001
2831#define A5XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002
2832#define A5XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004
2833#define A5XX_GRAS_CNTL_SIZE 0x00000008

--- 520 unchanged lines hidden (view full) ---

3354static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val)
3355{
3356 return ((val) << A5XX_RB_BLEND_RED_SINT__SHIFT) & A5XX_RB_BLEND_RED_SINT__MASK;
3357}
3358#define A5XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
3359#define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16
3360static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val)
3361{
3348 return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
3362 return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
3349}
3350
3351#define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1
3352#define A5XX_RB_BLEND_RED_F32__MASK 0xffffffff
3353#define A5XX_RB_BLEND_RED_F32__SHIFT 0
3354static inline uint32_t A5XX_RB_BLEND_RED_F32(float val)
3355{
3356 return ((fui(val)) << A5XX_RB_BLEND_RED_F32__SHIFT) & A5XX_RB_BLEND_RED_F32__MASK;

--- 11 unchanged lines hidden (view full) ---

3368static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val)
3369{
3370 return ((val) << A5XX_RB_BLEND_GREEN_SINT__SHIFT) & A5XX_RB_BLEND_GREEN_SINT__MASK;
3371}
3372#define A5XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
3373#define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
3374static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val)
3375{
3363}
3364
3365#define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1
3366#define A5XX_RB_BLEND_RED_F32__MASK 0xffffffff
3367#define A5XX_RB_BLEND_RED_F32__SHIFT 0
3368static inline uint32_t A5XX_RB_BLEND_RED_F32(float val)
3369{
3370 return ((fui(val)) << A5XX_RB_BLEND_RED_F32__SHIFT) & A5XX_RB_BLEND_RED_F32__MASK;

--- 11 unchanged lines hidden (view full) ---

3382static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val)
3383{
3384 return ((val) << A5XX_RB_BLEND_GREEN_SINT__SHIFT) & A5XX_RB_BLEND_GREEN_SINT__MASK;
3385}
3386#define A5XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
3387#define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
3388static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val)
3389{
3376 return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
3390 return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
3377}
3378
3379#define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3
3380#define A5XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
3381#define A5XX_RB_BLEND_GREEN_F32__SHIFT 0
3382static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val)
3383{
3384 return ((fui(val)) << A5XX_RB_BLEND_GREEN_F32__SHIFT) & A5XX_RB_BLEND_GREEN_F32__MASK;

--- 11 unchanged lines hidden (view full) ---

3396static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val)
3397{
3398 return ((val) << A5XX_RB_BLEND_BLUE_SINT__SHIFT) & A5XX_RB_BLEND_BLUE_SINT__MASK;
3399}
3400#define A5XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
3401#define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
3402static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val)
3403{
3391}
3392
3393#define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3
3394#define A5XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
3395#define A5XX_RB_BLEND_GREEN_F32__SHIFT 0
3396static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val)
3397{
3398 return ((fui(val)) << A5XX_RB_BLEND_GREEN_F32__SHIFT) & A5XX_RB_BLEND_GREEN_F32__MASK;

--- 11 unchanged lines hidden (view full) ---

3410static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val)
3411{
3412 return ((val) << A5XX_RB_BLEND_BLUE_SINT__SHIFT) & A5XX_RB_BLEND_BLUE_SINT__MASK;
3413}
3414#define A5XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
3415#define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
3416static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val)
3417{
3404 return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
3418 return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
3405}
3406
3407#define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5
3408#define A5XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
3409#define A5XX_RB_BLEND_BLUE_F32__SHIFT 0
3410static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val)
3411{
3412 return ((fui(val)) << A5XX_RB_BLEND_BLUE_F32__SHIFT) & A5XX_RB_BLEND_BLUE_F32__MASK;

--- 11 unchanged lines hidden (view full) ---

3424static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val)
3425{
3426 return ((val) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT) & A5XX_RB_BLEND_ALPHA_SINT__MASK;
3427}
3428#define A5XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
3429#define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
3430static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val)
3431{
3419}
3420
3421#define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5
3422#define A5XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
3423#define A5XX_RB_BLEND_BLUE_F32__SHIFT 0
3424static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val)
3425{
3426 return ((fui(val)) << A5XX_RB_BLEND_BLUE_F32__SHIFT) & A5XX_RB_BLEND_BLUE_F32__MASK;

--- 11 unchanged lines hidden (view full) ---

3438static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val)
3439{
3440 return ((val) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT) & A5XX_RB_BLEND_ALPHA_SINT__MASK;
3441}
3442#define A5XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
3443#define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
3444static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val)
3445{
3432 return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
3446 return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
3433}
3434
3435#define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7
3436#define A5XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
3437#define A5XX_RB_BLEND_ALPHA_F32__SHIFT 0
3438static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val)
3439{
3440 return ((fui(val)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT) & A5XX_RB_BLEND_ALPHA_F32__MASK;

--- 360 unchanged lines hidden (view full) ---

3801#define REG_A5XX_UNKNOWN_E293 0x0000e293
3802
3803static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
3804
3805static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
3806
3807#define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298
3808
3447}
3448
3449#define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7
3450#define A5XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
3451#define A5XX_RB_BLEND_ALPHA_F32__SHIFT 0
3452static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val)
3453{
3454 return ((fui(val)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT) & A5XX_RB_BLEND_ALPHA_F32__MASK;

--- 360 unchanged lines hidden (view full) ---

3815#define REG_A5XX_UNKNOWN_E293 0x0000e293
3816
3817static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
3818
3819static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
3820
3821#define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298
3822
3809#define REG_A5XX_UNKNOWN_E29A 0x0000e29a
3823#define REG_A5XX_VPC_CLIP_CNTL 0x0000e29a
3824#define A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
3825#define A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT 0
3826static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_MASK(uint32_t val)
3827{
3828 return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK;
3829}
3830#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
3831#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
3832static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
3833{
3834 return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
3835}
3836#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
3837#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
3838static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
3839{
3840 return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
3841}
3810
3811#define REG_A5XX_VPC_PACK 0x0000e29d
3812#define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff
3813#define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT 0
3814static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
3815{
3816 return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK;
3817}

--- 87 unchanged lines hidden (view full) ---

3905#define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000038
3906#define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT 3
3907static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
3908{
3909 return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK;
3910}
3911#define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE 0x00000040
3912
3842
3843#define REG_A5XX_VPC_PACK 0x0000e29d
3844#define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff
3845#define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT 0
3846static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
3847{
3848 return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK;
3849}

--- 87 unchanged lines hidden (view full) ---

3937#define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000038
3938#define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT 3
3939static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
3940{
3941 return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK;
3942}
3943#define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE 0x00000040
3944
3913#define REG_A5XX_UNKNOWN_E389 0x0000e389
3945#define REG_A5XX_PC_CLIP_CNTL 0x0000e389
3946#define A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
3947#define A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT 0
3948static inline uint32_t A5XX_PC_CLIP_CNTL_CLIP_MASK(uint32_t val)
3949{
3950 return ((val) << A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK;
3951}
3914
3915#define REG_A5XX_PC_RESTART_INDEX 0x0000e38c
3916
3917#define REG_A5XX_PC_GS_LAYERED 0x0000e38d
3918
3919#define REG_A5XX_PC_GS_PARAM 0x0000e38e
3920#define A5XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
3921#define A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0

--- 375 unchanged lines hidden (view full) ---

4297
4298#define REG_A5XX_UNKNOWN_E5C2 0x0000e5c2
4299
4300#define REG_A5XX_SP_FS_OBJ_START_LO 0x0000e5c3
4301
4302#define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4
4303
4304#define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9
3952
3953#define REG_A5XX_PC_RESTART_INDEX 0x0000e38c
3954
3955#define REG_A5XX_PC_GS_LAYERED 0x0000e38d
3956
3957#define REG_A5XX_PC_GS_PARAM 0x0000e38e
3958#define A5XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
3959#define A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0

--- 375 unchanged lines hidden (view full) ---

4335
4336#define REG_A5XX_UNKNOWN_E5C2 0x0000e5c2
4337
4338#define REG_A5XX_SP_FS_OBJ_START_LO 0x0000e5c3
4339
4340#define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4
4341
4342#define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9
4305#define A5XX_SP_BLEND_CNTL_ENABLED 0x00000001
4343#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
4344#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
4345static inline uint32_t A5XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
4346{
4347 return ((val) << A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;
4348}
4306#define A5XX_SP_BLEND_CNTL_UNK8 0x00000100
4307#define A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
4308
4309#define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca
4310#define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
4311#define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT 0
4312static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val)
4313{

--- 873 unchanged lines hidden (view full) ---

5187#define A5XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
5188#define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
5189static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val)
5190{
5191 return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK;
5192}
5193
5194#define REG_A5XX_TEX_SAMP_2 0x00000002
4349#define A5XX_SP_BLEND_CNTL_UNK8 0x00000100
4350#define A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
4351
4352#define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca
4353#define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
4354#define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT 0
4355static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val)
4356{

--- 873 unchanged lines hidden (view full) ---

5230#define A5XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
5231#define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
5232static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val)
5233{
5234 return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK;
5235}
5236
5237#define REG_A5XX_TEX_SAMP_2 0x00000002
5195#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xfffffff0
5196#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 4
5238#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xffffff80
5239#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 7
5197static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
5198{
5199 return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
5200}
5201
5202#define REG_A5XX_TEX_SAMP_3 0x00000003
5203
5204#define REG_A5XX_TEX_CONST_0 0x00000000

--- 63 unchanged lines hidden (view full) ---

5268#define A5XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000
5269#define A5XX_TEX_CONST_1_HEIGHT__SHIFT 15
5270static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val)
5271{
5272 return ((val) << A5XX_TEX_CONST_1_HEIGHT__SHIFT) & A5XX_TEX_CONST_1_HEIGHT__MASK;
5273}
5274
5275#define REG_A5XX_TEX_CONST_2 0x00000002
5240static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
5241{
5242 return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
5243}
5244
5245#define REG_A5XX_TEX_SAMP_3 0x00000003
5246
5247#define REG_A5XX_TEX_CONST_0 0x00000000

--- 63 unchanged lines hidden (view full) ---

5311#define A5XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000
5312#define A5XX_TEX_CONST_1_HEIGHT__SHIFT 15
5313static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val)
5314{
5315 return ((val) << A5XX_TEX_CONST_1_HEIGHT__SHIFT) & A5XX_TEX_CONST_1_HEIGHT__MASK;
5316}
5317
5318#define REG_A5XX_TEX_CONST_2 0x00000002
5319#define A5XX_TEX_CONST_2_UNK4 0x00000010
5276#define A5XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
5277#define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
5278static inline uint32_t A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
5279{
5280 return ((val) << A5XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A5XX_TEX_CONST_2_PITCHALIGN__MASK;
5281}
5282#define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
5283#define A5XX_TEX_CONST_2_PITCH__SHIFT 7
5284static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val)
5285{
5286 return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK;
5287}
5288#define A5XX_TEX_CONST_2_TYPE__MASK 0x60000000
5289#define A5XX_TEX_CONST_2_TYPE__SHIFT 29
5290static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val)
5291{
5292 return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK;
5293}
5320#define A5XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
5321#define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
5322static inline uint32_t A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
5323{
5324 return ((val) << A5XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A5XX_TEX_CONST_2_PITCHALIGN__MASK;
5325}
5326#define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
5327#define A5XX_TEX_CONST_2_PITCH__SHIFT 7
5328static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val)
5329{
5330 return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK;
5331}
5332#define A5XX_TEX_CONST_2_TYPE__MASK 0x60000000
5333#define A5XX_TEX_CONST_2_TYPE__SHIFT 29
5334static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val)
5335{
5336 return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK;
5337}
5338#define A5XX_TEX_CONST_2_UNK31 0x80000000
5294
5295#define REG_A5XX_TEX_CONST_3 0x00000003
5296#define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
5297#define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
5298static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
5299{
5300 return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK;
5301}

--- 137 unchanged lines hidden --- 		5339
5340#define REG_A5XX_TEX_CONST_3 0x00000003
5341#define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
5342#define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
5343static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
5344{
5345 return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK;
5346}

--- 137 unchanged lines hidden ---