a4xx.xml.h (e5451c8f8330e03ad3cfa16048b4daf961af434f) a4xx.xml.h (a2272e48eef02869dc3fa031720f36dd4cb05e4f)
1#ifndef A4XX_XML
2#define A4XX_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
1#ifndef A4XX_XML
2#define A4XX_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31)
16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48)
18- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
19
18- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
19
20Copyright (C) 2013-2015 by the following authors:
20Copyright (C) 2013-2016 by the following authors:
21- Rob Clark <robdclark@gmail.com> (robclark)
21- Rob Clark <robdclark@gmail.com> (robclark)
22- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
22
23Permission is hereby granted, free of charge, to any person obtaining
24a copy of this software and associated documentation files (the
25"Software"), to deal in the Software without restriction, including
26without limitation the rights to use, copy, modify, merge, publish,
27distribute, sublicense, and/or sell copies of the Software, and to
28permit persons to whom the Software is furnished to do so, subject to
29the following conditions:

--- 12 unchanged lines hidden (view full) ---

42*/
43
44
45enum a4xx_color_fmt {
46 RB4_A8_UNORM = 1,
47 RB4_R8_UNORM = 2,
48 RB4_R4G4B4A4_UNORM = 8,
49 RB4_R5G5B5A1_UNORM = 10,
23
24Permission is hereby granted, free of charge, to any person obtaining
25a copy of this software and associated documentation files (the
26"Software"), to deal in the Software without restriction, including
27without limitation the rights to use, copy, modify, merge, publish,
28distribute, sublicense, and/or sell copies of the Software, and to
29permit persons to whom the Software is furnished to do so, subject to
30the following conditions:

--- 12 unchanged lines hidden (view full) ---

43*/
44
45
46enum a4xx_color_fmt {
47 RB4_A8_UNORM = 1,
48 RB4_R8_UNORM = 2,
49 RB4_R4G4B4A4_UNORM = 8,
50 RB4_R5G5B5A1_UNORM = 10,
50 RB4_R5G6R5_UNORM = 14,
51 RB4_R5G6B5_UNORM = 14,
51 RB4_R8G8_UNORM = 15,
52 RB4_R8G8_SNORM = 16,
53 RB4_R8G8_UINT = 17,
54 RB4_R8G8_SINT = 18,
52 RB4_R8G8_UNORM = 15,
53 RB4_R8G8_SNORM = 16,
54 RB4_R8G8_UINT = 17,
55 RB4_R8G8_SINT = 18,
56 RB4_R16_UNORM = 19,
57 RB4_R16_SNORM = 20,
55 RB4_R16_FLOAT = 21,
56 RB4_R16_UINT = 22,
57 RB4_R16_SINT = 23,
58 RB4_R8G8B8_UNORM = 25,
59 RB4_R8G8B8A8_UNORM = 26,
60 RB4_R8G8B8A8_SNORM = 28,
61 RB4_R8G8B8A8_UINT = 29,
62 RB4_R8G8B8A8_SINT = 30,
63 RB4_R10G10B10A2_UNORM = 31,
64 RB4_R10G10B10A2_UINT = 34,
65 RB4_R11G11B10_FLOAT = 39,
58 RB4_R16_FLOAT = 21,
59 RB4_R16_UINT = 22,
60 RB4_R16_SINT = 23,
61 RB4_R8G8B8_UNORM = 25,
62 RB4_R8G8B8A8_UNORM = 26,
63 RB4_R8G8B8A8_SNORM = 28,
64 RB4_R8G8B8A8_UINT = 29,
65 RB4_R8G8B8A8_SINT = 30,
66 RB4_R10G10B10A2_UNORM = 31,
67 RB4_R10G10B10A2_UINT = 34,
68 RB4_R11G11B10_FLOAT = 39,
69 RB4_R16G16_UNORM = 40,
70 RB4_R16G16_SNORM = 41,
66 RB4_R16G16_FLOAT = 42,
67 RB4_R16G16_UINT = 43,
68 RB4_R16G16_SINT = 44,
69 RB4_R32_FLOAT = 45,
70 RB4_R32_UINT = 46,
71 RB4_R32_SINT = 47,
71 RB4_R16G16_FLOAT = 42,
72 RB4_R16G16_UINT = 43,
73 RB4_R16G16_SINT = 44,
74 RB4_R32_FLOAT = 45,
75 RB4_R32_UINT = 46,
76 RB4_R32_SINT = 47,
77 RB4_R16G16B16A16_UNORM = 52,
78 RB4_R16G16B16A16_SNORM = 53,
72 RB4_R16G16B16A16_FLOAT = 54,
73 RB4_R16G16B16A16_UINT = 55,
74 RB4_R16G16B16A16_SINT = 56,
75 RB4_R32G32_FLOAT = 57,
76 RB4_R32G32_UINT = 58,
77 RB4_R32G32_SINT = 59,
78 RB4_R32G32B32A32_FLOAT = 60,
79 RB4_R32G32B32A32_UINT = 61,

--- 21 unchanged lines hidden (view full) ---

101 VFMT4_16_FLOAT = 5,
102 VFMT4_16_16_FLOAT = 6,
103 VFMT4_16_16_16_FLOAT = 7,
104 VFMT4_16_16_16_16_FLOAT = 8,
105 VFMT4_32_FIXED = 9,
106 VFMT4_32_32_FIXED = 10,
107 VFMT4_32_32_32_FIXED = 11,
108 VFMT4_32_32_32_32_FIXED = 12,
79 RB4_R16G16B16A16_FLOAT = 54,
80 RB4_R16G16B16A16_UINT = 55,
81 RB4_R16G16B16A16_SINT = 56,
82 RB4_R32G32_FLOAT = 57,
83 RB4_R32G32_UINT = 58,
84 RB4_R32G32_SINT = 59,
85 RB4_R32G32B32A32_FLOAT = 60,
86 RB4_R32G32B32A32_UINT = 61,

--- 21 unchanged lines hidden (view full) ---

108 VFMT4_16_FLOAT = 5,
109 VFMT4_16_16_FLOAT = 6,
110 VFMT4_16_16_16_FLOAT = 7,
111 VFMT4_16_16_16_16_FLOAT = 8,
112 VFMT4_32_FIXED = 9,
113 VFMT4_32_32_FIXED = 10,
114 VFMT4_32_32_32_FIXED = 11,
115 VFMT4_32_32_32_32_FIXED = 12,
116 VFMT4_11_11_10_FLOAT = 13,
109 VFMT4_16_SINT = 16,
110 VFMT4_16_16_SINT = 17,
111 VFMT4_16_16_16_SINT = 18,
112 VFMT4_16_16_16_16_SINT = 19,
113 VFMT4_16_UINT = 20,
114 VFMT4_16_16_UINT = 21,
115 VFMT4_16_16_16_UINT = 22,
116 VFMT4_16_16_16_16_UINT = 23,

--- 24 unchanged lines hidden (view full) ---

141 VFMT4_8_SINT = 48,
142 VFMT4_8_8_SINT = 49,
143 VFMT4_8_8_8_SINT = 50,
144 VFMT4_8_8_8_8_SINT = 51,
145 VFMT4_8_SNORM = 52,
146 VFMT4_8_8_SNORM = 53,
147 VFMT4_8_8_8_SNORM = 54,
148 VFMT4_8_8_8_8_SNORM = 55,
117 VFMT4_16_SINT = 16,
118 VFMT4_16_16_SINT = 17,
119 VFMT4_16_16_16_SINT = 18,
120 VFMT4_16_16_16_16_SINT = 19,
121 VFMT4_16_UINT = 20,
122 VFMT4_16_16_UINT = 21,
123 VFMT4_16_16_16_UINT = 22,
124 VFMT4_16_16_16_16_UINT = 23,

--- 24 unchanged lines hidden (view full) ---

149 VFMT4_8_SINT = 48,
150 VFMT4_8_8_SINT = 49,
151 VFMT4_8_8_8_SINT = 50,
152 VFMT4_8_8_8_8_SINT = 51,
153 VFMT4_8_SNORM = 52,
154 VFMT4_8_8_SNORM = 53,
155 VFMT4_8_8_8_SNORM = 54,
156 VFMT4_8_8_8_8_SNORM = 55,
149 VFMT4_10_10_10_2_UINT = 60,
150 VFMT4_10_10_10_2_UNORM = 61,
151 VFMT4_10_10_10_2_SINT = 62,
152 VFMT4_10_10_10_2_SNORM = 63,
157 VFMT4_10_10_10_2_UINT = 56,
158 VFMT4_10_10_10_2_UNORM = 57,
159 VFMT4_10_10_10_2_SINT = 58,
160 VFMT4_10_10_10_2_SNORM = 59,
161 VFMT4_2_10_10_10_UINT = 60,
162 VFMT4_2_10_10_10_UNORM = 61,
163 VFMT4_2_10_10_10_SINT = 62,
164 VFMT4_2_10_10_10_SNORM = 63,
153};
154
155enum a4xx_tex_fmt {
165};
166
167enum a4xx_tex_fmt {
156 TFMT4_5_6_5_UNORM = 11,
157 TFMT4_5_5_5_1_UNORM = 10,
158 TFMT4_4_4_4_4_UNORM = 8,
159 TFMT4_X8Z24_UNORM = 71,
160 TFMT4_10_10_10_2_UNORM = 33,
161 TFMT4_A8_UNORM = 3,
168 TFMT4_A8_UNORM = 3,
162 TFMT4_L8_A8_UNORM = 13,
163 TFMT4_8_UNORM = 4,
169 TFMT4_8_UNORM = 4,
164 TFMT4_8_8_UNORM = 14,
165 TFMT4_8_8_8_8_UNORM = 28,
166 TFMT4_8_SNORM = 5,
170 TFMT4_8_SNORM = 5,
167 TFMT4_8_8_SNORM = 15,
168 TFMT4_8_8_8_8_SNORM = 29,
169 TFMT4_8_UINT = 6,
171 TFMT4_8_UINT = 6,
170 TFMT4_8_8_UINT = 16,
171 TFMT4_8_8_8_8_UINT = 30,
172 TFMT4_8_SINT = 7,
172 TFMT4_8_SINT = 7,
173 TFMT4_4_4_4_4_UNORM = 8,
174 TFMT4_5_5_5_1_UNORM = 9,
175 TFMT4_5_6_5_UNORM = 11,
176 TFMT4_L8_A8_UNORM = 13,
177 TFMT4_8_8_UNORM = 14,
178 TFMT4_8_8_SNORM = 15,
179 TFMT4_8_8_UINT = 16,
173 TFMT4_8_8_SINT = 17,
180 TFMT4_8_8_SINT = 17,
174 TFMT4_8_8_8_8_SINT = 31,
181 TFMT4_16_UNORM = 18,
182 TFMT4_16_SNORM = 19,
183 TFMT4_16_FLOAT = 20,
175 TFMT4_16_UINT = 21,
184 TFMT4_16_UINT = 21,
176 TFMT4_16_16_UINT = 41,
177 TFMT4_16_16_16_16_UINT = 54,
178 TFMT4_16_SINT = 22,
185 TFMT4_16_SINT = 22,
186 TFMT4_8_8_8_8_UNORM = 28,
187 TFMT4_8_8_8_8_SNORM = 29,
188 TFMT4_8_8_8_8_UINT = 30,
189 TFMT4_8_8_8_8_SINT = 31,
190 TFMT4_9_9_9_E5_FLOAT = 32,
191 TFMT4_10_10_10_2_UNORM = 33,
192 TFMT4_10_10_10_2_UINT = 34,
193 TFMT4_11_11_10_FLOAT = 37,
194 TFMT4_16_16_UNORM = 38,
195 TFMT4_16_16_SNORM = 39,
196 TFMT4_16_16_FLOAT = 40,
197 TFMT4_16_16_UINT = 41,
179 TFMT4_16_16_SINT = 42,
198 TFMT4_16_16_SINT = 42,
180 TFMT4_16_16_16_16_SINT = 55,
199 TFMT4_32_FLOAT = 43,
181 TFMT4_32_UINT = 44,
200 TFMT4_32_UINT = 44,
182 TFMT4_32_32_UINT = 57,
183 TFMT4_32_32_32_32_UINT = 64,
184 TFMT4_32_SINT = 45,
201 TFMT4_32_SINT = 45,
185 TFMT4_32_32_SINT = 58,
186 TFMT4_32_32_32_32_SINT = 65,
187 TFMT4_16_FLOAT = 20,
188 TFMT4_16_16_FLOAT = 40,
202 TFMT4_16_16_16_16_UNORM = 51,
203 TFMT4_16_16_16_16_SNORM = 52,
189 TFMT4_16_16_16_16_FLOAT = 53,
204 TFMT4_16_16_16_16_FLOAT = 53,
190 TFMT4_32_FLOAT = 43,
205 TFMT4_16_16_16_16_UINT = 54,
206 TFMT4_16_16_16_16_SINT = 55,
191 TFMT4_32_32_FLOAT = 56,
207 TFMT4_32_32_FLOAT = 56,
208 TFMT4_32_32_UINT = 57,
209 TFMT4_32_32_SINT = 58,
210 TFMT4_32_32_32_FLOAT = 59,
211 TFMT4_32_32_32_UINT = 60,
212 TFMT4_32_32_32_SINT = 61,
192 TFMT4_32_32_32_32_FLOAT = 63,
213 TFMT4_32_32_32_32_FLOAT = 63,
193 TFMT4_9_9_9_E5_FLOAT = 32,
194 TFMT4_11_11_10_FLOAT = 37,
214 TFMT4_32_32_32_32_UINT = 64,
215 TFMT4_32_32_32_32_SINT = 65,
216 TFMT4_X8Z24_UNORM = 71,
217 TFMT4_DXT1 = 86,
218 TFMT4_DXT3 = 87,
219 TFMT4_DXT5 = 88,
220 TFMT4_RGTC1_UNORM = 90,
221 TFMT4_RGTC1_SNORM = 91,
222 TFMT4_RGTC2_UNORM = 94,
223 TFMT4_RGTC2_SNORM = 95,
224 TFMT4_BPTC_UFLOAT = 97,
225 TFMT4_BPTC_FLOAT = 98,
226 TFMT4_BPTC = 99,
195 TFMT4_ATC_RGB = 100,
196 TFMT4_ATC_RGBA_EXPLICIT = 101,
197 TFMT4_ATC_RGBA_INTERPOLATED = 102,
198 TFMT4_ETC2_RG11_UNORM = 103,
199 TFMT4_ETC2_RG11_SNORM = 104,
200 TFMT4_ETC2_R11_UNORM = 105,
201 TFMT4_ETC2_R11_SNORM = 106,
202 TFMT4_ETC1 = 107,

--- 32 unchanged lines hidden (view full) ---

235};
236
237enum a4xx_tess_spacing {
238 EQUAL_SPACING = 0,
239 ODD_SPACING = 2,
240 EVEN_SPACING = 3,
241};
242
227 TFMT4_ATC_RGB = 100,
228 TFMT4_ATC_RGBA_EXPLICIT = 101,
229 TFMT4_ATC_RGBA_INTERPOLATED = 102,
230 TFMT4_ETC2_RG11_UNORM = 103,
231 TFMT4_ETC2_RG11_SNORM = 104,
232 TFMT4_ETC2_R11_UNORM = 105,
233 TFMT4_ETC2_R11_SNORM = 106,
234 TFMT4_ETC1 = 107,

--- 32 unchanged lines hidden (view full) ---

267};
268
269enum a4xx_tess_spacing {
270 EQUAL_SPACING = 0,
271 ODD_SPACING = 2,
272 EVEN_SPACING = 3,
273};
274
275enum a4xx_ccu_perfcounter_select {
276 CCU_BUSY_CYCLES = 0,
277 CCU_RB_DEPTH_RETURN_STALL = 2,
278 CCU_RB_COLOR_RETURN_STALL = 3,
279 CCU_DEPTH_BLOCKS = 6,
280 CCU_COLOR_BLOCKS = 7,
281 CCU_DEPTH_BLOCK_HIT = 8,
282 CCU_COLOR_BLOCK_HIT = 9,
283 CCU_DEPTH_FLAG1_COUNT = 10,
284 CCU_DEPTH_FLAG2_COUNT = 11,
285 CCU_DEPTH_FLAG3_COUNT = 12,
286 CCU_DEPTH_FLAG4_COUNT = 13,
287 CCU_COLOR_FLAG1_COUNT = 14,
288 CCU_COLOR_FLAG2_COUNT = 15,
289 CCU_COLOR_FLAG3_COUNT = 16,
290 CCU_COLOR_FLAG4_COUNT = 17,
291 CCU_PARTIAL_BLOCK_READ = 18,
292};
293
294enum a4xx_cp_perfcounter_select {
295 CP_ALWAYS_COUNT = 0,
296 CP_BUSY = 1,
297 CP_PFP_IDLE = 2,
298 CP_PFP_BUSY_WORKING = 3,
299 CP_PFP_STALL_CYCLES_ANY = 4,
300 CP_PFP_STARVE_CYCLES_ANY = 5,
301 CP_PFP_STARVED_PER_LOAD_ADDR = 6,
302 CP_PFP_STALLED_PER_STORE_ADDR = 7,
303 CP_PFP_PC_PROFILE = 8,
304 CP_PFP_MATCH_PM4_PKT_PROFILE = 9,
305 CP_PFP_COND_INDIRECT_DISCARDED = 10,
306 CP_LONG_RESUMPTIONS = 11,
307 CP_RESUME_CYCLES = 12,
308 CP_RESUME_TO_BOUNDARY_CYCLES = 13,
309 CP_LONG_PREEMPTIONS = 14,
310 CP_PREEMPT_CYCLES = 15,
311 CP_PREEMPT_TO_BOUNDARY_CYCLES = 16,
312 CP_ME_FIFO_EMPTY_PFP_IDLE = 17,
313 CP_ME_FIFO_EMPTY_PFP_BUSY = 18,
314 CP_ME_FIFO_NOT_EMPTY_NOT_FULL = 19,
315 CP_ME_FIFO_FULL_ME_BUSY = 20,
316 CP_ME_FIFO_FULL_ME_NON_WORKING = 21,
317 CP_ME_WAITING_FOR_PACKETS = 22,
318 CP_ME_BUSY_WORKING = 23,
319 CP_ME_STARVE_CYCLES_ANY = 24,
320 CP_ME_STARVE_CYCLES_PER_PROFILE = 25,
321 CP_ME_STALL_CYCLES_PER_PROFILE = 26,
322 CP_ME_PC_PROFILE = 27,
323 CP_RCIU_FIFO_EMPTY = 28,
324 CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL = 29,
325 CP_RCIU_FIFO_FULL = 30,
326 CP_RCIU_FIFO_FULL_NO_CONTEXT = 31,
327 CP_RCIU_FIFO_FULL_AHB_MASTER = 32,
328 CP_RCIU_FIFO_FULL_OTHER = 33,
329 CP_AHB_IDLE = 34,
330 CP_AHB_STALL_ON_GRANT_NO_SPLIT = 35,
331 CP_AHB_STALL_ON_GRANT_SPLIT = 36,
332 CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE = 37,
333 CP_AHB_BUSY_WORKING = 38,
334 CP_AHB_BUSY_STALL_ON_HRDY = 39,
335 CP_AHB_BUSY_STALL_ON_HRDY_PROFILE = 40,
336};
337
338enum a4xx_gras_ras_perfcounter_select {
339 RAS_SUPER_TILES = 0,
340 RAS_8X8_TILES = 1,
341 RAS_4X4_TILES = 2,
342 RAS_BUSY_CYCLES = 3,
343 RAS_STALL_CYCLES_BY_RB = 4,
344 RAS_STALL_CYCLES_BY_VSC = 5,
345 RAS_STARVE_CYCLES_BY_TSE = 6,
346 RAS_SUPERTILE_CYCLES = 7,
347 RAS_TILE_CYCLES = 8,
348 RAS_FULLY_COVERED_SUPER_TILES = 9,
349 RAS_FULLY_COVERED_8X8_TILES = 10,
350 RAS_4X4_PRIM = 11,
351 RAS_8X4_4X8_PRIM = 12,
352 RAS_8X8_PRIM = 13,
353};
354
355enum a4xx_gras_tse_perfcounter_select {
356 TSE_INPUT_PRIM = 0,
357 TSE_INPUT_NULL_PRIM = 1,
358 TSE_TRIVAL_REJ_PRIM = 2,
359 TSE_CLIPPED_PRIM = 3,
360 TSE_NEW_PRIM = 4,
361 TSE_ZERO_AREA_PRIM = 5,
362 TSE_FACENESS_CULLED_PRIM = 6,
363 TSE_ZERO_PIXEL_PRIM = 7,
364 TSE_OUTPUT_NULL_PRIM = 8,
365 TSE_OUTPUT_VISIBLE_PRIM = 9,
366 TSE_PRE_CLIP_PRIM = 10,
367 TSE_POST_CLIP_PRIM = 11,
368 TSE_BUSY_CYCLES = 12,
369 TSE_PC_STARVE = 13,
370 TSE_RAS_STALL = 14,
371 TSE_STALL_BARYPLANE_FIFO_FULL = 15,
372 TSE_STALL_ZPLANE_FIFO_FULL = 16,
373};
374
375enum a4xx_hlsq_perfcounter_select {
376 HLSQ_SP_VS_STAGE_CONSTANT = 0,
377 HLSQ_SP_VS_STAGE_INSTRUCTIONS = 1,
378 HLSQ_SP_FS_STAGE_CONSTANT = 2,
379 HLSQ_SP_FS_STAGE_INSTRUCTIONS = 3,
380 HLSQ_TP_STATE = 4,
381 HLSQ_QUADS = 5,
382 HLSQ_PIXELS = 6,
383 HLSQ_VERTICES = 7,
384 HLSQ_SP_VS_STAGE_DATA_BYTES = 13,
385 HLSQ_SP_FS_STAGE_DATA_BYTES = 14,
386 HLSQ_BUSY_CYCLES = 15,
387 HLSQ_STALL_CYCLES_SP_STATE = 16,
388 HLSQ_STALL_CYCLES_SP_VS_STAGE = 17,
389 HLSQ_STALL_CYCLES_SP_FS_STAGE = 18,
390 HLSQ_STALL_CYCLES_UCHE = 19,
391 HLSQ_RBBM_LOAD_CYCLES = 20,
392 HLSQ_DI_TO_VS_START_SP = 21,
393 HLSQ_DI_TO_FS_START_SP = 22,
394 HLSQ_VS_STAGE_START_TO_DONE_SP = 23,
395 HLSQ_FS_STAGE_START_TO_DONE_SP = 24,
396 HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE = 25,
397 HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE = 26,
398 HLSQ_UCHE_LATENCY_CYCLES = 27,
399 HLSQ_UCHE_LATENCY_COUNT = 28,
400 HLSQ_STARVE_CYCLES_VFD = 29,
401};
402
403enum a4xx_pc_perfcounter_select {
404 PC_VIS_STREAMS_LOADED = 0,
405 PC_VPC_PRIMITIVES = 2,
406 PC_DEAD_PRIM = 3,
407 PC_LIVE_PRIM = 4,
408 PC_DEAD_DRAWCALLS = 5,
409 PC_LIVE_DRAWCALLS = 6,
410 PC_VERTEX_MISSES = 7,
411 PC_STALL_CYCLES_VFD = 9,
412 PC_STALL_CYCLES_TSE = 10,
413 PC_STALL_CYCLES_UCHE = 11,
414 PC_WORKING_CYCLES = 12,
415 PC_IA_VERTICES = 13,
416 PC_GS_PRIMITIVES = 14,
417 PC_HS_INVOCATIONS = 15,
418 PC_DS_INVOCATIONS = 16,
419 PC_DS_PRIMITIVES = 17,
420 PC_STARVE_CYCLES_FOR_INDEX = 20,
421 PC_STARVE_CYCLES_FOR_TESS_FACTOR = 21,
422 PC_STARVE_CYCLES_FOR_VIZ_STREAM = 22,
423 PC_STALL_CYCLES_TESS = 23,
424 PC_STARVE_CYCLES_FOR_POSITION = 24,
425 PC_MODE0_DRAWCALL = 25,
426 PC_MODE1_DRAWCALL = 26,
427 PC_MODE2_DRAWCALL = 27,
428 PC_MODE3_DRAWCALL = 28,
429 PC_MODE4_DRAWCALL = 29,
430 PC_PREDICATED_DEAD_DRAWCALL = 30,
431 PC_STALL_CYCLES_BY_TSE_ONLY = 31,
432 PC_STALL_CYCLES_BY_VPC_ONLY = 32,
433 PC_VPC_POS_DATA_TRANSACTION = 33,
434 PC_BUSY_CYCLES = 34,
435 PC_STARVE_CYCLES_DI = 35,
436 PC_STALL_CYCLES_VPC = 36,
437 TESS_WORKING_CYCLES = 37,
438 TESS_NUM_CYCLES_SETUP_WORKING = 38,
439 TESS_NUM_CYCLES_PTGEN_WORKING = 39,
440 TESS_NUM_CYCLES_CONNGEN_WORKING = 40,
441 TESS_BUSY_CYCLES = 41,
442 TESS_STARVE_CYCLES_PC = 42,
443 TESS_STALL_CYCLES_PC = 43,
444};
445
446enum a4xx_pwr_perfcounter_select {
447 PWR_CORE_CLOCK_CYCLES = 0,
448 PWR_BUSY_CLOCK_CYCLES = 1,
449};
450
451enum a4xx_rb_perfcounter_select {
452 RB_BUSY_CYCLES = 0,
453 RB_BUSY_CYCLES_BINNING = 1,
454 RB_BUSY_CYCLES_RENDERING = 2,
455 RB_BUSY_CYCLES_RESOLVE = 3,
456 RB_STARVE_CYCLES_BY_SP = 4,
457 RB_STARVE_CYCLES_BY_RAS = 5,
458 RB_STARVE_CYCLES_BY_MARB = 6,
459 RB_STALL_CYCLES_BY_MARB = 7,
460 RB_STALL_CYCLES_BY_HLSQ = 8,
461 RB_RB_RB_MARB_DATA = 9,
462 RB_SP_RB_QUAD = 10,
463 RB_RAS_RB_Z_QUADS = 11,
464 RB_GMEM_CH0_READ = 12,
465 RB_GMEM_CH1_READ = 13,
466 RB_GMEM_CH0_WRITE = 14,
467 RB_GMEM_CH1_WRITE = 15,
468 RB_CP_CONTEXT_DONE = 16,
469 RB_CP_CACHE_FLUSH = 17,
470 RB_CP_ZPASS_DONE = 18,
471 RB_STALL_FIFO0_FULL = 19,
472 RB_STALL_FIFO1_FULL = 20,
473 RB_STALL_FIFO2_FULL = 21,
474 RB_STALL_FIFO3_FULL = 22,
475 RB_RB_HLSQ_TRANSACTIONS = 23,
476 RB_Z_READ = 24,
477 RB_Z_WRITE = 25,
478 RB_C_READ = 26,
479 RB_C_WRITE = 27,
480 RB_C_READ_LATENCY = 28,
481 RB_Z_READ_LATENCY = 29,
482 RB_STALL_BY_UCHE = 30,
483 RB_MARB_UCHE_TRANSACTIONS = 31,
484 RB_CACHE_STALL_MISS = 32,
485 RB_CACHE_STALL_FIFO_FULL = 33,
486 RB_8BIT_BLENDER_UNITS_ACTIVE = 34,
487 RB_16BIT_BLENDER_UNITS_ACTIVE = 35,
488 RB_SAMPLER_UNITS_ACTIVE = 36,
489 RB_TOTAL_PASS = 38,
490 RB_Z_PASS = 39,
491 RB_Z_FAIL = 40,
492 RB_S_FAIL = 41,
493 RB_POWER0 = 42,
494 RB_POWER1 = 43,
495 RB_POWER2 = 44,
496 RB_POWER3 = 45,
497 RB_POWER4 = 46,
498 RB_POWER5 = 47,
499 RB_POWER6 = 48,
500 RB_POWER7 = 49,
501};
502
503enum a4xx_rbbm_perfcounter_select {
504 RBBM_ALWAYS_ON = 0,
505 RBBM_VBIF_BUSY = 1,
506 RBBM_TSE_BUSY = 2,
507 RBBM_RAS_BUSY = 3,
508 RBBM_PC_DCALL_BUSY = 4,
509 RBBM_PC_VSD_BUSY = 5,
510 RBBM_VFD_BUSY = 6,
511 RBBM_VPC_BUSY = 7,
512 RBBM_UCHE_BUSY = 8,
513 RBBM_VSC_BUSY = 9,
514 RBBM_HLSQ_BUSY = 10,
515 RBBM_ANY_RB_BUSY = 11,
516 RBBM_ANY_TPL1_BUSY = 12,
517 RBBM_ANY_SP_BUSY = 13,
518 RBBM_ANY_MARB_BUSY = 14,
519 RBBM_ANY_ARB_BUSY = 15,
520 RBBM_AHB_STATUS_BUSY = 16,
521 RBBM_AHB_STATUS_STALLED = 17,
522 RBBM_AHB_STATUS_TXFR = 18,
523 RBBM_AHB_STATUS_TXFR_SPLIT = 19,
524 RBBM_AHB_STATUS_TXFR_ERROR = 20,
525 RBBM_AHB_STATUS_LONG_STALL = 21,
526 RBBM_STATUS_MASKED = 22,
527 RBBM_CP_BUSY_GFX_CORE_IDLE = 23,
528 RBBM_TESS_BUSY = 24,
529 RBBM_COM_BUSY = 25,
530 RBBM_DCOM_BUSY = 32,
531 RBBM_ANY_CCU_BUSY = 33,
532 RBBM_DPM_BUSY = 34,
533};
534
535enum a4xx_sp_perfcounter_select {
536 SP_LM_LOAD_INSTRUCTIONS = 0,
537 SP_LM_STORE_INSTRUCTIONS = 1,
538 SP_LM_ATOMICS = 2,
539 SP_GM_LOAD_INSTRUCTIONS = 3,
540 SP_GM_STORE_INSTRUCTIONS = 4,
541 SP_GM_ATOMICS = 5,
542 SP_VS_STAGE_TEX_INSTRUCTIONS = 6,
543 SP_VS_STAGE_CFLOW_INSTRUCTIONS = 7,
544 SP_VS_STAGE_EFU_INSTRUCTIONS = 8,
545 SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 9,
546 SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 10,
547 SP_FS_STAGE_TEX_INSTRUCTIONS = 11,
548 SP_FS_STAGE_CFLOW_INSTRUCTIONS = 12,
549 SP_FS_STAGE_EFU_INSTRUCTIONS = 13,
550 SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 14,
551 SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 15,
552 SP_VS_INSTRUCTIONS = 17,
553 SP_FS_INSTRUCTIONS = 18,
554 SP_ADDR_LOCK_COUNT = 19,
555 SP_UCHE_READ_TRANS = 20,
556 SP_UCHE_WRITE_TRANS = 21,
557 SP_EXPORT_VPC_TRANS = 22,
558 SP_EXPORT_RB_TRANS = 23,
559 SP_PIXELS_KILLED = 24,
560 SP_ICL1_REQUESTS = 25,
561 SP_ICL1_MISSES = 26,
562 SP_ICL0_REQUESTS = 27,
563 SP_ICL0_MISSES = 28,
564 SP_ALU_WORKING_CYCLES = 29,
565 SP_EFU_WORKING_CYCLES = 30,
566 SP_STALL_CYCLES_BY_VPC = 31,
567 SP_STALL_CYCLES_BY_TP = 32,
568 SP_STALL_CYCLES_BY_UCHE = 33,
569 SP_STALL_CYCLES_BY_RB = 34,
570 SP_BUSY_CYCLES = 35,
571 SP_HS_INSTRUCTIONS = 36,
572 SP_DS_INSTRUCTIONS = 37,
573 SP_GS_INSTRUCTIONS = 38,
574 SP_CS_INSTRUCTIONS = 39,
575 SP_SCHEDULER_NON_WORKING = 40,
576 SP_WAVE_CONTEXTS = 41,
577 SP_WAVE_CONTEXT_CYCLES = 42,
578 SP_POWER0 = 43,
579 SP_POWER1 = 44,
580 SP_POWER2 = 45,
581 SP_POWER3 = 46,
582 SP_POWER4 = 47,
583 SP_POWER5 = 48,
584 SP_POWER6 = 49,
585 SP_POWER7 = 50,
586 SP_POWER8 = 51,
587 SP_POWER9 = 52,
588 SP_POWER10 = 53,
589 SP_POWER11 = 54,
590 SP_POWER12 = 55,
591 SP_POWER13 = 56,
592 SP_POWER14 = 57,
593 SP_POWER15 = 58,
594};
595
596enum a4xx_tp_perfcounter_select {
597 TP_L1_REQUESTS = 0,
598 TP_L1_MISSES = 1,
599 TP_QUADS_OFFSET = 8,
600 TP_QUAD_SHADOW = 9,
601 TP_QUADS_ARRAY = 10,
602 TP_QUADS_GRADIENT = 11,
603 TP_QUADS_1D2D = 12,
604 TP_QUADS_3DCUBE = 13,
605 TP_BUSY_CYCLES = 16,
606 TP_STALL_CYCLES_BY_ARB = 17,
607 TP_STATE_CACHE_REQUESTS = 20,
608 TP_STATE_CACHE_MISSES = 21,
609 TP_POWER0 = 22,
610 TP_POWER1 = 23,
611 TP_POWER2 = 24,
612 TP_POWER3 = 25,
613 TP_POWER4 = 26,
614 TP_POWER5 = 27,
615 TP_POWER6 = 28,
616 TP_POWER7 = 29,
617};
618
619enum a4xx_uche_perfcounter_select {
620 UCHE_VBIF_READ_BEATS_TP = 0,
621 UCHE_VBIF_READ_BEATS_VFD = 1,
622 UCHE_VBIF_READ_BEATS_HLSQ = 2,
623 UCHE_VBIF_READ_BEATS_MARB = 3,
624 UCHE_VBIF_READ_BEATS_SP = 4,
625 UCHE_READ_REQUESTS_TP = 5,
626 UCHE_READ_REQUESTS_VFD = 6,
627 UCHE_READ_REQUESTS_HLSQ = 7,
628 UCHE_READ_REQUESTS_MARB = 8,
629 UCHE_READ_REQUESTS_SP = 9,
630 UCHE_WRITE_REQUESTS_MARB = 10,
631 UCHE_WRITE_REQUESTS_SP = 11,
632 UCHE_TAG_CHECK_FAILS = 12,
633 UCHE_EVICTS = 13,
634 UCHE_FLUSHES = 14,
635 UCHE_VBIF_LATENCY_CYCLES = 15,
636 UCHE_VBIF_LATENCY_SAMPLES = 16,
637 UCHE_BUSY_CYCLES = 17,
638 UCHE_VBIF_READ_BEATS_PC = 18,
639 UCHE_READ_REQUESTS_PC = 19,
640 UCHE_WRITE_REQUESTS_VPC = 20,
641 UCHE_STALL_BY_VBIF = 21,
642 UCHE_WRITE_REQUESTS_VSC = 22,
643 UCHE_POWER0 = 23,
644 UCHE_POWER1 = 24,
645 UCHE_POWER2 = 25,
646 UCHE_POWER3 = 26,
647 UCHE_POWER4 = 27,
648 UCHE_POWER5 = 28,
649 UCHE_POWER6 = 29,
650 UCHE_POWER7 = 30,
651};
652
653enum a4xx_vbif_perfcounter_select {
654 AXI_READ_REQUESTS_ID_0 = 0,
655 AXI_READ_REQUESTS_ID_1 = 1,
656 AXI_READ_REQUESTS_ID_2 = 2,
657 AXI_READ_REQUESTS_ID_3 = 3,
658 AXI_READ_REQUESTS_ID_4 = 4,
659 AXI_READ_REQUESTS_ID_5 = 5,
660 AXI_READ_REQUESTS_ID_6 = 6,
661 AXI_READ_REQUESTS_ID_7 = 7,
662 AXI_READ_REQUESTS_ID_8 = 8,
663 AXI_READ_REQUESTS_ID_9 = 9,
664 AXI_READ_REQUESTS_ID_10 = 10,
665 AXI_READ_REQUESTS_ID_11 = 11,
666 AXI_READ_REQUESTS_ID_12 = 12,
667 AXI_READ_REQUESTS_ID_13 = 13,
668 AXI_READ_REQUESTS_ID_14 = 14,
669 AXI_READ_REQUESTS_ID_15 = 15,
670 AXI0_READ_REQUESTS_TOTAL = 16,
671 AXI1_READ_REQUESTS_TOTAL = 17,
672 AXI2_READ_REQUESTS_TOTAL = 18,
673 AXI3_READ_REQUESTS_TOTAL = 19,
674 AXI_READ_REQUESTS_TOTAL = 20,
675 AXI_WRITE_REQUESTS_ID_0 = 21,
676 AXI_WRITE_REQUESTS_ID_1 = 22,
677 AXI_WRITE_REQUESTS_ID_2 = 23,
678 AXI_WRITE_REQUESTS_ID_3 = 24,
679 AXI_WRITE_REQUESTS_ID_4 = 25,
680 AXI_WRITE_REQUESTS_ID_5 = 26,
681 AXI_WRITE_REQUESTS_ID_6 = 27,
682 AXI_WRITE_REQUESTS_ID_7 = 28,
683 AXI_WRITE_REQUESTS_ID_8 = 29,
684 AXI_WRITE_REQUESTS_ID_9 = 30,
685 AXI_WRITE_REQUESTS_ID_10 = 31,
686 AXI_WRITE_REQUESTS_ID_11 = 32,
687 AXI_WRITE_REQUESTS_ID_12 = 33,
688 AXI_WRITE_REQUESTS_ID_13 = 34,
689 AXI_WRITE_REQUESTS_ID_14 = 35,
690 AXI_WRITE_REQUESTS_ID_15 = 36,
691 AXI0_WRITE_REQUESTS_TOTAL = 37,
692 AXI1_WRITE_REQUESTS_TOTAL = 38,
693 AXI2_WRITE_REQUESTS_TOTAL = 39,
694 AXI3_WRITE_REQUESTS_TOTAL = 40,
695 AXI_WRITE_REQUESTS_TOTAL = 41,
696 AXI_TOTAL_REQUESTS = 42,
697 AXI_READ_DATA_BEATS_ID_0 = 43,
698 AXI_READ_DATA_BEATS_ID_1 = 44,
699 AXI_READ_DATA_BEATS_ID_2 = 45,
700 AXI_READ_DATA_BEATS_ID_3 = 46,
701 AXI_READ_DATA_BEATS_ID_4 = 47,
702 AXI_READ_DATA_BEATS_ID_5 = 48,
703 AXI_READ_DATA_BEATS_ID_6 = 49,
704 AXI_READ_DATA_BEATS_ID_7 = 50,
705 AXI_READ_DATA_BEATS_ID_8 = 51,
706 AXI_READ_DATA_BEATS_ID_9 = 52,
707 AXI_READ_DATA_BEATS_ID_10 = 53,
708 AXI_READ_DATA_BEATS_ID_11 = 54,
709 AXI_READ_DATA_BEATS_ID_12 = 55,
710 AXI_READ_DATA_BEATS_ID_13 = 56,
711 AXI_READ_DATA_BEATS_ID_14 = 57,
712 AXI_READ_DATA_BEATS_ID_15 = 58,
713 AXI0_READ_DATA_BEATS_TOTAL = 59,
714 AXI1_READ_DATA_BEATS_TOTAL = 60,
715 AXI2_READ_DATA_BEATS_TOTAL = 61,
716 AXI3_READ_DATA_BEATS_TOTAL = 62,
717 AXI_READ_DATA_BEATS_TOTAL = 63,
718 AXI_WRITE_DATA_BEATS_ID_0 = 64,
719 AXI_WRITE_DATA_BEATS_ID_1 = 65,
720 AXI_WRITE_DATA_BEATS_ID_2 = 66,
721 AXI_WRITE_DATA_BEATS_ID_3 = 67,
722 AXI_WRITE_DATA_BEATS_ID_4 = 68,
723 AXI_WRITE_DATA_BEATS_ID_5 = 69,
724 AXI_WRITE_DATA_BEATS_ID_6 = 70,
725 AXI_WRITE_DATA_BEATS_ID_7 = 71,
726 AXI_WRITE_DATA_BEATS_ID_8 = 72,
727 AXI_WRITE_DATA_BEATS_ID_9 = 73,
728 AXI_WRITE_DATA_BEATS_ID_10 = 74,
729 AXI_WRITE_DATA_BEATS_ID_11 = 75,
730 AXI_WRITE_DATA_BEATS_ID_12 = 76,
731 AXI_WRITE_DATA_BEATS_ID_13 = 77,
732 AXI_WRITE_DATA_BEATS_ID_14 = 78,
733 AXI_WRITE_DATA_BEATS_ID_15 = 79,
734 AXI0_WRITE_DATA_BEATS_TOTAL = 80,
735 AXI1_WRITE_DATA_BEATS_TOTAL = 81,
736 AXI2_WRITE_DATA_BEATS_TOTAL = 82,
737 AXI3_WRITE_DATA_BEATS_TOTAL = 83,
738 AXI_WRITE_DATA_BEATS_TOTAL = 84,
739 AXI_DATA_BEATS_TOTAL = 85,
740 CYCLES_HELD_OFF_ID_0 = 86,
741 CYCLES_HELD_OFF_ID_1 = 87,
742 CYCLES_HELD_OFF_ID_2 = 88,
743 CYCLES_HELD_OFF_ID_3 = 89,
744 CYCLES_HELD_OFF_ID_4 = 90,
745 CYCLES_HELD_OFF_ID_5 = 91,
746 CYCLES_HELD_OFF_ID_6 = 92,
747 CYCLES_HELD_OFF_ID_7 = 93,
748 CYCLES_HELD_OFF_ID_8 = 94,
749 CYCLES_HELD_OFF_ID_9 = 95,
750 CYCLES_HELD_OFF_ID_10 = 96,
751 CYCLES_HELD_OFF_ID_11 = 97,
752 CYCLES_HELD_OFF_ID_12 = 98,
753 CYCLES_HELD_OFF_ID_13 = 99,
754 CYCLES_HELD_OFF_ID_14 = 100,
755 CYCLES_HELD_OFF_ID_15 = 101,
756 AXI_READ_REQUEST_HELD_OFF = 102,
757 AXI_WRITE_REQUEST_HELD_OFF = 103,
758 AXI_REQUEST_HELD_OFF = 104,
759 AXI_WRITE_DATA_HELD_OFF = 105,
760 OCMEM_AXI_READ_REQUEST_HELD_OFF = 106,
761 OCMEM_AXI_WRITE_REQUEST_HELD_OFF = 107,
762 OCMEM_AXI_REQUEST_HELD_OFF = 108,
763 OCMEM_AXI_WRITE_DATA_HELD_OFF = 109,
764 ELAPSED_CYCLES_DDR = 110,
765 ELAPSED_CYCLES_OCMEM = 111,
766};
767
768enum a4xx_vfd_perfcounter_select {
769 VFD_UCHE_BYTE_FETCHED = 0,
770 VFD_UCHE_TRANS = 1,
771 VFD_FETCH_INSTRUCTIONS = 3,
772 VFD_BUSY_CYCLES = 5,
773 VFD_STALL_CYCLES_UCHE = 6,
774 VFD_STALL_CYCLES_HLSQ = 7,
775 VFD_STALL_CYCLES_VPC_BYPASS = 8,
776 VFD_STALL_CYCLES_VPC_ALLOC = 9,
777 VFD_MODE_0_FIBERS = 13,
778 VFD_MODE_1_FIBERS = 14,
779 VFD_MODE_2_FIBERS = 15,
780 VFD_MODE_3_FIBERS = 16,
781 VFD_MODE_4_FIBERS = 17,
782 VFD_BFIFO_STALL = 18,
783 VFD_NUM_VERTICES_TOTAL = 19,
784 VFD_PACKER_FULL = 20,
785 VFD_UCHE_REQUEST_FIFO_FULL = 21,
786 VFD_STARVE_CYCLES_PC = 22,
787 VFD_STARVE_CYCLES_UCHE = 23,
788};
789
790enum a4xx_vpc_perfcounter_select {
791 VPC_SP_LM_COMPONENTS = 2,
792 VPC_SP0_LM_BYTES = 3,
793 VPC_SP1_LM_BYTES = 4,
794 VPC_SP2_LM_BYTES = 5,
795 VPC_SP3_LM_BYTES = 6,
796 VPC_WORKING_CYCLES = 7,
797 VPC_STALL_CYCLES_LM = 8,
798 VPC_STARVE_CYCLES_RAS = 9,
799 VPC_STREAMOUT_CYCLES = 10,
800 VPC_UCHE_TRANSACTIONS = 12,
801 VPC_STALL_CYCLES_UCHE = 13,
802 VPC_BUSY_CYCLES = 14,
803 VPC_STARVE_CYCLES_SP = 15,
804};
805
806enum a4xx_vsc_perfcounter_select {
807 VSC_BUSY_CYCLES = 0,
808 VSC_WORKING_CYCLES = 1,
809 VSC_STALL_CYCLES_UCHE = 2,
810 VSC_STARVE_CYCLES_RAS = 3,
811 VSC_EOT_NUM = 4,
812};
813
243enum a4xx_tex_filter {
244 A4XX_TEX_NEAREST = 0,
245 A4XX_TEX_LINEAR = 1,
246 A4XX_TEX_ANISO = 2,
247};
248
249enum a4xx_tex_clamp {
250 A4XX_TEX_REPEAT = 0,

--- 70 unchanged lines hidden (view full) ---

321#define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb
322
323#define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc
324
325#define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd
326
327#define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce
328
814enum a4xx_tex_filter {
815 A4XX_TEX_NEAREST = 0,
816 A4XX_TEX_LINEAR = 1,
817 A4XX_TEX_ANISO = 2,
818};
819
820enum a4xx_tex_clamp {
821 A4XX_TEX_REPEAT = 0,

--- 70 unchanged lines hidden (view full) ---

892#define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb
893
894#define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc
895
896#define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd
897
898#define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce
899
900#define REG_A4XX_RB_PERFCTR_CCU_SEL_0 0x00000ccf
901
902#define REG_A4XX_RB_PERFCTR_CCU_SEL_1 0x00000cd0
903
904#define REG_A4XX_RB_PERFCTR_CCU_SEL_2 0x00000cd1
905
329#define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2
330
331#define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
332#define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff
333#define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0
334static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
335{
336 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;

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395#define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000
396
397static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
398
399static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
400#define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
401#define A4XX_RB_MRT_CONTROL_BLEND 0x00000010
402#define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020
906#define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2
907
908#define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
909#define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff
910#define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0
911static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
912{
913 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;

--- 58 unchanged lines hidden (view full) ---

972#define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000
973
974static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
975
976static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
977#define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
978#define A4XX_RB_MRT_CONTROL_BLEND 0x00000010
979#define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020
403#define A4XX_RB_MRT_CONTROL_FASTCLEAR 0x00000400
404#define A4XX_RB_MRT_CONTROL_B11 0x00000800
980#define A4XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000040
981#define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00
982#define A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8
983static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
984{
985 return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK;
986}
405#define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
406#define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24
407static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
408{
409 return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
410}
411
412static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; }

--- 72 unchanged lines hidden (view full) ---

485}
486#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
487#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
488static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
489{
490 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
491}
492
987#define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
988#define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24
989static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
990{
991 return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
992}
993
994static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; }

--- 72 unchanged lines hidden (view full) ---

1067}
1068#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
1069#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
1070static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
1071{
1072 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
1073}
1074
493#define REG_A4XX_RB_BLEND_RED 0x000020f3
494#define A4XX_RB_BLEND_RED_UINT__MASK 0x00007fff
1075#define REG_A4XX_RB_BLEND_RED 0x000020f0
1076#define A4XX_RB_BLEND_RED_UINT__MASK 0x0000ffff
495#define A4XX_RB_BLEND_RED_UINT__SHIFT 0
496static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)
497{
498 return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK;
499}
500#define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
501#define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
502static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
503{
504 return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
505}
506
1077#define A4XX_RB_BLEND_RED_UINT__SHIFT 0
1078static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)
1079{
1080 return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK;
1081}
1082#define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
1083#define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
1084static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
1085{
1086 return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
1087}
1088
507#define REG_A4XX_RB_BLEND_GREEN 0x000020f4
508#define A4XX_RB_BLEND_GREEN_UINT__MASK 0x00007fff
1089#define REG_A4XX_RB_BLEND_RED_F32 0x000020f1
1090#define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff
1091#define A4XX_RB_BLEND_RED_F32__SHIFT 0
1092static inline uint32_t A4XX_RB_BLEND_RED_F32(float val)
1093{
1094 return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK;
1095}
1096
1097#define REG_A4XX_RB_BLEND_GREEN 0x000020f2
1098#define A4XX_RB_BLEND_GREEN_UINT__MASK 0x0000ffff
509#define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0
510static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)
511{
512 return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK;
513}
514#define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
515#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
516static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
517{
518 return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
519}
520
1099#define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0
1100static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)
1101{
1102 return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK;
1103}
1104#define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
1105#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
1106static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
1107{
1108 return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
1109}
1110
521#define REG_A4XX_RB_BLEND_BLUE 0x000020f5
522#define A4XX_RB_BLEND_BLUE_UINT__MASK 0x00007fff
1111#define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3
1112#define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
1113#define A4XX_RB_BLEND_GREEN_F32__SHIFT 0
1114static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val)
1115{
1116 return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK;
1117}
1118
1119#define REG_A4XX_RB_BLEND_BLUE 0x000020f4
1120#define A4XX_RB_BLEND_BLUE_UINT__MASK 0x0000ffff
523#define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0
524static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)
525{
526 return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK;
527}
528#define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
529#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
530static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
531{
532 return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
533}
534
1121#define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0
1122static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)
1123{
1124 return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK;
1125}
1126#define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
1127#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
1128static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
1129{
1130 return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
1131}
1132
1133#define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5
1134#define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
1135#define A4XX_RB_BLEND_BLUE_F32__SHIFT 0
1136static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val)
1137{
1138 return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK;
1139}
1140
535#define REG_A4XX_RB_BLEND_ALPHA 0x000020f6
1141#define REG_A4XX_RB_BLEND_ALPHA 0x000020f6
536#define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x00007fff
1142#define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x0000ffff
537#define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0
538static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)
539{
540 return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK;
541}
542#define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
543#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
544static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
545{
546 return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
547}
548
1143#define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0
1144static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)
1145{
1146 return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK;
1147}
1148#define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
1149#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
1150static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
1151{
1152 return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
1153}
1154
1155#define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7
1156#define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
1157#define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0
1158static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val)
1159{
1160 return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK;
1161}
1162
549#define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8
550#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
551#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
552static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
553{
554 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
555}
556#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100

--- 6 unchanged lines hidden (view full) ---

563
564#define REG_A4XX_RB_FS_OUTPUT 0x000020f9
565#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff
566#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0
567static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)
568{
569 return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK;
570}
1163#define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8
1164#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
1165#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
1166static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
1167{
1168 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
1169}
1170#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100

--- 6 unchanged lines hidden (view full) ---

1177
1178#define REG_A4XX_RB_FS_OUTPUT 0x000020f9
1179#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff
1180#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0
1181static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)
1182{
1183 return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK;
1184}
571#define A4XX_RB_FS_OUTPUT_FAST_CLEAR 0x00000100
1185#define A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND 0x00000100
572#define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000
573#define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16
574static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
575{
576 return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;
577}
578
579#define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa

--- 151 unchanged lines hidden (view full) ---

731#define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
732#define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
733static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
734{
735 return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
736}
737#define A4XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080
738#define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000
1186#define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000
1187#define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16
1188static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
1189{
1190 return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;
1191}
1192
1193#define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa

--- 151 unchanged lines hidden (view full) ---

1345#define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
1346#define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
1347static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
1348{
1349 return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
1350}
1351#define A4XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080
1352#define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000
1353#define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000
739#define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
740
741#define REG_A4XX_RB_DEPTH_CLEAR 0x00002102
742
743#define REG_A4XX_RB_DEPTH_INFO 0x00002103
744#define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003
745#define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
746static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val)

--- 244 unchanged lines hidden (view full) ---

991#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a
992
993#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b
994
995#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c
996
997#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d
998
1354#define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
1355
1356#define REG_A4XX_RB_DEPTH_CLEAR 0x00002102
1357
1358#define REG_A4XX_RB_DEPTH_INFO 0x00002103
1359#define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003
1360#define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
1361static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val)

--- 244 unchanged lines hidden (view full) ---

1606#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a
1607
1608#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b
1609
1610#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c
1611
1612#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d
1613
1614#define REG_A4XX_RBBM_POWER_CNTL_IP 0x00000098
1615#define A4XX_RBBM_POWER_CNTL_IP_SW_COLLAPSE 0x00000001
1616#define A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON 0x00100000
1617
999#define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c
1000
1618#define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c
1619
1620#define REG_A4XX_RBBM_PERFCTR_CP_0_HI 0x0000009d
1621
1622#define REG_A4XX_RBBM_PERFCTR_CP_1_LO 0x0000009e
1623
1624#define REG_A4XX_RBBM_PERFCTR_CP_1_HI 0x0000009f
1625
1626#define REG_A4XX_RBBM_PERFCTR_CP_2_LO 0x000000a0
1627
1628#define REG_A4XX_RBBM_PERFCTR_CP_2_HI 0x000000a1
1629
1630#define REG_A4XX_RBBM_PERFCTR_CP_3_LO 0x000000a2
1631
1632#define REG_A4XX_RBBM_PERFCTR_CP_3_HI 0x000000a3
1633
1634#define REG_A4XX_RBBM_PERFCTR_CP_4_LO 0x000000a4
1635
1636#define REG_A4XX_RBBM_PERFCTR_CP_4_HI 0x000000a5
1637
1638#define REG_A4XX_RBBM_PERFCTR_CP_5_LO 0x000000a6
1639
1640#define REG_A4XX_RBBM_PERFCTR_CP_5_HI 0x000000a7
1641
1642#define REG_A4XX_RBBM_PERFCTR_CP_6_LO 0x000000a8
1643
1644#define REG_A4XX_RBBM_PERFCTR_CP_6_HI 0x000000a9
1645
1646#define REG_A4XX_RBBM_PERFCTR_CP_7_LO 0x000000aa
1647
1648#define REG_A4XX_RBBM_PERFCTR_CP_7_HI 0x000000ab
1649
1650#define REG_A4XX_RBBM_PERFCTR_RBBM_0_LO 0x000000ac
1651
1652#define REG_A4XX_RBBM_PERFCTR_RBBM_0_HI 0x000000ad
1653
1654#define REG_A4XX_RBBM_PERFCTR_RBBM_1_LO 0x000000ae
1655
1656#define REG_A4XX_RBBM_PERFCTR_RBBM_1_HI 0x000000af
1657
1658#define REG_A4XX_RBBM_PERFCTR_RBBM_2_LO 0x000000b0
1659
1660#define REG_A4XX_RBBM_PERFCTR_RBBM_2_HI 0x000000b1
1661
1662#define REG_A4XX_RBBM_PERFCTR_RBBM_3_LO 0x000000b2
1663
1664#define REG_A4XX_RBBM_PERFCTR_RBBM_3_HI 0x000000b3
1665
1666#define REG_A4XX_RBBM_PERFCTR_PC_0_LO 0x000000b4
1667
1668#define REG_A4XX_RBBM_PERFCTR_PC_0_HI 0x000000b5
1669
1670#define REG_A4XX_RBBM_PERFCTR_PC_1_LO 0x000000b6
1671
1672#define REG_A4XX_RBBM_PERFCTR_PC_1_HI 0x000000b7
1673
1674#define REG_A4XX_RBBM_PERFCTR_PC_2_LO 0x000000b8
1675
1676#define REG_A4XX_RBBM_PERFCTR_PC_2_HI 0x000000b9
1677
1678#define REG_A4XX_RBBM_PERFCTR_PC_3_LO 0x000000ba
1679
1680#define REG_A4XX_RBBM_PERFCTR_PC_3_HI 0x000000bb
1681
1682#define REG_A4XX_RBBM_PERFCTR_PC_4_LO 0x000000bc
1683
1684#define REG_A4XX_RBBM_PERFCTR_PC_4_HI 0x000000bd
1685
1686#define REG_A4XX_RBBM_PERFCTR_PC_5_LO 0x000000be
1687
1688#define REG_A4XX_RBBM_PERFCTR_PC_5_HI 0x000000bf
1689
1690#define REG_A4XX_RBBM_PERFCTR_PC_6_LO 0x000000c0
1691
1692#define REG_A4XX_RBBM_PERFCTR_PC_6_HI 0x000000c1
1693
1694#define REG_A4XX_RBBM_PERFCTR_PC_7_LO 0x000000c2
1695
1696#define REG_A4XX_RBBM_PERFCTR_PC_7_HI 0x000000c3
1697
1698#define REG_A4XX_RBBM_PERFCTR_VFD_0_LO 0x000000c4
1699
1700#define REG_A4XX_RBBM_PERFCTR_VFD_0_HI 0x000000c5
1701
1702#define REG_A4XX_RBBM_PERFCTR_VFD_1_LO 0x000000c6
1703
1704#define REG_A4XX_RBBM_PERFCTR_VFD_1_HI 0x000000c7
1705
1706#define REG_A4XX_RBBM_PERFCTR_VFD_2_LO 0x000000c8
1707
1708#define REG_A4XX_RBBM_PERFCTR_VFD_2_HI 0x000000c9
1709
1710#define REG_A4XX_RBBM_PERFCTR_VFD_3_LO 0x000000ca
1711
1712#define REG_A4XX_RBBM_PERFCTR_VFD_3_HI 0x000000cb
1713
1714#define REG_A4XX_RBBM_PERFCTR_VFD_4_LO 0x000000cc
1715
1716#define REG_A4XX_RBBM_PERFCTR_VFD_4_HI 0x000000cd
1717
1718#define REG_A4XX_RBBM_PERFCTR_VFD_5_LO 0x000000ce
1719
1720#define REG_A4XX_RBBM_PERFCTR_VFD_5_HI 0x000000cf
1721
1722#define REG_A4XX_RBBM_PERFCTR_VFD_6_LO 0x000000d0
1723
1724#define REG_A4XX_RBBM_PERFCTR_VFD_6_HI 0x000000d1
1725
1726#define REG_A4XX_RBBM_PERFCTR_VFD_7_LO 0x000000d2
1727
1728#define REG_A4XX_RBBM_PERFCTR_VFD_7_HI 0x000000d3
1729
1730#define REG_A4XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000d4
1731
1732#define REG_A4XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000d5
1733
1734#define REG_A4XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000d6
1735
1736#define REG_A4XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000d7
1737
1738#define REG_A4XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000d8
1739
1740#define REG_A4XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000d9
1741
1742#define REG_A4XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000da
1743
1744#define REG_A4XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000db
1745
1746#define REG_A4XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000dc
1747
1748#define REG_A4XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000dd
1749
1750#define REG_A4XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000de
1751
1752#define REG_A4XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000df
1753
1754#define REG_A4XX_RBBM_PERFCTR_HLSQ_6_LO 0x000000e0
1755
1756#define REG_A4XX_RBBM_PERFCTR_HLSQ_6_HI 0x000000e1
1757
1758#define REG_A4XX_RBBM_PERFCTR_HLSQ_7_LO 0x000000e2
1759
1760#define REG_A4XX_RBBM_PERFCTR_HLSQ_7_HI 0x000000e3
1761
1762#define REG_A4XX_RBBM_PERFCTR_VPC_0_LO 0x000000e4
1763
1764#define REG_A4XX_RBBM_PERFCTR_VPC_0_HI 0x000000e5
1765
1766#define REG_A4XX_RBBM_PERFCTR_VPC_1_LO 0x000000e6
1767
1768#define REG_A4XX_RBBM_PERFCTR_VPC_1_HI 0x000000e7
1769
1770#define REG_A4XX_RBBM_PERFCTR_VPC_2_LO 0x000000e8
1771
1772#define REG_A4XX_RBBM_PERFCTR_VPC_2_HI 0x000000e9
1773
1774#define REG_A4XX_RBBM_PERFCTR_VPC_3_LO 0x000000ea
1775
1776#define REG_A4XX_RBBM_PERFCTR_VPC_3_HI 0x000000eb
1777
1778#define REG_A4XX_RBBM_PERFCTR_CCU_0_LO 0x000000ec
1779
1780#define REG_A4XX_RBBM_PERFCTR_CCU_0_HI 0x000000ed
1781
1782#define REG_A4XX_RBBM_PERFCTR_CCU_1_LO 0x000000ee
1783
1784#define REG_A4XX_RBBM_PERFCTR_CCU_1_HI 0x000000ef
1785
1786#define REG_A4XX_RBBM_PERFCTR_CCU_2_LO 0x000000f0
1787
1788#define REG_A4XX_RBBM_PERFCTR_CCU_2_HI 0x000000f1
1789
1790#define REG_A4XX_RBBM_PERFCTR_CCU_3_LO 0x000000f2
1791
1792#define REG_A4XX_RBBM_PERFCTR_CCU_3_HI 0x000000f3
1793
1794#define REG_A4XX_RBBM_PERFCTR_TSE_0_LO 0x000000f4
1795
1796#define REG_A4XX_RBBM_PERFCTR_TSE_0_HI 0x000000f5
1797
1798#define REG_A4XX_RBBM_PERFCTR_TSE_1_LO 0x000000f6
1799
1800#define REG_A4XX_RBBM_PERFCTR_TSE_1_HI 0x000000f7
1801
1802#define REG_A4XX_RBBM_PERFCTR_TSE_2_LO 0x000000f8
1803
1804#define REG_A4XX_RBBM_PERFCTR_TSE_2_HI 0x000000f9
1805
1806#define REG_A4XX_RBBM_PERFCTR_TSE_3_LO 0x000000fa
1807
1808#define REG_A4XX_RBBM_PERFCTR_TSE_3_HI 0x000000fb
1809
1810#define REG_A4XX_RBBM_PERFCTR_RAS_0_LO 0x000000fc
1811
1812#define REG_A4XX_RBBM_PERFCTR_RAS_0_HI 0x000000fd
1813
1814#define REG_A4XX_RBBM_PERFCTR_RAS_1_LO 0x000000fe
1815
1816#define REG_A4XX_RBBM_PERFCTR_RAS_1_HI 0x000000ff
1817
1818#define REG_A4XX_RBBM_PERFCTR_RAS_2_LO 0x00000100
1819
1820#define REG_A4XX_RBBM_PERFCTR_RAS_2_HI 0x00000101
1821
1822#define REG_A4XX_RBBM_PERFCTR_RAS_3_LO 0x00000102
1823
1824#define REG_A4XX_RBBM_PERFCTR_RAS_3_HI 0x00000103
1825
1826#define REG_A4XX_RBBM_PERFCTR_UCHE_0_LO 0x00000104
1827
1828#define REG_A4XX_RBBM_PERFCTR_UCHE_0_HI 0x00000105
1829
1830#define REG_A4XX_RBBM_PERFCTR_UCHE_1_LO 0x00000106
1831
1832#define REG_A4XX_RBBM_PERFCTR_UCHE_1_HI 0x00000107
1833
1834#define REG_A4XX_RBBM_PERFCTR_UCHE_2_LO 0x00000108
1835
1836#define REG_A4XX_RBBM_PERFCTR_UCHE_2_HI 0x00000109
1837
1838#define REG_A4XX_RBBM_PERFCTR_UCHE_3_LO 0x0000010a
1839
1840#define REG_A4XX_RBBM_PERFCTR_UCHE_3_HI 0x0000010b
1841
1842#define REG_A4XX_RBBM_PERFCTR_UCHE_4_LO 0x0000010c
1843
1844#define REG_A4XX_RBBM_PERFCTR_UCHE_4_HI 0x0000010d
1845
1846#define REG_A4XX_RBBM_PERFCTR_UCHE_5_LO 0x0000010e
1847
1848#define REG_A4XX_RBBM_PERFCTR_UCHE_5_HI 0x0000010f
1849
1850#define REG_A4XX_RBBM_PERFCTR_UCHE_6_LO 0x00000110
1851
1852#define REG_A4XX_RBBM_PERFCTR_UCHE_6_HI 0x00000111
1853
1854#define REG_A4XX_RBBM_PERFCTR_UCHE_7_LO 0x00000112
1855
1856#define REG_A4XX_RBBM_PERFCTR_UCHE_7_HI 0x00000113
1857
1858#define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114
1859
1860#define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115
1861
1862#define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114
1863
1864#define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115
1865
1866#define REG_A4XX_RBBM_PERFCTR_TP_1_LO 0x00000116
1867
1868#define REG_A4XX_RBBM_PERFCTR_TP_1_HI 0x00000117
1869
1870#define REG_A4XX_RBBM_PERFCTR_TP_2_LO 0x00000118
1871
1872#define REG_A4XX_RBBM_PERFCTR_TP_2_HI 0x00000119
1873
1874#define REG_A4XX_RBBM_PERFCTR_TP_3_LO 0x0000011a
1875
1876#define REG_A4XX_RBBM_PERFCTR_TP_3_HI 0x0000011b
1877
1878#define REG_A4XX_RBBM_PERFCTR_TP_4_LO 0x0000011c
1879
1880#define REG_A4XX_RBBM_PERFCTR_TP_4_HI 0x0000011d
1881
1882#define REG_A4XX_RBBM_PERFCTR_TP_5_LO 0x0000011e
1883
1884#define REG_A4XX_RBBM_PERFCTR_TP_5_HI 0x0000011f
1885
1886#define REG_A4XX_RBBM_PERFCTR_TP_6_LO 0x00000120
1887
1888#define REG_A4XX_RBBM_PERFCTR_TP_6_HI 0x00000121
1889
1890#define REG_A4XX_RBBM_PERFCTR_TP_7_LO 0x00000122
1891
1892#define REG_A4XX_RBBM_PERFCTR_TP_7_HI 0x00000123
1893
1894#define REG_A4XX_RBBM_PERFCTR_SP_0_LO 0x00000124
1895
1896#define REG_A4XX_RBBM_PERFCTR_SP_0_HI 0x00000125
1897
1898#define REG_A4XX_RBBM_PERFCTR_SP_1_LO 0x00000126
1899
1900#define REG_A4XX_RBBM_PERFCTR_SP_1_HI 0x00000127
1901
1902#define REG_A4XX_RBBM_PERFCTR_SP_2_LO 0x00000128
1903
1904#define REG_A4XX_RBBM_PERFCTR_SP_2_HI 0x00000129
1905
1906#define REG_A4XX_RBBM_PERFCTR_SP_3_LO 0x0000012a
1907
1908#define REG_A4XX_RBBM_PERFCTR_SP_3_HI 0x0000012b
1909
1910#define REG_A4XX_RBBM_PERFCTR_SP_4_LO 0x0000012c
1911
1912#define REG_A4XX_RBBM_PERFCTR_SP_4_HI 0x0000012d
1913
1914#define REG_A4XX_RBBM_PERFCTR_SP_5_LO 0x0000012e
1915
1916#define REG_A4XX_RBBM_PERFCTR_SP_5_HI 0x0000012f
1917
1918#define REG_A4XX_RBBM_PERFCTR_SP_6_LO 0x00000130
1919
1920#define REG_A4XX_RBBM_PERFCTR_SP_6_HI 0x00000131
1921
1922#define REG_A4XX_RBBM_PERFCTR_SP_7_LO 0x00000132
1923
1924#define REG_A4XX_RBBM_PERFCTR_SP_7_HI 0x00000133
1925
1926#define REG_A4XX_RBBM_PERFCTR_SP_8_LO 0x00000134
1927
1928#define REG_A4XX_RBBM_PERFCTR_SP_8_HI 0x00000135
1929
1930#define REG_A4XX_RBBM_PERFCTR_SP_9_LO 0x00000136
1931
1932#define REG_A4XX_RBBM_PERFCTR_SP_9_HI 0x00000137
1933
1934#define REG_A4XX_RBBM_PERFCTR_SP_10_LO 0x00000138
1935
1936#define REG_A4XX_RBBM_PERFCTR_SP_10_HI 0x00000139
1937
1938#define REG_A4XX_RBBM_PERFCTR_SP_11_LO 0x0000013a
1939
1940#define REG_A4XX_RBBM_PERFCTR_SP_11_HI 0x0000013b
1941
1942#define REG_A4XX_RBBM_PERFCTR_RB_0_LO 0x0000013c
1943
1944#define REG_A4XX_RBBM_PERFCTR_RB_0_HI 0x0000013d
1945
1946#define REG_A4XX_RBBM_PERFCTR_RB_1_LO 0x0000013e
1947
1948#define REG_A4XX_RBBM_PERFCTR_RB_1_HI 0x0000013f
1949
1950#define REG_A4XX_RBBM_PERFCTR_RB_2_LO 0x00000140
1951
1952#define REG_A4XX_RBBM_PERFCTR_RB_2_HI 0x00000141
1953
1954#define REG_A4XX_RBBM_PERFCTR_RB_3_LO 0x00000142
1955
1956#define REG_A4XX_RBBM_PERFCTR_RB_3_HI 0x00000143
1957
1958#define REG_A4XX_RBBM_PERFCTR_RB_4_LO 0x00000144
1959
1960#define REG_A4XX_RBBM_PERFCTR_RB_4_HI 0x00000145
1961
1962#define REG_A4XX_RBBM_PERFCTR_RB_5_LO 0x00000146
1963
1964#define REG_A4XX_RBBM_PERFCTR_RB_5_HI 0x00000147
1965
1966#define REG_A4XX_RBBM_PERFCTR_RB_6_LO 0x00000148
1967
1968#define REG_A4XX_RBBM_PERFCTR_RB_6_HI 0x00000149
1969
1970#define REG_A4XX_RBBM_PERFCTR_RB_7_LO 0x0000014a
1971
1972#define REG_A4XX_RBBM_PERFCTR_RB_7_HI 0x0000014b
1973
1974#define REG_A4XX_RBBM_PERFCTR_VSC_0_LO 0x0000014c
1975
1976#define REG_A4XX_RBBM_PERFCTR_VSC_0_HI 0x0000014d
1977
1978#define REG_A4XX_RBBM_PERFCTR_VSC_1_LO 0x0000014e
1979
1980#define REG_A4XX_RBBM_PERFCTR_VSC_1_HI 0x0000014f
1981
1982#define REG_A4XX_RBBM_PERFCTR_PWR_0_LO 0x00000166
1983
1984#define REG_A4XX_RBBM_PERFCTR_PWR_0_HI 0x00000167
1985
1986#define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
1987
1988#define REG_A4XX_RBBM_PERFCTR_PWR_1_HI 0x00000169
1989
1990#define REG_A4XX_RBBM_ALWAYSON_COUNTER_LO 0x0000016e
1991
1992#define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI 0x0000016f
1993
1001static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; }
1002
1003static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }
1004
1005static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; }
1006
1007static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; }
1008

--- 32 unchanged lines hidden (view full) ---

1041#define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c
1042
1043#define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d
1044
1045static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; }
1046
1047static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; }
1048
1994static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; }
1995
1996static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }
1997
1998static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; }
1999
2000static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; }
2001

--- 32 unchanged lines hidden (view full) ---

2034#define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c
2035
2036#define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d
2037
2038static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; }
2039
2040static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; }
2041
2042#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x00000099
2043
2044#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x0000009a
2045
1049#define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
1050
1051#define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170
1052
1053#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171
1054
1055#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172
1056
1057#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173
1058
1059#define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174
1060
1061#define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175
1062
2046#define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
2047
2048#define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170
2049
2050#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171
2051
2052#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172
2053
2054#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173
2055
2056#define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174
2057
2058#define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175
2059
2060#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000176
2061
2062#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000177
2063
2064#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000178
2065
2066#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_3 0x00000179
2067
1063#define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a
1064
1065#define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d
1066
1067#define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182
1068
1069#define REG_A4XX_RBBM_AHB_STATUS 0x00000189
1070

--- 23 unchanged lines hidden (view full) ---

1094#define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000
1095#define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000
1096#define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
1097#define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
1098#define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000
1099
1100#define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f
1101
2068#define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a
2069
2070#define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d
2071
2072#define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182
2073
2074#define REG_A4XX_RBBM_AHB_STATUS 0x00000189
2075

--- 23 unchanged lines hidden (view full) ---

2099#define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000
2100#define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000
2101#define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
2102#define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
2103#define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000
2104
2105#define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f
2106
2107#define REG_A4XX_RBBM_POWER_STATUS 0x000001b0
2108#define A4XX_RBBM_POWER_STATUS_SP_TP_PWR_ON 0x00100000
2109
2110#define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2 0x000001b8
2111
1102#define REG_A4XX_CP_SCRATCH_UMASK 0x00000228
1103
1104#define REG_A4XX_CP_SCRATCH_ADDR 0x00000229
1105
1106#define REG_A4XX_CP_RB_BASE 0x00000200
1107
1108#define REG_A4XX_CP_RB_CNTL 0x00000201
1109

--- 76 unchanged lines hidden (view full) ---

1186#define REG_A4XX_CP_HW_FAULT 0x000004d8
1187
1188#define REG_A4XX_CP_PROTECT_STATUS 0x000004da
1189
1190#define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd
1191
1192#define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500
1193
2112#define REG_A4XX_CP_SCRATCH_UMASK 0x00000228
2113
2114#define REG_A4XX_CP_SCRATCH_ADDR 0x00000229
2115
2116#define REG_A4XX_CP_RB_BASE 0x00000200
2117
2118#define REG_A4XX_CP_RB_CNTL 0x00000201
2119

--- 76 unchanged lines hidden (view full) ---

2196#define REG_A4XX_CP_HW_FAULT 0x000004d8
2197
2198#define REG_A4XX_CP_PROTECT_STATUS 0x000004da
2199
2200#define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd
2201
2202#define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500
2203
2204#define REG_A4XX_CP_PERFCTR_CP_SEL_1 0x00000501
2205
2206#define REG_A4XX_CP_PERFCTR_CP_SEL_2 0x00000502
2207
2208#define REG_A4XX_CP_PERFCTR_CP_SEL_3 0x00000503
2209
2210#define REG_A4XX_CP_PERFCTR_CP_SEL_4 0x00000504
2211
2212#define REG_A4XX_CP_PERFCTR_CP_SEL_5 0x00000505
2213
2214#define REG_A4XX_CP_PERFCTR_CP_SEL_6 0x00000506
2215
2216#define REG_A4XX_CP_PERFCTR_CP_SEL_7 0x00000507
2217
1194#define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b
1195
1196static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; }
1197
1198static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; }
1199
1200#define REG_A4XX_SP_VS_STATUS 0x00000ec0
1201
1202#define REG_A4XX_SP_MODE_CONTROL 0x00000ec3
1203
2218#define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b
2219
2220static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; }
2221
2222static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; }
2223
2224#define REG_A4XX_SP_VS_STATUS 0x00000ec0
2225
2226#define REG_A4XX_SP_MODE_CONTROL 0x00000ec3
2227
2228#define REG_A4XX_SP_PERFCTR_SP_SEL_0 0x00000ec4
2229
2230#define REG_A4XX_SP_PERFCTR_SP_SEL_1 0x00000ec5
2231
2232#define REG_A4XX_SP_PERFCTR_SP_SEL_2 0x00000ec6
2233
2234#define REG_A4XX_SP_PERFCTR_SP_SEL_3 0x00000ec7
2235
2236#define REG_A4XX_SP_PERFCTR_SP_SEL_4 0x00000ec8
2237
2238#define REG_A4XX_SP_PERFCTR_SP_SEL_5 0x00000ec9
2239
2240#define REG_A4XX_SP_PERFCTR_SP_SEL_6 0x00000eca
2241
2242#define REG_A4XX_SP_PERFCTR_SP_SEL_7 0x00000ecb
2243
2244#define REG_A4XX_SP_PERFCTR_SP_SEL_8 0x00000ecc
2245
2246#define REG_A4XX_SP_PERFCTR_SP_SEL_9 0x00000ecd
2247
2248#define REG_A4XX_SP_PERFCTR_SP_SEL_10 0x00000ece
2249
1204#define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf
1205
1206#define REG_A4XX_SP_SP_CTRL_REG 0x000022c0
1207#define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000
1208
1209#define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1
1210#define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080
1211#define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100

--- 482 unchanged lines hidden (view full) ---

1694#define REG_A4XX_SP_GS_LENGTH_REG 0x00002360
1695
1696#define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60
1697
1698#define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61
1699
1700#define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64
1701
2250#define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf
2251
2252#define REG_A4XX_SP_SP_CTRL_REG 0x000022c0
2253#define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000
2254
2255#define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1
2256#define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080
2257#define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100

--- 482 unchanged lines hidden (view full) ---

2740#define REG_A4XX_SP_GS_LENGTH_REG 0x00002360
2741
2742#define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60
2743
2744#define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61
2745
2746#define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64
2747
2748#define REG_A4XX_VPC_PERFCTR_VPC_SEL_0 0x00000e65
2749
2750#define REG_A4XX_VPC_PERFCTR_VPC_SEL_1 0x00000e66
2751
2752#define REG_A4XX_VPC_PERFCTR_VPC_SEL_2 0x00000e67
2753
1702#define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68
1703
1704#define REG_A4XX_VPC_ATTR 0x00002140
1705#define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff
1706#define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0
1707static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val)
1708{
1709 return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK;

--- 96 unchanged lines hidden (view full) ---

1806#define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41
1807
1808#define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50
1809
1810#define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51
1811
1812#define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40
1813
2754#define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68
2755
2756#define REG_A4XX_VPC_ATTR 0x00002140
2757#define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff
2758#define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0
2759static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val)
2760{
2761 return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK;

--- 96 unchanged lines hidden (view full) ---

2858#define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41
2859
2860#define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50
2861
2862#define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51
2863
2864#define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40
2865
2866#define REG_A4XX_VFD_PERFCTR_VFD_SEL_0 0x00000e43
2867
2868#define REG_A4XX_VFD_PERFCTR_VFD_SEL_1 0x00000e44
2869
2870#define REG_A4XX_VFD_PERFCTR_VFD_SEL_2 0x00000e45
2871
2872#define REG_A4XX_VFD_PERFCTR_VFD_SEL_3 0x00000e46
2873
2874#define REG_A4XX_VFD_PERFCTR_VFD_SEL_4 0x00000e47
2875
2876#define REG_A4XX_VFD_PERFCTR_VFD_SEL_5 0x00000e48
2877
2878#define REG_A4XX_VFD_PERFCTR_VFD_SEL_6 0x00000e49
2879
1814#define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a
1815
1816#define REG_A4XX_VGT_CL_INITIATOR 0x000021d0
1817
1818#define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9
1819
1820#define REG_A4XX_VFD_CONTROL_0 0x00002200
1821#define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff

--- 140 unchanged lines hidden (view full) ---

1962}
1963#define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000
1964#define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000
1965
1966#define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00
1967
1968#define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03
1969
2880#define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a
2881
2882#define REG_A4XX_VGT_CL_INITIATOR 0x000021d0
2883
2884#define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9
2885
2886#define REG_A4XX_VFD_CONTROL_0 0x00002200
2887#define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff

--- 140 unchanged lines hidden (view full) ---

3028}
3029#define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000
3030#define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000
3031
3032#define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00
3033
3034#define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03
3035
3036#define REG_A4XX_TPL1_PERFCTR_TP_SEL_0 0x00000f04
3037
3038#define REG_A4XX_TPL1_PERFCTR_TP_SEL_1 0x00000f05
3039
3040#define REG_A4XX_TPL1_PERFCTR_TP_SEL_2 0x00000f06
3041
3042#define REG_A4XX_TPL1_PERFCTR_TP_SEL_3 0x00000f07
3043
3044#define REG_A4XX_TPL1_PERFCTR_TP_SEL_4 0x00000f08
3045
3046#define REG_A4XX_TPL1_PERFCTR_TP_SEL_5 0x00000f09
3047
3048#define REG_A4XX_TPL1_PERFCTR_TP_SEL_6 0x00000f0a
3049
1970#define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b
1971
1972#define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380
1973
1974#define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381
1975#define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff
1976#define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0
1977static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val)

--- 38 unchanged lines hidden (view full) ---

2016#define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6
2017
2018#define REG_A4XX_GRAS_TSE_STATUS 0x00000c80
2019
2020#define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81
2021
2022#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88
2023
3050#define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b
3051
3052#define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380
3053
3054#define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381
3055#define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff
3056#define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0
3057static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val)

--- 38 unchanged lines hidden (view full) ---

3096#define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6
3097
3098#define REG_A4XX_GRAS_TSE_STATUS 0x00000c80
3099
3100#define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81
3101
3102#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88
3103
3104#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c89
3105
3106#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c8a
3107
2024#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b
2025
3108#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b
3109
3110#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c8c
3111
3112#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c8d
3113
3114#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c8e
3115
3116#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c8f
3117
2026#define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000
3118#define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000
3119#define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000
3120#define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000
2027
2028#define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003
2029#define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001
2030
2031#define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004
2032#define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
2033#define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0
2034static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)

--- 74 unchanged lines hidden (view full) ---

2109#define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0
2110static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val)
2111{
2112 return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK;
2113}
2114
2115#define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073
2116#define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004
3121
3122#define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003
3123#define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001
3124
3125#define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004
3126#define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
3127#define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0
3128static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)

--- 74 unchanged lines hidden (view full) ---

3203#define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0
3204static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val)
3205{
3206 return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK;
3207}
3208
3209#define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073
3210#define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004
3211#define A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS 0x00000008
2117
2118#define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074
2119#define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
2120#define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
2121static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2122{
2123 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2124}

--- 155 unchanged lines hidden (view full) ---

2280#define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88
2281
2282#define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a
2283
2284#define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b
2285
2286#define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c
2287
3212
3213#define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074
3214#define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
3215#define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
3216static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
3217{
3218 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
3219}

--- 155 unchanged lines hidden (view full) ---

3375#define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88
3376
3377#define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a
3378
3379#define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b
3380
3381#define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c
3382
3383#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e8e
3384
3385#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e8f
3386
3387#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e90
3388
3389#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e91
3390
3391#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e92
3392
3393#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e93
3394
3395#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e94
3396
2288#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95
2289
2290#define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00
2291
2292#define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04
2293
2294#define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05
2295
2296#define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e
2297
3397#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95
3398
3399#define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00
3400
3401#define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04
3402
3403#define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05
3404
3405#define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e
3406
3407#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e06
3408
3409#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e07
3410
3411#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e08
3412
3413#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e09
3414
3415#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e0a
3416
3417#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e0b
3418
3419#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e0c
3420
3421#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e0d
3422
2298#define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0
2299#define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
2300#define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
2301static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
2302{
2303 return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
2304}
2305#define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040

--- 238 unchanged lines hidden (view full) ---

2544
2545#define REG_A4XX_PC_BINNING_COMMAND 0x00000d00
2546#define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001
2547
2548#define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c
2549
2550#define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10
2551
3423#define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0
3424#define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
3425#define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
3426static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
3427{
3428 return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
3429}
3430#define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040

--- 238 unchanged lines hidden (view full) ---

3669
3670#define REG_A4XX_PC_BINNING_COMMAND 0x00000d00
3671#define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001
3672
3673#define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c
3674
3675#define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10
3676
3677#define REG_A4XX_PC_PERFCTR_PC_SEL_1 0x00000d11
3678
3679#define REG_A4XX_PC_PERFCTR_PC_SEL_2 0x00000d12
3680
3681#define REG_A4XX_PC_PERFCTR_PC_SEL_3 0x00000d13
3682
3683#define REG_A4XX_PC_PERFCTR_PC_SEL_4 0x00000d14
3684
3685#define REG_A4XX_PC_PERFCTR_PC_SEL_5 0x00000d15
3686
3687#define REG_A4XX_PC_PERFCTR_PC_SEL_6 0x00000d16
3688
2552#define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17
2553
2554#define REG_A4XX_PC_BIN_BASE 0x000021c0
2555
2556#define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4
2557#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f
2558#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0
2559static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
2560{
2561 return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK;
2562}
2563#define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
2564#define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
2565#define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
2566
3689#define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17
3690
3691#define REG_A4XX_PC_BIN_BASE 0x000021c0
3692
3693#define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4
3694#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f
3695#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0
3696static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
3697{
3698 return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK;
3699}
3700#define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
3701#define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
3702#define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
3703
2567#define REG_A4XX_UNKNOWN_21C5 0x000021c5
3704#define REG_A4XX_PC_PRIM_VTX_CNTL2 0x000021c5
3705#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK 0x00000007
3706#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT 0
3707static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
3708{
3709 return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK;
3710}
3711#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK 0x00000038
3712#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT 3
3713static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
3714{
3715 return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK;
3716}
3717#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE 0x00000040
2568
2569#define REG_A4XX_PC_RESTART_INDEX 0x000021c6
2570
2571#define REG_A4XX_PC_GS_PARAM 0x000021e5
2572#define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
2573#define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0
2574static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
2575{

--- 65 unchanged lines hidden (view full) ---

2641#define REG_A4XX_UNKNOWN_0EC2 0x00000ec2
2642
2643#define REG_A4XX_UNKNOWN_2001 0x00002001
2644
2645#define REG_A4XX_UNKNOWN_209B 0x0000209b
2646
2647#define REG_A4XX_UNKNOWN_20EF 0x000020ef
2648
3718
3719#define REG_A4XX_PC_RESTART_INDEX 0x000021c6
3720
3721#define REG_A4XX_PC_GS_PARAM 0x000021e5
3722#define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
3723#define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0
3724static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
3725{

--- 65 unchanged lines hidden (view full) ---

3791#define REG_A4XX_UNKNOWN_0EC2 0x00000ec2
3792
3793#define REG_A4XX_UNKNOWN_2001 0x00002001
3794
3795#define REG_A4XX_UNKNOWN_209B 0x0000209b
3796
3797#define REG_A4XX_UNKNOWN_20EF 0x000020ef
3798
2649#define REG_A4XX_UNKNOWN_20F0 0x000020f0
2650
2651#define REG_A4XX_UNKNOWN_20F1 0x000020f1
2652
2653#define REG_A4XX_UNKNOWN_20F2 0x000020f2
2654
2655#define REG_A4XX_UNKNOWN_20F7 0x000020f7
2656#define A4XX_UNKNOWN_20F7__MASK 0xffffffff
2657#define A4XX_UNKNOWN_20F7__SHIFT 0
2658static inline uint32_t A4XX_UNKNOWN_20F7(float val)
2659{
2660 return ((fui(val)) << A4XX_UNKNOWN_20F7__SHIFT) & A4XX_UNKNOWN_20F7__MASK;
2661}
2662
2663#define REG_A4XX_UNKNOWN_2152 0x00002152
2664
2665#define REG_A4XX_UNKNOWN_2153 0x00002153
2666
2667#define REG_A4XX_UNKNOWN_2154 0x00002154
2668
2669#define REG_A4XX_UNKNOWN_2155 0x00002155
2670

--- 44 unchanged lines hidden (view full) ---

2715 return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK;
2716}
2717#define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
2718#define A4XX_TEX_SAMP_0_ANISO__SHIFT 14
2719static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val)
2720{
2721 return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK;
2722}
3799#define REG_A4XX_UNKNOWN_2152 0x00002152
3800
3801#define REG_A4XX_UNKNOWN_2153 0x00002153
3802
3803#define REG_A4XX_UNKNOWN_2154 0x00002154
3804
3805#define REG_A4XX_UNKNOWN_2155 0x00002155
3806

--- 44 unchanged lines hidden (view full) ---

3851 return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK;
3852}
3853#define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
3854#define A4XX_TEX_SAMP_0_ANISO__SHIFT 14
3855static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val)
3856{
3857 return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK;
3858}
3859#define A4XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
3860#define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
3861static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val)
3862{
3863 return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS__MASK;
3864}
2723
2724#define REG_A4XX_TEX_SAMP_1 0x00000001
2725#define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
2726#define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
2727static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
2728{
2729 return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
2730}
3865
3866#define REG_A4XX_TEX_SAMP_1 0x00000001
3867#define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
3868#define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
3869static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
3870{
3871 return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
3872}
3873#define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
2731#define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
2732#define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
2733#define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
2734#define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
2735static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val)
2736{
2737 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK;
2738}

--- 52 unchanged lines hidden (view full) ---

2791
2792#define REG_A4XX_TEX_CONST_1 0x00000001
2793#define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff
2794#define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0
2795static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val)
2796{
2797 return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK;
2798}
3874#define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
3875#define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
3876#define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
3877#define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
3878static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val)
3879{
3880 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK;
3881}

--- 52 unchanged lines hidden (view full) ---

3934
3935#define REG_A4XX_TEX_CONST_1 0x00000001
3936#define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff
3937#define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0
3938static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val)
3939{
3940 return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK;
3941}
2799#define A4XX_TEX_CONST_1_WIDTH__MASK 0x1fff8000
3942#define A4XX_TEX_CONST_1_WIDTH__MASK 0x3fff8000
2800#define A4XX_TEX_CONST_1_WIDTH__SHIFT 15
2801static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
2802{
2803 return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK;
2804}
2805
2806#define REG_A4XX_TEX_CONST_2 0x00000002
2807#define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f

--- 54 unchanged lines hidden --- 		3943#define A4XX_TEX_CONST_1_WIDTH__SHIFT 15
3944static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
3945{
3946 return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK;
3947}
3948
3949#define REG_A4XX_TEX_CONST_2 0x00000002
3950#define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f

--- 54 unchanged lines hidden ---