a4xx.xml.h (4b4193256c8d3bc3a5397b5cd9494c2ad386317d) a4xx.xml.h (cc4c26d4ae4e458669d46ff69f16ac0c74f7cd49)
1#ifndef A4XX_XML
2#define A4XX_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
1#ifndef A4XX_XML
2#define A4XX_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
12- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
13- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
14- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
15- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
16- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
17- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
18- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
19- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
20- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
21- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
22- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
23- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
11- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24
24
25Copyright (C) 2013-2020 by the following authors:
25Copyright (C) 2013-2021 by the following authors:
26- Rob Clark <robdclark@gmail.com> (robclark)
27- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
29Permission is hereby granted, free of charge, to any person obtaining
30a copy of this software and associated documentation files (the
31"Software"), to deal in the Software without restriction, including
32without limitation the rights to use, copy, modify, merge, publish,
33distribute, sublicense, and/or sell copies of the Software, and to

--- 1046 unchanged lines hidden (view full) ---

1080static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val)
1081{
1082 return ((val) << A4XX_RB_BLEND_RED_SINT__SHIFT) & A4XX_RB_BLEND_RED_SINT__MASK;
1083}
1084#define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
1085#define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
1086static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
1087{
26- Rob Clark <robdclark@gmail.com> (robclark)
27- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
29Permission is hereby granted, free of charge, to any person obtaining
30a copy of this software and associated documentation files (the
31"Software"), to deal in the Software without restriction, including
32without limitation the rights to use, copy, modify, merge, publish,
33distribute, sublicense, and/or sell copies of the Software, and to

--- 1046 unchanged lines hidden (view full) ---

1080static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val)
1081{
1082 return ((val) << A4XX_RB_BLEND_RED_SINT__SHIFT) & A4XX_RB_BLEND_RED_SINT__MASK;
1083}
1084#define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
1085#define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
1086static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
1087{
1088 return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
1088 return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
1089}
1090
1091#define REG_A4XX_RB_BLEND_RED_F32 0x000020f1
1092#define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff
1093#define A4XX_RB_BLEND_RED_F32__SHIFT 0
1094static inline uint32_t A4XX_RB_BLEND_RED_F32(float val)
1095{
1096 return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK;

--- 11 unchanged lines hidden (view full) ---

1108static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val)
1109{
1110 return ((val) << A4XX_RB_BLEND_GREEN_SINT__SHIFT) & A4XX_RB_BLEND_GREEN_SINT__MASK;
1111}
1112#define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
1113#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
1114static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
1115{
1089}
1090
1091#define REG_A4XX_RB_BLEND_RED_F32 0x000020f1
1092#define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff
1093#define A4XX_RB_BLEND_RED_F32__SHIFT 0
1094static inline uint32_t A4XX_RB_BLEND_RED_F32(float val)
1095{
1096 return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK;

--- 11 unchanged lines hidden (view full) ---

1108static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val)
1109{
1110 return ((val) << A4XX_RB_BLEND_GREEN_SINT__SHIFT) & A4XX_RB_BLEND_GREEN_SINT__MASK;
1111}
1112#define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
1113#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
1114static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
1115{
1116 return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
1116 return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
1117}
1118
1119#define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3
1120#define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
1121#define A4XX_RB_BLEND_GREEN_F32__SHIFT 0
1122static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val)
1123{
1124 return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK;

--- 11 unchanged lines hidden (view full) ---

1136static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val)
1137{
1138 return ((val) << A4XX_RB_BLEND_BLUE_SINT__SHIFT) & A4XX_RB_BLEND_BLUE_SINT__MASK;
1139}
1140#define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
1141#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
1142static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
1143{
1117}
1118
1119#define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3
1120#define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
1121#define A4XX_RB_BLEND_GREEN_F32__SHIFT 0
1122static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val)
1123{
1124 return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK;

--- 11 unchanged lines hidden (view full) ---

1136static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val)
1137{
1138 return ((val) << A4XX_RB_BLEND_BLUE_SINT__SHIFT) & A4XX_RB_BLEND_BLUE_SINT__MASK;
1139}
1140#define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
1141#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
1142static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
1143{
1144 return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
1144 return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
1145}
1146
1147#define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5
1148#define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
1149#define A4XX_RB_BLEND_BLUE_F32__SHIFT 0
1150static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val)
1151{
1152 return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK;

--- 11 unchanged lines hidden (view full) ---

1164static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val)
1165{
1166 return ((val) << A4XX_RB_BLEND_ALPHA_SINT__SHIFT) & A4XX_RB_BLEND_ALPHA_SINT__MASK;
1167}
1168#define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
1169#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
1170static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
1171{
1145}
1146
1147#define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5
1148#define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
1149#define A4XX_RB_BLEND_BLUE_F32__SHIFT 0
1150static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val)
1151{
1152 return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK;

--- 11 unchanged lines hidden (view full) ---

1164static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val)
1165{
1166 return ((val) << A4XX_RB_BLEND_ALPHA_SINT__SHIFT) & A4XX_RB_BLEND_ALPHA_SINT__MASK;
1167}
1168#define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
1169#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
1170static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
1171{
1172 return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
1172 return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
1173}
1174
1175#define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7
1176#define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
1177#define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0
1178static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val)
1179{
1180 return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK;

--- 3095 unchanged lines hidden --- 		1173}
1174
1175#define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7
1176#define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
1177#define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0
1178static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val)
1179{
1180 return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK;

--- 3095 unchanged lines hidden ---