a3xx.xml.h (e5451c8f8330e03ad3cfa16048b4daf961af434f) a3xx.xml.h (a2272e48eef02869dc3fa031720f36dd4cb05e4f)
1#ifndef A3XX_XML
2#define A3XX_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
1#ifndef A3XX_XML
2#define A3XX_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31)
16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48)
18- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
19
18- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
19
20Copyright (C) 2013-2015 by the following authors:
20Copyright (C) 2013-2016 by the following authors:
21- Rob Clark <robdclark@gmail.com> (robclark)
21- Rob Clark <robdclark@gmail.com> (robclark)
22- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
22
23Permission is hereby granted, free of charge, to any person obtaining
24a copy of this software and associated documentation files (the
25"Software"), to deal in the Software without restriction, including
26without limitation the rights to use, copy, modify, merge, publish,
27distribute, sublicense, and/or sell copies of the Software, and to
28permit persons to whom the Software is furnished to do so, subject to
29the following conditions:

--- 76 unchanged lines hidden (view full) ---

106 VFMT_8_SINT = 48,
107 VFMT_8_8_SINT = 49,
108 VFMT_8_8_8_SINT = 50,
109 VFMT_8_8_8_8_SINT = 51,
110 VFMT_8_SNORM = 52,
111 VFMT_8_8_SNORM = 53,
112 VFMT_8_8_8_SNORM = 54,
113 VFMT_8_8_8_8_SNORM = 55,
23
24Permission is hereby granted, free of charge, to any person obtaining
25a copy of this software and associated documentation files (the
26"Software"), to deal in the Software without restriction, including
27without limitation the rights to use, copy, modify, merge, publish,
28distribute, sublicense, and/or sell copies of the Software, and to
29permit persons to whom the Software is furnished to do so, subject to
30the following conditions:

--- 76 unchanged lines hidden (view full) ---

107 VFMT_8_SINT = 48,
108 VFMT_8_8_SINT = 49,
109 VFMT_8_8_8_SINT = 50,
110 VFMT_8_8_8_8_SINT = 51,
111 VFMT_8_SNORM = 52,
112 VFMT_8_8_SNORM = 53,
113 VFMT_8_8_8_SNORM = 54,
114 VFMT_8_8_8_8_SNORM = 55,
114 VFMT_10_10_10_2_UINT = 60,
115 VFMT_10_10_10_2_UNORM = 61,
116 VFMT_10_10_10_2_SINT = 62,
117 VFMT_10_10_10_2_SNORM = 63,
115 VFMT_10_10_10_2_UINT = 56,
116 VFMT_10_10_10_2_UNORM = 57,
117 VFMT_10_10_10_2_SINT = 58,
118 VFMT_10_10_10_2_SNORM = 59,
119 VFMT_2_10_10_10_UINT = 60,
120 VFMT_2_10_10_10_UNORM = 61,
121 VFMT_2_10_10_10_SINT = 62,
122 VFMT_2_10_10_10_SNORM = 63,
118};
119
120enum a3xx_tex_fmt {
121 TFMT_5_6_5_UNORM = 4,
122 TFMT_5_5_5_1_UNORM = 5,
123 TFMT_4_4_4_4_UNORM = 7,
124 TFMT_Z16_UNORM = 9,
125 TFMT_X8Z24_UNORM = 10,

--- 7 unchanged lines hidden (view full) ---

133 TFMT_I420_V = 27,
134 TFMT_ATC_RGB = 32,
135 TFMT_ATC_RGBA_EXPLICIT = 33,
136 TFMT_ETC1 = 34,
137 TFMT_ATC_RGBA_INTERPOLATED = 35,
138 TFMT_DXT1 = 36,
139 TFMT_DXT3 = 37,
140 TFMT_DXT5 = 38,
123};
124
125enum a3xx_tex_fmt {
126 TFMT_5_6_5_UNORM = 4,
127 TFMT_5_5_5_1_UNORM = 5,
128 TFMT_4_4_4_4_UNORM = 7,
129 TFMT_Z16_UNORM = 9,
130 TFMT_X8Z24_UNORM = 10,

--- 7 unchanged lines hidden (view full) ---

138 TFMT_I420_V = 27,
139 TFMT_ATC_RGB = 32,
140 TFMT_ATC_RGBA_EXPLICIT = 33,
141 TFMT_ETC1 = 34,
142 TFMT_ATC_RGBA_INTERPOLATED = 35,
143 TFMT_DXT1 = 36,
144 TFMT_DXT3 = 37,
145 TFMT_DXT5 = 38,
146 TFMT_2_10_10_10_UNORM = 40,
141 TFMT_10_10_10_2_UNORM = 41,
142 TFMT_9_9_9_E5_FLOAT = 42,
143 TFMT_11_11_10_FLOAT = 43,
144 TFMT_A8_UNORM = 44,
147 TFMT_10_10_10_2_UNORM = 41,
148 TFMT_9_9_9_E5_FLOAT = 42,
149 TFMT_11_11_10_FLOAT = 43,
150 TFMT_A8_UNORM = 44,
151 TFMT_L8_UNORM = 45,
145 TFMT_L8_A8_UNORM = 47,
146 TFMT_8_UNORM = 48,
147 TFMT_8_8_UNORM = 49,
148 TFMT_8_8_8_UNORM = 50,
149 TFMT_8_8_8_8_UNORM = 51,
150 TFMT_8_SNORM = 52,
151 TFMT_8_8_SNORM = 53,
152 TFMT_8_8_8_SNORM = 54,

--- 25 unchanged lines hidden (view full) ---

178 TFMT_32_32_FLOAT = 85,
179 TFMT_32_32_32_32_FLOAT = 87,
180 TFMT_32_UINT = 88,
181 TFMT_32_32_UINT = 89,
182 TFMT_32_32_32_32_UINT = 91,
183 TFMT_32_SINT = 92,
184 TFMT_32_32_SINT = 93,
185 TFMT_32_32_32_32_SINT = 95,
152 TFMT_L8_A8_UNORM = 47,
153 TFMT_8_UNORM = 48,
154 TFMT_8_8_UNORM = 49,
155 TFMT_8_8_8_UNORM = 50,
156 TFMT_8_8_8_8_UNORM = 51,
157 TFMT_8_SNORM = 52,
158 TFMT_8_8_SNORM = 53,
159 TFMT_8_8_8_SNORM = 54,

--- 25 unchanged lines hidden (view full) ---

185 TFMT_32_32_FLOAT = 85,
186 TFMT_32_32_32_32_FLOAT = 87,
187 TFMT_32_UINT = 88,
188 TFMT_32_32_UINT = 89,
189 TFMT_32_32_32_32_UINT = 91,
190 TFMT_32_SINT = 92,
191 TFMT_32_32_SINT = 93,
192 TFMT_32_32_32_32_SINT = 95,
193 TFMT_2_10_10_10_UINT = 96,
194 TFMT_10_10_10_2_UINT = 97,
186 TFMT_ETC2_RG11_SNORM = 112,
187 TFMT_ETC2_RG11_UNORM = 113,
188 TFMT_ETC2_R11_SNORM = 114,
189 TFMT_ETC2_R11_UNORM = 115,
190 TFMT_ETC2_RGBA8 = 116,
191 TFMT_ETC2_RGB8A1 = 117,
192 TFMT_ETC2_RGB8 = 118,
193};

--- 16 unchanged lines hidden (view full) ---

210 RB_R8G8B8A8_SNORM = 9,
211 RB_R8G8B8A8_UINT = 10,
212 RB_R8G8B8A8_SINT = 11,
213 RB_R8G8_UNORM = 12,
214 RB_R8G8_SNORM = 13,
215 RB_R8_UINT = 14,
216 RB_R8_SINT = 15,
217 RB_R10G10B10A2_UNORM = 16,
195 TFMT_ETC2_RG11_SNORM = 112,
196 TFMT_ETC2_RG11_UNORM = 113,
197 TFMT_ETC2_R11_SNORM = 114,
198 TFMT_ETC2_R11_UNORM = 115,
199 TFMT_ETC2_RGBA8 = 116,
200 TFMT_ETC2_RGB8A1 = 117,
201 TFMT_ETC2_RGB8 = 118,
202};

--- 16 unchanged lines hidden (view full) ---

219 RB_R8G8B8A8_SNORM = 9,
220 RB_R8G8B8A8_UINT = 10,
221 RB_R8G8B8A8_SINT = 11,
222 RB_R8G8_UNORM = 12,
223 RB_R8G8_SNORM = 13,
224 RB_R8_UINT = 14,
225 RB_R8_SINT = 15,
226 RB_R10G10B10A2_UNORM = 16,
227 RB_A2R10G10B10_UNORM = 17,
228 RB_R10G10B10A2_UINT = 18,
229 RB_A2R10G10B10_UINT = 19,
218 RB_A8_UNORM = 20,
219 RB_R8_UNORM = 21,
220 RB_R16_FLOAT = 24,
221 RB_R16G16_FLOAT = 25,
222 RB_R16G16B16A16_FLOAT = 27,
223 RB_R11G11B10_FLOAT = 28,
224 RB_R16_SNORM = 32,
225 RB_R16G16_SNORM = 33,

--- 13 unchanged lines hidden (view full) ---

239 RB_R32_SINT = 52,
240 RB_R32G32_SINT = 53,
241 RB_R32G32B32A32_SINT = 55,
242 RB_R32_UINT = 56,
243 RB_R32G32_UINT = 57,
244 RB_R32G32B32A32_UINT = 59,
245};
246
230 RB_A8_UNORM = 20,
231 RB_R8_UNORM = 21,
232 RB_R16_FLOAT = 24,
233 RB_R16G16_FLOAT = 25,
234 RB_R16G16B16A16_FLOAT = 27,
235 RB_R11G11B10_FLOAT = 28,
236 RB_R16_SNORM = 32,
237 RB_R16G16_SNORM = 33,

--- 13 unchanged lines hidden (view full) ---

251 RB_R32_SINT = 52,
252 RB_R32G32_SINT = 53,
253 RB_R32G32B32A32_SINT = 55,
254 RB_R32_UINT = 56,
255 RB_R32G32_UINT = 57,
256 RB_R32G32B32A32_UINT = 59,
257};
258
259enum a3xx_cp_perfcounter_select {
260 CP_ALWAYS_COUNT = 0,
261 CP_AHB_PFPTRANS_WAIT = 3,
262 CP_AHB_NRTTRANS_WAIT = 6,
263 CP_CSF_NRT_READ_WAIT = 8,
264 CP_CSF_I1_FIFO_FULL = 9,
265 CP_CSF_I2_FIFO_FULL = 10,
266 CP_CSF_ST_FIFO_FULL = 11,
267 CP_RESERVED_12 = 12,
268 CP_CSF_RING_ROQ_FULL = 13,
269 CP_CSF_I1_ROQ_FULL = 14,
270 CP_CSF_I2_ROQ_FULL = 15,
271 CP_CSF_ST_ROQ_FULL = 16,
272 CP_RESERVED_17 = 17,
273 CP_MIU_TAG_MEM_FULL = 18,
274 CP_MIU_NRT_WRITE_STALLED = 22,
275 CP_MIU_NRT_READ_STALLED = 23,
276 CP_ME_REGS_RB_DONE_FIFO_FULL = 26,
277 CP_ME_REGS_VS_EVENT_FIFO_FULL = 27,
278 CP_ME_REGS_PS_EVENT_FIFO_FULL = 28,
279 CP_ME_REGS_CF_EVENT_FIFO_FULL = 29,
280 CP_ME_MICRO_RB_STARVED = 30,
281 CP_AHB_RBBM_DWORD_SENT = 40,
282 CP_ME_BUSY_CLOCKS = 41,
283 CP_ME_WAIT_CONTEXT_AVAIL = 42,
284 CP_PFP_TYPE0_PACKET = 43,
285 CP_PFP_TYPE3_PACKET = 44,
286 CP_CSF_RB_WPTR_NEQ_RPTR = 45,
287 CP_CSF_I1_SIZE_NEQ_ZERO = 46,
288 CP_CSF_I2_SIZE_NEQ_ZERO = 47,
289 CP_CSF_RBI1I2_FETCHING = 48,
290};
291
292enum a3xx_gras_tse_perfcounter_select {
293 GRAS_TSEPERF_INPUT_PRIM = 0,
294 GRAS_TSEPERF_INPUT_NULL_PRIM = 1,
295 GRAS_TSEPERF_TRIVAL_REJ_PRIM = 2,
296 GRAS_TSEPERF_CLIPPED_PRIM = 3,
297 GRAS_TSEPERF_NEW_PRIM = 4,
298 GRAS_TSEPERF_ZERO_AREA_PRIM = 5,
299 GRAS_TSEPERF_FACENESS_CULLED_PRIM = 6,
300 GRAS_TSEPERF_ZERO_PIXEL_PRIM = 7,
301 GRAS_TSEPERF_OUTPUT_NULL_PRIM = 8,
302 GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM = 9,
303 GRAS_TSEPERF_PRE_CLIP_PRIM = 10,
304 GRAS_TSEPERF_POST_CLIP_PRIM = 11,
305 GRAS_TSEPERF_WORKING_CYCLES = 12,
306 GRAS_TSEPERF_PC_STARVE = 13,
307 GRAS_TSERASPERF_STALL = 14,
308};
309
310enum a3xx_gras_ras_perfcounter_select {
311 GRAS_RASPERF_16X16_TILES = 0,
312 GRAS_RASPERF_8X8_TILES = 1,
313 GRAS_RASPERF_4X4_TILES = 2,
314 GRAS_RASPERF_WORKING_CYCLES = 3,
315 GRAS_RASPERF_STALL_CYCLES_BY_RB = 4,
316 GRAS_RASPERF_STALL_CYCLES_BY_VSC = 5,
317 GRAS_RASPERF_STARVE_CYCLES_BY_TSE = 6,
318};
319
320enum a3xx_hlsq_perfcounter_select {
321 HLSQ_PERF_SP_VS_CONSTANT = 0,
322 HLSQ_PERF_SP_VS_INSTRUCTIONS = 1,
323 HLSQ_PERF_SP_FS_CONSTANT = 2,
324 HLSQ_PERF_SP_FS_INSTRUCTIONS = 3,
325 HLSQ_PERF_TP_STATE = 4,
326 HLSQ_PERF_QUADS = 5,
327 HLSQ_PERF_PIXELS = 6,
328 HLSQ_PERF_VERTICES = 7,
329 HLSQ_PERF_FS8_THREADS = 8,
330 HLSQ_PERF_FS16_THREADS = 9,
331 HLSQ_PERF_FS32_THREADS = 10,
332 HLSQ_PERF_VS8_THREADS = 11,
333 HLSQ_PERF_VS16_THREADS = 12,
334 HLSQ_PERF_SP_VS_DATA_BYTES = 13,
335 HLSQ_PERF_SP_FS_DATA_BYTES = 14,
336 HLSQ_PERF_ACTIVE_CYCLES = 15,
337 HLSQ_PERF_STALL_CYCLES_SP_STATE = 16,
338 HLSQ_PERF_STALL_CYCLES_SP_VS = 17,
339 HLSQ_PERF_STALL_CYCLES_SP_FS = 18,
340 HLSQ_PERF_STALL_CYCLES_UCHE = 19,
341 HLSQ_PERF_RBBM_LOAD_CYCLES = 20,
342 HLSQ_PERF_DI_TO_VS_START_SP0 = 21,
343 HLSQ_PERF_DI_TO_FS_START_SP0 = 22,
344 HLSQ_PERF_VS_START_TO_DONE_SP0 = 23,
345 HLSQ_PERF_FS_START_TO_DONE_SP0 = 24,
346 HLSQ_PERF_SP_STATE_COPY_CYCLES_VS = 25,
347 HLSQ_PERF_SP_STATE_COPY_CYCLES_FS = 26,
348 HLSQ_PERF_UCHE_LATENCY_CYCLES = 27,
349 HLSQ_PERF_UCHE_LATENCY_COUNT = 28,
350};
351
352enum a3xx_pc_perfcounter_select {
353 PC_PCPERF_VISIBILITY_STREAMS = 0,
354 PC_PCPERF_TOTAL_INSTANCES = 1,
355 PC_PCPERF_PRIMITIVES_PC_VPC = 2,
356 PC_PCPERF_PRIMITIVES_KILLED_BY_VS = 3,
357 PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS = 4,
358 PC_PCPERF_DRAWCALLS_KILLED_BY_VS = 5,
359 PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS = 6,
360 PC_PCPERF_VERTICES_TO_VFD = 7,
361 PC_PCPERF_REUSED_VERTICES = 8,
362 PC_PCPERF_CYCLES_STALLED_BY_VFD = 9,
363 PC_PCPERF_CYCLES_STALLED_BY_TSE = 10,
364 PC_PCPERF_CYCLES_STALLED_BY_VBIF = 11,
365 PC_PCPERF_CYCLES_IS_WORKING = 12,
366};
367
368enum a3xx_rb_perfcounter_select {
369 RB_RBPERF_ACTIVE_CYCLES_ANY = 0,
370 RB_RBPERF_ACTIVE_CYCLES_ALL = 1,
371 RB_RBPERF_STARVE_CYCLES_BY_SP = 2,
372 RB_RBPERF_STARVE_CYCLES_BY_RAS = 3,
373 RB_RBPERF_STARVE_CYCLES_BY_MARB = 4,
374 RB_RBPERF_STALL_CYCLES_BY_MARB = 5,
375 RB_RBPERF_STALL_CYCLES_BY_HLSQ = 6,
376 RB_RBPERF_RB_MARB_DATA = 7,
377 RB_RBPERF_SP_RB_QUAD = 8,
378 RB_RBPERF_RAS_EARLY_Z_QUADS = 9,
379 RB_RBPERF_GMEM_CH0_READ = 10,
380 RB_RBPERF_GMEM_CH1_READ = 11,
381 RB_RBPERF_GMEM_CH0_WRITE = 12,
382 RB_RBPERF_GMEM_CH1_WRITE = 13,
383 RB_RBPERF_CP_CONTEXT_DONE = 14,
384 RB_RBPERF_CP_CACHE_FLUSH = 15,
385 RB_RBPERF_CP_ZPASS_DONE = 16,
386};
387
388enum a3xx_rbbm_perfcounter_select {
389 RBBM_ALAWYS_ON = 0,
390 RBBM_VBIF_BUSY = 1,
391 RBBM_TSE_BUSY = 2,
392 RBBM_RAS_BUSY = 3,
393 RBBM_PC_DCALL_BUSY = 4,
394 RBBM_PC_VSD_BUSY = 5,
395 RBBM_VFD_BUSY = 6,
396 RBBM_VPC_BUSY = 7,
397 RBBM_UCHE_BUSY = 8,
398 RBBM_VSC_BUSY = 9,
399 RBBM_HLSQ_BUSY = 10,
400 RBBM_ANY_RB_BUSY = 11,
401 RBBM_ANY_TEX_BUSY = 12,
402 RBBM_ANY_USP_BUSY = 13,
403 RBBM_ANY_MARB_BUSY = 14,
404 RBBM_ANY_ARB_BUSY = 15,
405 RBBM_AHB_STATUS_BUSY = 16,
406 RBBM_AHB_STATUS_STALLED = 17,
407 RBBM_AHB_STATUS_TXFR = 18,
408 RBBM_AHB_STATUS_TXFR_SPLIT = 19,
409 RBBM_AHB_STATUS_TXFR_ERROR = 20,
410 RBBM_AHB_STATUS_LONG_STALL = 21,
411 RBBM_RBBM_STATUS_MASKED = 22,
412};
413
247enum a3xx_sp_perfcounter_select {
414enum a3xx_sp_perfcounter_select {
415 SP_LM_LOAD_INSTRUCTIONS = 0,
416 SP_LM_STORE_INSTRUCTIONS = 1,
417 SP_LM_ATOMICS = 2,
418 SP_UCHE_LOAD_INSTRUCTIONS = 3,
419 SP_UCHE_STORE_INSTRUCTIONS = 4,
420 SP_UCHE_ATOMICS = 5,
421 SP_VS_TEX_INSTRUCTIONS = 6,
422 SP_VS_CFLOW_INSTRUCTIONS = 7,
423 SP_VS_EFU_INSTRUCTIONS = 8,
424 SP_VS_FULL_ALU_INSTRUCTIONS = 9,
425 SP_VS_HALF_ALU_INSTRUCTIONS = 10,
426 SP_FS_TEX_INSTRUCTIONS = 11,
248 SP_FS_CFLOW_INSTRUCTIONS = 12,
427 SP_FS_CFLOW_INSTRUCTIONS = 12,
428 SP_FS_EFU_INSTRUCTIONS = 13,
249 SP_FS_FULL_ALU_INSTRUCTIONS = 14,
429 SP_FS_FULL_ALU_INSTRUCTIONS = 14,
250 SP0_ICL1_MISSES = 26,
430 SP_FS_HALF_ALU_INSTRUCTIONS = 15,
431 SP_FS_BARY_INSTRUCTIONS = 16,
432 SP_VS_INSTRUCTIONS = 17,
433 SP_FS_INSTRUCTIONS = 18,
434 SP_ADDR_LOCK_COUNT = 19,
435 SP_UCHE_READ_TRANS = 20,
436 SP_UCHE_WRITE_TRANS = 21,
437 SP_EXPORT_VPC_TRANS = 22,
438 SP_EXPORT_RB_TRANS = 23,
439 SP_PIXELS_KILLED = 24,
440 SP_ICL1_REQUESTS = 25,
441 SP_ICL1_MISSES = 26,
442 SP_ICL0_REQUESTS = 27,
443 SP_ICL0_MISSES = 28,
251 SP_ALU_ACTIVE_CYCLES = 29,
444 SP_ALU_ACTIVE_CYCLES = 29,
445 SP_EFU_ACTIVE_CYCLES = 30,
446 SP_STALL_CYCLES_BY_VPC = 31,
447 SP_STALL_CYCLES_BY_TP = 32,
448 SP_STALL_CYCLES_BY_UCHE = 33,
449 SP_STALL_CYCLES_BY_RB = 34,
450 SP_ACTIVE_CYCLES_ANY = 35,
451 SP_ACTIVE_CYCLES_ALL = 36,
252};
253
452};
453
254enum a3xx_rop_code {
255 ROP_CLEAR = 0,
256 ROP_NOR = 1,
257 ROP_AND_INVERTED = 2,
258 ROP_COPY_INVERTED = 3,
259 ROP_AND_REVERSE = 4,
260 ROP_INVERT = 5,
261 ROP_XOR = 6,
262 ROP_NAND = 7,
263 ROP_AND = 8,
264 ROP_EQUIV = 9,
265 ROP_NOOP = 10,
266 ROP_OR_INVERTED = 11,
267 ROP_COPY = 12,
268 ROP_OR_REVERSE = 13,
269 ROP_OR = 14,
270 ROP_SET = 15,
454enum a3xx_tp_perfcounter_select {
455 TPL1_TPPERF_L1_REQUESTS = 0,
456 TPL1_TPPERF_TP0_L1_REQUESTS = 1,
457 TPL1_TPPERF_TP0_L1_MISSES = 2,
458 TPL1_TPPERF_TP1_L1_REQUESTS = 3,
459 TPL1_TPPERF_TP1_L1_MISSES = 4,
460 TPL1_TPPERF_TP2_L1_REQUESTS = 5,
461 TPL1_TPPERF_TP2_L1_MISSES = 6,
462 TPL1_TPPERF_TP3_L1_REQUESTS = 7,
463 TPL1_TPPERF_TP3_L1_MISSES = 8,
464 TPL1_TPPERF_OUTPUT_TEXELS_POINT = 9,
465 TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR = 10,
466 TPL1_TPPERF_OUTPUT_TEXELS_MIP = 11,
467 TPL1_TPPERF_OUTPUT_TEXELS_ANISO = 12,
468 TPL1_TPPERF_BILINEAR_OPS = 13,
469 TPL1_TPPERF_QUADSQUADS_OFFSET = 14,
470 TPL1_TPPERF_QUADQUADS_SHADOW = 15,
471 TPL1_TPPERF_QUADS_ARRAY = 16,
472 TPL1_TPPERF_QUADS_PROJECTION = 17,
473 TPL1_TPPERF_QUADS_GRADIENT = 18,
474 TPL1_TPPERF_QUADS_1D2D = 19,
475 TPL1_TPPERF_QUADS_3DCUBE = 20,
476 TPL1_TPPERF_ZERO_LOD = 21,
477 TPL1_TPPERF_OUTPUT_TEXELS = 22,
478 TPL1_TPPERF_ACTIVE_CYCLES_ANY = 23,
479 TPL1_TPPERF_ACTIVE_CYCLES_ALL = 24,
480 TPL1_TPPERF_STALL_CYCLES_BY_ARB = 25,
481 TPL1_TPPERF_LATENCY = 26,
482 TPL1_TPPERF_LATENCY_TRANS = 27,
271};
272
483};
484
485enum a3xx_vfd_perfcounter_select {
486 VFD_PERF_UCHE_BYTE_FETCHED = 0,
487 VFD_PERF_UCHE_TRANS = 1,
488 VFD_PERF_VPC_BYPASS_COMPONENTS = 2,
489 VFD_PERF_FETCH_INSTRUCTIONS = 3,
490 VFD_PERF_DECODE_INSTRUCTIONS = 4,
491 VFD_PERF_ACTIVE_CYCLES = 5,
492 VFD_PERF_STALL_CYCLES_UCHE = 6,
493 VFD_PERF_STALL_CYCLES_HLSQ = 7,
494 VFD_PERF_STALL_CYCLES_VPC_BYPASS = 8,
495 VFD_PERF_STALL_CYCLES_VPC_ALLOC = 9,
496};
497
498enum a3xx_vpc_perfcounter_select {
499 VPC_PERF_SP_LM_PRIMITIVES = 0,
500 VPC_PERF_COMPONENTS_FROM_SP = 1,
501 VPC_PERF_SP_LM_COMPONENTS = 2,
502 VPC_PERF_ACTIVE_CYCLES = 3,
503 VPC_PERF_STALL_CYCLES_LM = 4,
504 VPC_PERF_STALL_CYCLES_RAS = 5,
505};
506
507enum a3xx_uche_perfcounter_select {
508 UCHE_UCHEPERF_VBIF_READ_BEATS_TP = 0,
509 UCHE_UCHEPERF_VBIF_READ_BEATS_VFD = 1,
510 UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ = 2,
511 UCHE_UCHEPERF_VBIF_READ_BEATS_MARB = 3,
512 UCHE_UCHEPERF_VBIF_READ_BEATS_SP = 4,
513 UCHE_UCHEPERF_READ_REQUESTS_TP = 8,
514 UCHE_UCHEPERF_READ_REQUESTS_VFD = 9,
515 UCHE_UCHEPERF_READ_REQUESTS_HLSQ = 10,
516 UCHE_UCHEPERF_READ_REQUESTS_MARB = 11,
517 UCHE_UCHEPERF_READ_REQUESTS_SP = 12,
518 UCHE_UCHEPERF_WRITE_REQUESTS_MARB = 13,
519 UCHE_UCHEPERF_WRITE_REQUESTS_SP = 14,
520 UCHE_UCHEPERF_TAG_CHECK_FAILS = 15,
521 UCHE_UCHEPERF_EVICTS = 16,
522 UCHE_UCHEPERF_FLUSHES = 17,
523 UCHE_UCHEPERF_VBIF_LATENCY_CYCLES = 18,
524 UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES = 19,
525 UCHE_UCHEPERF_ACTIVE_CYCLES = 20,
526};
527
273enum a3xx_rb_blend_opcode {
274 BLEND_DST_PLUS_SRC = 0,
275 BLEND_SRC_MINUS_DST = 1,
276 BLEND_DST_MINUS_SRC = 2,
277 BLEND_MIN_DST_SRC = 3,
278 BLEND_MAX_DST_SRC = 4,
279};
280

--- 1143 unchanged lines hidden (view full) ---

1424#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE 0x00001000
1425#define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
1426#define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
1427#define A3XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
1428
1429#define REG_A3XX_PC_RESTART_INDEX 0x000021ed
1430
1431#define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200
528enum a3xx_rb_blend_opcode {
529 BLEND_DST_PLUS_SRC = 0,
530 BLEND_SRC_MINUS_DST = 1,
531 BLEND_DST_MINUS_SRC = 2,
532 BLEND_MIN_DST_SRC = 3,
533 BLEND_MAX_DST_SRC = 4,
534};
535

--- 1143 unchanged lines hidden (view full) ---

1679#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE 0x00001000
1680#define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
1681#define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
1682#define A3XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
1683
1684#define REG_A3XX_PC_RESTART_INDEX 0x000021ed
1685
1686#define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200
1432#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
1687#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000030
1433#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
1434static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
1435{
1436 return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
1437}
1438#define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
1688#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
1689static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
1690{
1691 return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
1692}
1693#define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
1694#define A3XX_HLSQ_CONTROL_0_REG_COMPUTEMODE 0x00000100
1439#define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
1440#define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
1695#define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
1696#define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
1697#define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK 0x00fff000
1698#define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT 12
1699static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC(uint32_t val)
1700{
1701 return ((val) << A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK;
1702}
1703#define A3XX_HLSQ_CONTROL_0_REG_FSONLYTEX 0x02000000
1441#define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
1442#define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000
1443#define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27
1444static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
1445{
1446 return ((val) << A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
1447}
1448#define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000
1449#define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000
1450#define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000
1451#define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
1452
1453#define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201
1704#define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
1705#define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000
1706#define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27
1707static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
1708{
1709 return ((val) << A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
1710}
1711#define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000
1712#define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000
1713#define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000
1714#define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
1715
1716#define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201
1454#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040
1717#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x000000c0
1455#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
1456static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
1457{
1458 return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
1459}
1460#define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
1718#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
1719static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
1720{
1721 return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
1722}
1723#define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
1461#define A3XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
1462#define A3XX_HLSQ_CONTROL_1_REG_ZWCOORD 0x02000000
1724#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK 0x00ff0000
1725#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT 16
1726static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(uint32_t val)
1727{
1728 return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK;
1729}
1730#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK 0xff000000
1731#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT 24
1732static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(uint32_t val)
1733{
1734 return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK;
1735}
1463
1464#define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202
1736
1737#define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202
1738#define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK 0x000003fc
1739#define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT 2
1740static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(uint32_t val)
1741{
1742 return ((val) << A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK;
1743}
1744#define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK 0x03fc0000
1745#define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT 18
1746static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID(uint32_t val)
1747{
1748 return ((val) << A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK;
1749}
1465#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
1466#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
1467static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
1468{
1469 return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
1470}
1471
1472#define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203
1473#define A3XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff
1474#define A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0
1475static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
1476{
1477 return ((val) << A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_REGID__MASK;
1478}
1479
1480#define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204
1750#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
1751#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
1752static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
1753{
1754 return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
1755}
1756
1757#define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203
1758#define A3XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff
1759#define A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0
1760static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
1761{
1762 return ((val) << A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_REGID__MASK;
1763}
1764
1765#define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204
1481#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff
1766#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000003ff
1482#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
1483static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
1484{
1485 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
1486}
1767#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
1768static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
1769{
1770 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
1771}
1487#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000
1772#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x001ff000
1488#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12
1489static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
1490{
1491 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK;
1492}
1493#define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
1494#define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24
1495static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
1496{
1497 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
1498}
1499
1500#define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205
1773#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12
1774static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
1775{
1776 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK;
1777}
1778#define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
1779#define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24
1780static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
1781{
1782 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
1783}
1784
1785#define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205
1501#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff
1786#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000003ff
1502#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
1503static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
1504{
1505 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
1506}
1787#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
1788static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
1789{
1790 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
1791}
1507#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000
1792#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x001ff000
1508#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12
1509static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
1510{
1511 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK;
1512}
1513#define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
1514#define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24
1515static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
1516{
1517 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
1518}
1519
1520#define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206
1793#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12
1794static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
1795{
1796 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK;
1797}
1798#define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
1799#define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24
1800static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
1801{
1802 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
1803}
1804
1805#define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206
1521#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff
1806#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x000001ff
1522#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0
1523static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
1524{
1525 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK;
1526}
1807#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0
1808static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
1809{
1810 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK;
1811}
1527#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000
1812#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0x01ff0000
1528#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16
1529static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
1530{
1531 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK;
1532}
1533
1534#define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207
1813#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16
1814static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
1815{
1816 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK;
1817}
1818
1819#define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207
1535#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff
1820#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x000001ff
1536#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0
1537static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
1538{
1539 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK;
1540}
1821#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0
1822static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
1823{
1824 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK;
1825}
1541#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000
1826#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0x01ff0000
1542#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16
1543static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
1544{
1545 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK;
1546}
1547
1548#define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a
1549#define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK 0x00000003

--- 65 unchanged lines hidden (view full) ---

1615#define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xf8000000
1616#define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 27
1617static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
1618{
1619 return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
1620}
1621
1622#define REG_A3XX_VFD_CONTROL_1 0x00002241
1827#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16
1828static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
1829{
1830 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK;
1831}
1832
1833#define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a
1834#define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK 0x00000003

--- 65 unchanged lines hidden (view full) ---

1900#define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xf8000000
1901#define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 27
1902static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
1903{
1904 return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
1905}
1906
1907#define REG_A3XX_VFD_CONTROL_1 0x00002241
1623#define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff
1908#define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000000f
1624#define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
1625static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
1626{
1627 return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
1628}
1909#define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
1910static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
1911{
1912 return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
1913}
1914#define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK 0x000000f0
1915#define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT 4
1916static inline uint32_t A3XX_VFD_CONTROL_1_MAXTHRESHOLD(uint32_t val)
1917{
1918 return ((val) << A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK;
1919}
1920#define A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK 0x00000f00
1921#define A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT 8
1922static inline uint32_t A3XX_VFD_CONTROL_1_MINTHRESHOLD(uint32_t val)
1923{
1924 return ((val) << A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK;
1925}
1629#define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
1630#define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
1631static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
1632{
1633 return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK;
1634}
1635#define A3XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000
1636#define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT 24

--- 366 unchanged lines hidden (view full) ---

2003}
2004#define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002
2005#define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1
2006static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val)
2007{
2008 return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK;
2009}
2010#define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
1926#define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
1927#define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
1928static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
1929{
1930 return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK;
1931}
1932#define A3XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000
1933#define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT 24

--- 366 unchanged lines hidden (view full) ---

2300}
2301#define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002
2302#define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1
2303static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val)
2304{
2305 return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK;
2306}
2307#define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
2308#define A3XX_SP_VS_CTRL_REG0_ALUSCHMODE 0x00000008
2011#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
2012#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
2013static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2014{
2015 return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2016}
2309#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
2310#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
2311static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2312{
2313 return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2314}
2017#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
2315#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
2018#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
2019static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2020{
2021 return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2022}
2316#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
2317static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2318{
2319 return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2320}
2023#define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
2024#define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
2025static inline uint32_t A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
2026{
2027 return ((val) << A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK;
2028}
2029#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
2030#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
2031static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2032{
2033 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
2034}
2035#define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
2321#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
2322#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
2323static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2324{
2325 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
2326}
2327#define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
2036#define A3XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
2037#define A3XX_SP_VS_CTRL_REG0_COMPUTEMODE 0x00800000
2038#define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000
2039#define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24
2040static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val)
2041{
2042 return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK;
2043}
2044
2045#define REG_A3XX_SP_VS_CTRL_REG1 0x000022c5

--- 24 unchanged lines hidden (view full) ---

2070 return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK;
2071}
2072#define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00
2073#define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8
2074static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
2075{
2076 return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
2077}
2328#define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000
2329#define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24
2330static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val)
2331{
2332 return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK;
2333}
2334
2335#define REG_A3XX_SP_VS_CTRL_REG1 0x000022c5

--- 24 unchanged lines hidden (view full) ---

2360 return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK;
2361}
2362#define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00
2363#define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8
2364static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
2365{
2366 return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
2367}
2078#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000
2368#define A3XX_SP_VS_PARAM_REG_POS2DMODE 0x00010000
2369#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0x01f00000
2079#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
2080static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
2081{
2082 return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
2083}
2084
2085static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
2086
2087static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
2370#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
2371static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
2372{
2373 return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
2374}
2375
2376static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
2377
2378static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
2088#define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
2379#define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
2089#define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
2090static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
2091{
2092 return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK;
2093}
2380#define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
2381static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
2382{
2383 return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK;
2384}
2385#define A3XX_SP_VS_OUT_REG_A_HALF 0x00000100
2094#define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
2095#define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
2096static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
2097{
2098 return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
2099}
2386#define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
2387#define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
2388static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
2389{
2390 return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
2391}
2100#define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000
2392#define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
2101#define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
2102static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
2103{
2104 return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK;
2105}
2393#define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
2394static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
2395{
2396 return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK;
2397}
2398#define A3XX_SP_VS_OUT_REG_B_HALF 0x01000000
2106#define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
2107#define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
2108static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
2109{
2110 return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
2111}
2112
2113static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
2114
2115static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
2399#define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
2400#define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
2401static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
2402{
2403 return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
2404}
2405
2406static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
2407
2408static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
2116#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
2409#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x0000007f
2117#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
2118static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
2119{
2120 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
2121}
2410#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
2411static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
2412{
2413 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
2414}
2122#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
2415#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x00007f00
2123#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
2124static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
2125{
2126 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
2127}
2416#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
2417static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
2418{
2419 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
2420}
2128#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
2421#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x007f0000
2129#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
2130static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
2131{
2132 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
2133}
2422#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
2423static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
2424{
2425 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
2426}
2134#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
2427#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0x7f000000
2135#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
2136static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
2137{
2138 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
2139}
2140
2141#define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4
2428#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
2429static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
2430{
2431 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
2432}
2433
2434#define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4
2435#define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK 0x0000ffff
2436#define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT 0
2437static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val)
2438{
2439 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK;
2440}
2142#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2143#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2144static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2145{
2146 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2147}
2148#define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2149#define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2150static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2151{
2152 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2153}
2154
2155#define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5
2156
2157#define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG 0x000022d6
2441#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2442#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2443static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2444{
2445 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2446}
2447#define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2448#define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2449static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2450{
2451 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2452}
2453
2454#define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5
2455
2456#define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG 0x000022d6
2457#define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK 0x000000ff
2458#define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0
2459static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val)
2460{
2461 return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK;
2462}
2463#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00
2464#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8
2465static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val)
2466{
2467 return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK;
2468}
2469#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000
2470#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT 24
2471static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val)
2472{
2473 return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK;
2474}
2158
2159#define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7
2475
2476#define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7
2477#define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK 0x0000001f
2478#define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT 0
2479static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val)
2480{
2481 return ((val) << A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK;
2482}
2483#define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK 0xffffffe0
2484#define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5
2485static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)
2486{
2487 return ((val >> 5) << A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;
2488}
2160
2161#define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8
2162
2163#define REG_A3XX_SP_VS_LENGTH_REG 0x000022df
2164#define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff
2165#define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT 0
2166static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val)
2167{

--- 9 unchanged lines hidden (view full) ---

2177}
2178#define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002
2179#define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1
2180static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val)
2181{
2182 return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK;
2183}
2184#define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
2489
2490#define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8
2491
2492#define REG_A3XX_SP_VS_LENGTH_REG 0x000022df
2493#define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff
2494#define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT 0
2495static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val)
2496{

--- 9 unchanged lines hidden (view full) ---

2506}
2507#define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002
2508#define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1
2509static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val)
2510{
2511 return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK;
2512}
2513#define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
2514#define A3XX_SP_FS_CTRL_REG0_ALUSCHMODE 0x00000008
2185#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
2186#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
2187static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2188{
2189 return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2190}
2515#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
2516#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
2517static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2518{
2519 return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2520}
2191#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
2521#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
2192#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
2193static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2194{
2195 return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2196}
2522#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
2523static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2524{
2525 return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2526}
2197#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
2198#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
2199static inline uint32_t A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
2200{
2201 return ((val) << A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK;
2202}
2527#define A3XX_SP_FS_CTRL_REG0_FSBYPASSENABLE 0x00020000
2528#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP 0x00040000
2529#define A3XX_SP_FS_CTRL_REG0_OUTORDERED 0x00080000
2203#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
2204#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
2205static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2206{
2207 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
2208}
2209#define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
2210#define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000

--- 19 unchanged lines hidden (view full) ---

2230 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK;
2231}
2232#define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x00f00000
2233#define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 20
2234static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
2235{
2236 return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK;
2237}
2530#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
2531#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
2532static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2533{
2534 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
2535}
2536#define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
2537#define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000

--- 19 unchanged lines hidden (view full) ---

2557 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK;
2558}
2559#define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x00f00000
2560#define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 20
2561static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
2562{
2563 return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK;
2564}
2238#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x3f000000
2565#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x7f000000
2239#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24
2240static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val)
2241{
2242 return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK;
2243}
2244
2245#define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2
2566#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24
2567static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val)
2568{
2569 return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK;
2570}
2571
2572#define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2
2573#define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK 0x0000ffff
2574#define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT 0
2575static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val)
2576{
2577 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK;
2578}
2246#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2247#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2248static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2249{
2250 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2251}
2252#define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2253#define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2254static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2255{
2256 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2257}
2258
2259#define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3
2260
2261#define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG 0x000022e4
2579#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2580#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2581static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2582{
2583 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2584}
2585#define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2586#define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2587static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2588{
2589 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2590}
2591
2592#define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3
2593
2594#define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG 0x000022e4
2595#define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK 0x000000ff
2596#define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0
2597static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val)
2598{
2599 return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK;
2600}
2601#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00
2602#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8
2603static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val)
2604{
2605 return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK;
2606}
2607#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000
2608#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT 24
2609static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val)
2610{
2611 return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK;
2612}
2262
2263#define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5
2613
2614#define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5
2615#define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK 0x0000001f
2616#define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT 0
2617static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val)
2618{
2619 return ((val) << A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK;
2620}
2621#define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK 0xffffffe0
2622#define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5
2623static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)
2624{
2625 return ((val >> 5) << A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;
2626}
2264
2265#define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6
2266
2267#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 0x000022e8
2268
2269#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9
2270
2271#define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec

--- 589 unchanged lines hidden --- 		2627
2628#define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6
2629
2630#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 0x000022e8
2631
2632#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9
2633
2634#define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec

--- 589 unchanged lines hidden ---