handlers.c (e39c5add322184de3be052d438dfd24375bfeaea) handlers.c (04d348ae3f0aea6523bc3b0688b5fc90c1c60d0e)
1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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246 if (data & GEN8_GRDOM_MEDIA2) {
247 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
248 if (HAS_BSD2(vgpu->gvt->dev_priv))
249 bitmap |= (1 << VCS2);
250 }
251 return 0;
252}
253
1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

--- 237 unchanged lines hidden (view full) ---

246 if (data & GEN8_GRDOM_MEDIA2) {
247 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
248 if (HAS_BSD2(vgpu->gvt->dev_priv))
249 bitmap |= (1 << VCS2);
250 }
251 return 0;
252}
253
254static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
255 void *p_data, unsigned int bytes)
256{
257 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);
258}
259
260static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
261 void *p_data, unsigned int bytes)
262{
263 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);
264}
265
266static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu,
267 unsigned int offset, void *p_data, unsigned int bytes)
268{
269 write_vreg(vgpu, offset, p_data, bytes);
270
271 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
272 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_ON;
273 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
274 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
275 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
276
277 } else
278 vgpu_vreg(vgpu, PCH_PP_STATUS) &=
279 ~(PP_ON | PP_SEQUENCE_POWER_DOWN
280 | PP_CYCLE_DELAY_ACTIVE);
281 return 0;
282}
283
284static int transconf_mmio_write(struct intel_vgpu *vgpu,
285 unsigned int offset, void *p_data, unsigned int bytes)
286{
287 write_vreg(vgpu, offset, p_data, bytes);
288
289 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
290 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
291 else
292 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
293 return 0;
294}
295
296static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
297 void *p_data, unsigned int bytes)
298{
299 write_vreg(vgpu, offset, p_data, bytes);
300
301 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
302 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
303 else
304 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
305
306 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
307 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
308 else
309 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
310
311 return 0;
312}
313
314static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
315 void *p_data, unsigned int bytes)
316{
317 *(u32 *)p_data = (1 << 17);
318 return 0;
319}
320
321static int dpy_reg_mmio_read_2(struct intel_vgpu *vgpu, unsigned int offset,
322 void *p_data, unsigned int bytes)
323{
324 *(u32 *)p_data = 3;
325 return 0;
326}
327
328static int dpy_reg_mmio_read_3(struct intel_vgpu *vgpu, unsigned int offset,
329 void *p_data, unsigned int bytes)
330{
331 *(u32 *)p_data = (0x2f << 16);
332 return 0;
333}
334
335static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
336 void *p_data, unsigned int bytes)
337{
338 u32 data;
339
340 write_vreg(vgpu, offset, p_data, bytes);
341 data = vgpu_vreg(vgpu, offset);
342
343 if (data & PIPECONF_ENABLE)
344 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
345 else
346 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
347 intel_gvt_check_vblank_emulation(vgpu->gvt);
348 return 0;
349}
350
351static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
352 void *p_data, unsigned int bytes)
353{
354 write_vreg(vgpu, offset, p_data, bytes);
355
356 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
357 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
358 } else {
359 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
360 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
361 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E))
362 &= ~DP_TP_STATUS_AUTOTRAIN_DONE;
363 }
364 return 0;
365}
366
367static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
368 unsigned int offset, void *p_data, unsigned int bytes)
369{
370 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
371 return 0;
372}
373
374#define FDI_LINK_TRAIN_PATTERN1 0
375#define FDI_LINK_TRAIN_PATTERN2 1
376
377static int fdi_auto_training_started(struct intel_vgpu *vgpu)
378{
379 u32 ddi_buf_ctl = vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_E));
380 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
381 u32 tx_ctl = vgpu_vreg(vgpu, DP_TP_CTL(PORT_E));
382
383 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) &&
384 (rx_ctl & FDI_RX_ENABLE) &&
385 (rx_ctl & FDI_AUTO_TRAINING) &&
386 (tx_ctl & DP_TP_CTL_ENABLE) &&
387 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN))
388 return 1;
389 else
390 return 0;
391}
392
393static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
394 enum pipe pipe, unsigned int train_pattern)
395{
396 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;
397 unsigned int fdi_rx_check_bits, fdi_tx_check_bits;
398 unsigned int fdi_rx_train_bits, fdi_tx_train_bits;
399 unsigned int fdi_iir_check_bits;
400
401 fdi_rx_imr = FDI_RX_IMR(pipe);
402 fdi_tx_ctl = FDI_TX_CTL(pipe);
403 fdi_rx_ctl = FDI_RX_CTL(pipe);
404
405 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) {
406 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT;
407 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1;
408 fdi_iir_check_bits = FDI_RX_BIT_LOCK;
409 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) {
410 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT;
411 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2;
412 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK;
413 } else {
414 gvt_err("Invalid train pattern %d\n", train_pattern);
415 return -EINVAL;
416 }
417
418 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits;
419 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits;
420
421 /* If imr bit has been masked */
422 if (vgpu_vreg(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
423 return 0;
424
425 if (((vgpu_vreg(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
426 == fdi_tx_check_bits)
427 && ((vgpu_vreg(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
428 == fdi_rx_check_bits))
429 return 1;
430 else
431 return 0;
432}
433
434#define INVALID_INDEX (~0U)
435
436static unsigned int calc_index(unsigned int offset, unsigned int start,
437 unsigned int next, unsigned int end, i915_reg_t i915_end)
438{
439 unsigned int range = next - start;
440
441 if (!end)
442 end = i915_mmio_reg_offset(i915_end);
443 if (offset < start || offset > end)
444 return INVALID_INDEX;
445 offset -= start;
446 return offset / range;
447}
448
449#define FDI_RX_CTL_TO_PIPE(offset) \
450 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
451
452#define FDI_TX_CTL_TO_PIPE(offset) \
453 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
454
455#define FDI_RX_IMR_TO_PIPE(offset) \
456 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
457
458static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
459 unsigned int offset, void *p_data, unsigned int bytes)
460{
461 i915_reg_t fdi_rx_iir;
462 unsigned int index;
463 int ret;
464
465 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX)
466 index = FDI_RX_CTL_TO_PIPE(offset);
467 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX)
468 index = FDI_TX_CTL_TO_PIPE(offset);
469 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
470 index = FDI_RX_IMR_TO_PIPE(offset);
471 else {
472 gvt_err("Unsupport registers %x\n", offset);
473 return -EINVAL;
474 }
475
476 write_vreg(vgpu, offset, p_data, bytes);
477
478 fdi_rx_iir = FDI_RX_IIR(index);
479
480 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1);
481 if (ret < 0)
482 return ret;
483 if (ret)
484 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
485
486 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2);
487 if (ret < 0)
488 return ret;
489 if (ret)
490 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
491
492 if (offset == _FDI_RXA_CTL)
493 if (fdi_auto_training_started(vgpu))
494 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) |=
495 DP_TP_STATUS_AUTOTRAIN_DONE;
496 return 0;
497}
498
499#define DP_TP_CTL_TO_PORT(offset) \
500 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
501
502static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
503 void *p_data, unsigned int bytes)
504{
505 i915_reg_t status_reg;
506 unsigned int index;
507 u32 data;
508
509 write_vreg(vgpu, offset, p_data, bytes);
510
511 index = DP_TP_CTL_TO_PORT(offset);
512 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
513 if (data == 0x2) {
514 status_reg = DP_TP_STATUS(index);
515 vgpu_vreg(vgpu, status_reg) |= (1 << 25);
516 }
517 return 0;
518}
519
520static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu,
521 unsigned int offset, void *p_data, unsigned int bytes)
522{
523 u32 reg_val;
524 u32 sticky_mask;
525
526 reg_val = *((u32 *)p_data);
527 sticky_mask = GENMASK(27, 26) | (1 << 24);
528
529 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
530 (vgpu_vreg(vgpu, offset) & sticky_mask);
531 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
532 return 0;
533}
534
535static int pch_adpa_mmio_write(struct intel_vgpu *vgpu,
536 unsigned int offset, void *p_data, unsigned int bytes)
537{
538 u32 data;
539
540 write_vreg(vgpu, offset, p_data, bytes);
541 data = vgpu_vreg(vgpu, offset);
542
543 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
544 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
545 return 0;
546}
547
548static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
549 unsigned int offset, void *p_data, unsigned int bytes)
550{
551 u32 data;
552
553 write_vreg(vgpu, offset, p_data, bytes);
554 data = vgpu_vreg(vgpu, offset);
555
556 if (data & FDI_MPHY_IOSFSB_RESET_CTL)
557 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
558 else
559 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
560 return 0;
561}
562
563#define DSPSURF_TO_PIPE(offset) \
564 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
565
566static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
567 void *p_data, unsigned int bytes)
568{
569 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
570 unsigned int index = DSPSURF_TO_PIPE(offset);
571 i915_reg_t surflive_reg = DSPSURFLIVE(index);
572 int flip_event[] = {
573 [PIPE_A] = PRIMARY_A_FLIP_DONE,
574 [PIPE_B] = PRIMARY_B_FLIP_DONE,
575 [PIPE_C] = PRIMARY_C_FLIP_DONE,
576 };
577
578 write_vreg(vgpu, offset, p_data, bytes);
579 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
580
581 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
582 return 0;
583}
584
585#define SPRSURF_TO_PIPE(offset) \
586 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
587
588static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
589 void *p_data, unsigned int bytes)
590{
591 unsigned int index = SPRSURF_TO_PIPE(offset);
592 i915_reg_t surflive_reg = SPRSURFLIVE(index);
593 int flip_event[] = {
594 [PIPE_A] = SPRITE_A_FLIP_DONE,
595 [PIPE_B] = SPRITE_B_FLIP_DONE,
596 [PIPE_C] = SPRITE_C_FLIP_DONE,
597 };
598
599 write_vreg(vgpu, offset, p_data, bytes);
600 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
601
602 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
603 return 0;
604}
605
606static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
607 unsigned int reg)
608{
609 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
610 enum intel_gvt_event_type event;
611
612 if (reg == _DPA_AUX_CH_CTL)
613 event = AUX_CHANNEL_A;
614 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL)
615 event = AUX_CHANNEL_B;
616 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL)
617 event = AUX_CHANNEL_C;
618 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL)
619 event = AUX_CHANNEL_D;
620 else {
621 WARN_ON(true);
622 return -EINVAL;
623 }
624
625 intel_vgpu_trigger_virtual_event(vgpu, event);
626 return 0;
627}
628
629static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
630 unsigned int reg, int len, bool data_valid)
631{
632 /* mark transaction done */
633 value |= DP_AUX_CH_CTL_DONE;
634 value &= ~DP_AUX_CH_CTL_SEND_BUSY;
635 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR;
636
637 if (data_valid)
638 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR;
639 else
640 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR;
641
642 /* message size */
643 value &= ~(0xf << 20);
644 value |= (len << 20);
645 vgpu_vreg(vgpu, reg) = value;
646
647 if (value & DP_AUX_CH_CTL_INTERRUPT)
648 return trigger_aux_channel_interrupt(vgpu, reg);
649 return 0;
650}
651
652static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
653 uint8_t t)
654{
655 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) {
656 /* training pattern 1 for CR */
657 /* set LANE0_CR_DONE, LANE1_CR_DONE */
658 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE;
659 /* set LANE2_CR_DONE, LANE3_CR_DONE */
660 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE;
661 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
662 DPCD_TRAINING_PATTERN_2) {
663 /* training pattern 2 for EQ */
664 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */
665 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE;
666 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED;
667 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */
668 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE;
669 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED;
670 /* set INTERLANE_ALIGN_DONE */
671 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |=
672 DPCD_INTERLANE_ALIGN_DONE;
673 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
674 DPCD_LINK_TRAINING_DISABLED) {
675 /* finish link training */
676 /* set sink status as synchronized */
677 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC;
678 }
679}
680
681#define _REG_HSW_DP_AUX_CH_CTL(dp) \
682 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010)
683
684#define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100)
685
686#define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
687
688#define dpy_is_valid_port(port) \
689 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
690
691static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
692 unsigned int offset, void *p_data, unsigned int bytes)
693{
694 struct intel_vgpu_display *display = &vgpu->display;
695 int msg, addr, ctrl, op, len;
696 int port_index = OFFSET_TO_DP_AUX_PORT(offset);
697 struct intel_vgpu_dpcd_data *dpcd = NULL;
698 struct intel_vgpu_port *port = NULL;
699 u32 data;
700
701 if (!dpy_is_valid_port(port_index)) {
702 gvt_err("GVT(%d): Unsupported DP port access!\n", vgpu->id);
703 return 0;
704 }
705
706 write_vreg(vgpu, offset, p_data, bytes);
707 data = vgpu_vreg(vgpu, offset);
708
709 if (IS_SKYLAKE(vgpu->gvt->dev_priv) &&
710 offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
711 /* SKL DPB/C/D aux ctl register changed */
712 return 0;
713 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) &&
714 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) {
715 /* write to the data registers */
716 return 0;
717 }
718
719 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) {
720 /* just want to clear the sticky bits */
721 vgpu_vreg(vgpu, offset) = 0;
722 return 0;
723 }
724
725 port = &display->ports[port_index];
726 dpcd = port->dpcd;
727
728 /* read out message from DATA1 register */
729 msg = vgpu_vreg(vgpu, offset + 4);
730 addr = (msg >> 8) & 0xffff;
731 ctrl = (msg >> 24) & 0xff;
732 len = msg & 0xff;
733 op = ctrl >> 4;
734
735 if (op == GVT_AUX_NATIVE_WRITE) {
736 int t;
737 uint8_t buf[16];
738
739 if ((addr + len + 1) >= DPCD_SIZE) {
740 /*
741 * Write request exceeds what we supported,
742 * DCPD spec: When a Source Device is writing a DPCD
743 * address not supported by the Sink Device, the Sink
744 * Device shall reply with AUX NACK and “M” equal to
745 * zero.
746 */
747
748 /* NAK the write */
749 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
750 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);
751 return 0;
752 }
753
754 /*
755 * Write request format: (command + address) occupies
756 * 3 bytes, followed by (len + 1) bytes of data.
757 */
758 if (WARN_ON((len + 4) > AUX_BURST_SIZE))
759 return -EINVAL;
760
761 /* unpack data from vreg to buf */
762 for (t = 0; t < 4; t++) {
763 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
764
765 buf[t * 4] = (r >> 24) & 0xff;
766 buf[t * 4 + 1] = (r >> 16) & 0xff;
767 buf[t * 4 + 2] = (r >> 8) & 0xff;
768 buf[t * 4 + 3] = r & 0xff;
769 }
770
771 /* write to virtual DPCD */
772 if (dpcd && dpcd->data_valid) {
773 for (t = 0; t <= len; t++) {
774 int p = addr + t;
775
776 dpcd->data[p] = buf[t];
777 /* check for link training */
778 if (p == DPCD_TRAINING_PATTERN_SET)
779 dp_aux_ch_ctl_link_training(dpcd,
780 buf[t]);
781 }
782 }
783
784 /* ACK the write */
785 vgpu_vreg(vgpu, offset + 4) = 0;
786 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1,
787 dpcd && dpcd->data_valid);
788 return 0;
789 }
790
791 if (op == GVT_AUX_NATIVE_READ) {
792 int idx, i, ret = 0;
793
794 if ((addr + len + 1) >= DPCD_SIZE) {
795 /*
796 * read request exceeds what we supported
797 * DPCD spec: A Sink Device receiving a Native AUX CH
798 * read request for an unsupported DPCD address must
799 * reply with an AUX ACK and read data set equal to
800 * zero instead of replying with AUX NACK.
801 */
802
803 /* ACK the READ*/
804 vgpu_vreg(vgpu, offset + 4) = 0;
805 vgpu_vreg(vgpu, offset + 8) = 0;
806 vgpu_vreg(vgpu, offset + 12) = 0;
807 vgpu_vreg(vgpu, offset + 16) = 0;
808 vgpu_vreg(vgpu, offset + 20) = 0;
809
810 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
811 true);
812 return 0;
813 }
814
815 for (idx = 1; idx <= 5; idx++) {
816 /* clear the data registers */
817 vgpu_vreg(vgpu, offset + 4 * idx) = 0;
818 }
819
820 /*
821 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
822 */
823 if (WARN_ON((len + 2) > AUX_BURST_SIZE))
824 return -EINVAL;
825
826 /* read from virtual DPCD to vreg */
827 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */
828 if (dpcd && dpcd->data_valid) {
829 for (i = 1; i <= (len + 1); i++) {
830 int t;
831
832 t = dpcd->data[addr + i - 1];
833 t <<= (24 - 8 * (i % 4));
834 ret |= t;
835
836 if ((i % 4 == 3) || (i == (len + 1))) {
837 vgpu_vreg(vgpu, offset +
838 (i / 4 + 1) * 4) = ret;
839 ret = 0;
840 }
841 }
842 }
843 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
844 dpcd && dpcd->data_valid);
845 return 0;
846 }
847
848 /* i2c transaction starts */
849 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);
850
851 if (data & DP_AUX_CH_CTL_INTERRUPT)
852 trigger_aux_channel_interrupt(vgpu, offset);
853 return 0;
854}
855
856static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
857 void *p_data, unsigned int bytes)
858{
859 bool vga_disable;
860
861 write_vreg(vgpu, offset, p_data, bytes);
862 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
863
864 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id,
865 vga_disable ? "Disable" : "Enable");
866 return 0;
867}
868
869static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu,
870 unsigned int sbi_offset)
871{
872 struct intel_vgpu_display *display = &vgpu->display;
873 int num = display->sbi.number;
874 int i;
875
876 for (i = 0; i < num; ++i)
877 if (display->sbi.registers[i].offset == sbi_offset)
878 break;
879
880 if (i == num)
881 return 0;
882
883 return display->sbi.registers[i].value;
884}
885
886static void write_virtual_sbi_register(struct intel_vgpu *vgpu,
887 unsigned int offset, u32 value)
888{
889 struct intel_vgpu_display *display = &vgpu->display;
890 int num = display->sbi.number;
891 int i;
892
893 for (i = 0; i < num; ++i) {
894 if (display->sbi.registers[i].offset == offset)
895 break;
896 }
897
898 if (i == num) {
899 if (num == SBI_REG_MAX) {
900 gvt_err("vgpu%d: SBI caching meets maximum limits\n",
901 vgpu->id);
902 return;
903 }
904 display->sbi.number++;
905 }
906
907 display->sbi.registers[i].offset = offset;
908 display->sbi.registers[i].value = value;
909}
910
911static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
912 void *p_data, unsigned int bytes)
913{
914 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
915 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) {
916 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) &
917 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
918 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu,
919 sbi_offset);
920 }
921 read_vreg(vgpu, offset, p_data, bytes);
922 return 0;
923}
924
925static bool sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
926 void *p_data, unsigned int bytes)
927{
928 u32 data;
929
930 write_vreg(vgpu, offset, p_data, bytes);
931 data = vgpu_vreg(vgpu, offset);
932
933 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT);
934 data |= SBI_READY;
935
936 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT);
937 data |= SBI_RESPONSE_SUCCESS;
938
939 vgpu_vreg(vgpu, offset) = data;
940
941 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
942 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) {
943 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) &
944 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
945
946 write_virtual_sbi_register(vgpu, sbi_offset,
947 vgpu_vreg(vgpu, SBI_DATA));
948 }
949 return 0;
950}
951
254#define _vgtif_reg(x) \
255 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
256
257static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
258 void *p_data, unsigned int bytes)
259{
260 bool invalid_read = false;
261

--- 45 unchanged lines hidden (view full) ---

307 case 1: /* Remove this in guest driver. */
308 break;
309 default:
310 gvt_err("Invalid PV notification %d\n", notification);
311 }
312 return ret;
313}
314
952#define _vgtif_reg(x) \
953 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
954
955static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
956 void *p_data, unsigned int bytes)
957{
958 bool invalid_read = false;
959

--- 45 unchanged lines hidden (view full) ---

1005 case 1: /* Remove this in guest driver. */
1006 break;
1007 default:
1008 gvt_err("Invalid PV notification %d\n", notification);
1009 }
1010 return ret;
1011}
1012
1013static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
1014{
1015 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1016 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
1017 char *env[3] = {NULL, NULL, NULL};
1018 char vmid_str[20];
1019 char display_ready_str[20];
1020
1021 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d\n", ready);
1022 env[0] = display_ready_str;
1023
1024 snprintf(vmid_str, 20, "VMID=%d", vgpu->id);
1025 env[1] = vmid_str;
1026
1027 return kobject_uevent_env(kobj, KOBJ_ADD, env);
1028}
1029
315static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
316 void *p_data, unsigned int bytes)
317{
318 u32 data;
319 int ret;
320
321 write_vreg(vgpu, offset, p_data, bytes);
322 data = vgpu_vreg(vgpu, offset);
323
324 switch (offset) {
325 case _vgtif_reg(display_ready):
1030static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1031 void *p_data, unsigned int bytes)
1032{
1033 u32 data;
1034 int ret;
1035
1036 write_vreg(vgpu, offset, p_data, bytes);
1037 data = vgpu_vreg(vgpu, offset);
1038
1039 switch (offset) {
1040 case _vgtif_reg(display_ready):
1041 send_display_ready_uevent(vgpu, data ? 1 : 0);
1042 break;
326 case _vgtif_reg(g2v_notify):
327 ret = handle_g2v_notification(vgpu, data);
328 break;
329 /* add xhot and yhot to handled list to avoid error log */
330 case 0x78830:
331 case 0x78834:
332 case _vgtif_reg(pdp[0].lo):
333 case _vgtif_reg(pdp[0].hi):

--- 9 unchanged lines hidden (view full) ---

343 default:
344 gvt_err("invalid pvinfo write offset %x bytes %x data %x\n",
345 offset, bytes, data);
346 break;
347 }
348 return 0;
349}
350
1043 case _vgtif_reg(g2v_notify):
1044 ret = handle_g2v_notification(vgpu, data);
1045 break;
1046 /* add xhot and yhot to handled list to avoid error log */
1047 case 0x78830:
1048 case 0x78834:
1049 case _vgtif_reg(pdp[0].lo):
1050 case _vgtif_reg(pdp[0].hi):

--- 9 unchanged lines hidden (view full) ---

1060 default:
1061 gvt_err("invalid pvinfo write offset %x bytes %x data %x\n",
1062 offset, bytes, data);
1063 break;
1064 }
1065 return 0;
1066}
1067
1068static int pf_write(struct intel_vgpu *vgpu,
1069 unsigned int offset, void *p_data, unsigned int bytes)
1070{
1071 u32 val = *(u32 *)p_data;
1072
1073 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
1074 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
1075 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
1076 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n",
1077 vgpu->id);
1078 return 0;
1079 }
1080
1081 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
1082}
1083
1084static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
1085 unsigned int offset, void *p_data, unsigned int bytes)
1086{
1087 write_vreg(vgpu, offset, p_data, bytes);
1088
1089 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_ENABLE_REQUEST)
1090 vgpu_vreg(vgpu, offset) |= HSW_PWR_WELL_STATE_ENABLED;
1091 else
1092 vgpu_vreg(vgpu, offset) &= ~HSW_PWR_WELL_STATE_ENABLED;
1093 return 0;
1094}
1095
351static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
352 unsigned int offset, void *p_data, unsigned int bytes)
353{
354 write_vreg(vgpu, offset, p_data, bytes);
355
356 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
357 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
358 return 0;

--- 40 unchanged lines hidden (view full) ---

399 if (val & 1) {
400 /* unblock hw logic */
401 I915_WRITE(_MMIO(offset), val);
402 }
403 write_vreg(vgpu, offset, p_data, bytes);
404 return 0;
405}
406
1096static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
1097 unsigned int offset, void *p_data, unsigned int bytes)
1098{
1099 write_vreg(vgpu, offset, p_data, bytes);
1100
1101 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
1102 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
1103 return 0;

--- 40 unchanged lines hidden (view full) ---

1144 if (val & 1) {
1145 /* unblock hw logic */
1146 I915_WRITE(_MMIO(offset), val);
1147 }
1148 write_vreg(vgpu, offset, p_data, bytes);
1149 return 0;
1150}
1151
1152static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset,
1153 void *p_data, unsigned int bytes)
1154{
1155 u32 v = 0;
1156
1157 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
1158 v |= (1 << 0);
1159
1160 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
1161 v |= (1 << 8);
1162
1163 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
1164 v |= (1 << 16);
1165
1166 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
1167 v |= (1 << 24);
1168
1169 vgpu_vreg(vgpu, offset) = v;
1170
1171 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1172}
1173
1174static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
1175 void *p_data, unsigned int bytes)
1176{
1177 u32 value = *(u32 *)p_data;
1178 u32 cmd = value & 0xff;
1179 u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA);
1180
1181 switch (cmd) {
1182 case 0x6:
1183 /**
1184 * "Read memory latency" command on gen9.
1185 * Below memory latency values are read
1186 * from skylake platform.
1187 */
1188 if (!*data0)
1189 *data0 = 0x1e1a1100;
1190 else
1191 *data0 = 0x61514b3d;
1192 break;
1193 case 0x5:
1194 *data0 |= 0x1;
1195 break;
1196 }
1197
1198 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n",
1199 vgpu->id, value, *data0);
1200
1201 value &= ~(1 << 31);
1202 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1203}
1204
1205static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1206 unsigned int offset, void *p_data, unsigned int bytes)
1207{
1208 u32 v = *(u32 *)p_data;
1209
1210 v &= (1 << 31) | (1 << 29) | (1 << 9) |
1211 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
1212 v |= (v >> 1);
1213
1214 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1215}
1216
1217static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1218 void *p_data, unsigned int bytes)
1219{
1220 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1221 i915_reg_t reg = {.reg = offset};
1222
1223 switch (offset) {
1224 case 0x4ddc:
1225 vgpu_vreg(vgpu, offset) = 0x8000003c;
1226 break;
1227 case 0x42080:
1228 vgpu_vreg(vgpu, offset) = 0x8000;
1229 break;
1230 default:
1231 return -EINVAL;
1232 }
1233
1234 /**
1235 * TODO: need detect stepping info after gvt contain such information
1236 * 0x4ddc enabled after C0, 0x42080 enabled after E0.
1237 */
1238 I915_WRITE(reg, vgpu_vreg(vgpu, offset));
1239 return 0;
1240}
1241
1242static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
1243 void *p_data, unsigned int bytes)
1244{
1245 u32 v = *(u32 *)p_data;
1246
1247 /* other bits are MBZ. */
1248 v &= (1 << 31) | (1 << 30);
1249 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30));
1250
1251 vgpu_vreg(vgpu, offset) = v;
1252
1253 return 0;
1254}
1255
1256static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu,
1257 unsigned int offset, void *p_data, unsigned int bytes)
1258{
1259 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1260
1261 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
1262 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1263}
1264
407#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
408 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \
409 f, s, am, rm, d, r, w); \
410 if (ret) \
411 return ret; \
412} while (0)
413
414#define MMIO_D(reg, d) \

--- 70 unchanged lines hidden (view full) ---

485
486 /* RING MODE */
487#define RING_REG(base) (base + 0x29c)
488 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK, NULL, NULL);
489#undef RING_REG
490
491 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK, NULL, NULL);
492 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK, NULL, NULL);
1265#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
1266 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \
1267 f, s, am, rm, d, r, w); \
1268 if (ret) \
1269 return ret; \
1270} while (0)
1271
1272#define MMIO_D(reg, d) \

--- 70 unchanged lines hidden (view full) ---

1343
1344 /* RING MODE */
1345#define RING_REG(base) (base + 0x29c)
1346 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK, NULL, NULL);
1347#undef RING_REG
1348
1349 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK, NULL, NULL);
1350 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK, NULL, NULL);
493 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, NULL, NULL);
494 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, NULL, NULL);
1351 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
1352 ring_timestamp_mmio_read, NULL);
1353 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
1354 ring_timestamp_mmio_read, NULL);
495
496 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK, NULL, NULL);
497 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK, NULL, NULL);
498 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK, NULL, NULL);
499
500 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK, NULL, NULL);
501 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK, NULL, NULL);
502 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK, NULL, NULL);

--- 23 unchanged lines hidden (view full) ---

526 MMIO_D(0xc4040, D_ALL);
527 MMIO_D(DERRMR, D_ALL);
528
529 MMIO_D(PIPEDSL(PIPE_A), D_ALL);
530 MMIO_D(PIPEDSL(PIPE_B), D_ALL);
531 MMIO_D(PIPEDSL(PIPE_C), D_ALL);
532 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
533
1355
1356 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK, NULL, NULL);
1357 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK, NULL, NULL);
1358 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK, NULL, NULL);
1359
1360 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK, NULL, NULL);
1361 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK, NULL, NULL);
1362 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK, NULL, NULL);

--- 23 unchanged lines hidden (view full) ---

1386 MMIO_D(0xc4040, D_ALL);
1387 MMIO_D(DERRMR, D_ALL);
1388
1389 MMIO_D(PIPEDSL(PIPE_A), D_ALL);
1390 MMIO_D(PIPEDSL(PIPE_B), D_ALL);
1391 MMIO_D(PIPEDSL(PIPE_C), D_ALL);
1392 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
1393
534 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, NULL);
535 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, NULL);
536 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, NULL);
537 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, NULL);
1394 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
1395 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
1396 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
1397 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
538
539 MMIO_D(PIPESTAT(PIPE_A), D_ALL);
540 MMIO_D(PIPESTAT(PIPE_B), D_ALL);
541 MMIO_D(PIPESTAT(PIPE_C), D_ALL);
542 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
543
544 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
545 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);

--- 26 unchanged lines hidden (view full) ---

572 MMIO_D(0x70098, D_ALL);
573 MMIO_D(0x7009c, D_ALL);
574
575 MMIO_D(DSPCNTR(PIPE_A), D_ALL);
576 MMIO_D(DSPADDR(PIPE_A), D_ALL);
577 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
578 MMIO_D(DSPPOS(PIPE_A), D_ALL);
579 MMIO_D(DSPSIZE(PIPE_A), D_ALL);
1398
1399 MMIO_D(PIPESTAT(PIPE_A), D_ALL);
1400 MMIO_D(PIPESTAT(PIPE_B), D_ALL);
1401 MMIO_D(PIPESTAT(PIPE_C), D_ALL);
1402 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
1403
1404 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
1405 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);

--- 26 unchanged lines hidden (view full) ---

1432 MMIO_D(0x70098, D_ALL);
1433 MMIO_D(0x7009c, D_ALL);
1434
1435 MMIO_D(DSPCNTR(PIPE_A), D_ALL);
1436 MMIO_D(DSPADDR(PIPE_A), D_ALL);
1437 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
1438 MMIO_D(DSPPOS(PIPE_A), D_ALL);
1439 MMIO_D(DSPSIZE(PIPE_A), D_ALL);
580 MMIO_D(DSPSURF(PIPE_A), D_ALL);
1440 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
581 MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
582 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
583
584 MMIO_D(DSPCNTR(PIPE_B), D_ALL);
585 MMIO_D(DSPADDR(PIPE_B), D_ALL);
586 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
587 MMIO_D(DSPPOS(PIPE_B), D_ALL);
588 MMIO_D(DSPSIZE(PIPE_B), D_ALL);
1441 MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
1442 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
1443
1444 MMIO_D(DSPCNTR(PIPE_B), D_ALL);
1445 MMIO_D(DSPADDR(PIPE_B), D_ALL);
1446 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
1447 MMIO_D(DSPPOS(PIPE_B), D_ALL);
1448 MMIO_D(DSPSIZE(PIPE_B), D_ALL);
589 MMIO_D(DSPSURF(PIPE_B), D_ALL);
1449 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
590 MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
591 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
592
593 MMIO_D(DSPCNTR(PIPE_C), D_ALL);
594 MMIO_D(DSPADDR(PIPE_C), D_ALL);
595 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
596 MMIO_D(DSPPOS(PIPE_C), D_ALL);
597 MMIO_D(DSPSIZE(PIPE_C), D_ALL);
1450 MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
1451 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
1452
1453 MMIO_D(DSPCNTR(PIPE_C), D_ALL);
1454 MMIO_D(DSPADDR(PIPE_C), D_ALL);
1455 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
1456 MMIO_D(DSPPOS(PIPE_C), D_ALL);
1457 MMIO_D(DSPSIZE(PIPE_C), D_ALL);
598 MMIO_D(DSPSURF(PIPE_C), D_ALL);
1458 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
599 MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
600 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
601
602 MMIO_D(SPRCTL(PIPE_A), D_ALL);
603 MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
604 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
605 MMIO_D(SPRPOS(PIPE_A), D_ALL);
606 MMIO_D(SPRSIZE(PIPE_A), D_ALL);
607 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
608 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
1459 MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
1460 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
1461
1462 MMIO_D(SPRCTL(PIPE_A), D_ALL);
1463 MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
1464 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
1465 MMIO_D(SPRPOS(PIPE_A), D_ALL);
1466 MMIO_D(SPRSIZE(PIPE_A), D_ALL);
1467 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
1468 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
609 MMIO_D(SPRSURF(PIPE_A), D_ALL);
1469 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
610 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
611 MMIO_D(SPROFFSET(PIPE_A), D_ALL);
612 MMIO_D(SPRSCALE(PIPE_A), D_ALL);
613 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
614
615 MMIO_D(SPRCTL(PIPE_B), D_ALL);
616 MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
617 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
618 MMIO_D(SPRPOS(PIPE_B), D_ALL);
619 MMIO_D(SPRSIZE(PIPE_B), D_ALL);
620 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
621 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
1470 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
1471 MMIO_D(SPROFFSET(PIPE_A), D_ALL);
1472 MMIO_D(SPRSCALE(PIPE_A), D_ALL);
1473 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
1474
1475 MMIO_D(SPRCTL(PIPE_B), D_ALL);
1476 MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
1477 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
1478 MMIO_D(SPRPOS(PIPE_B), D_ALL);
1479 MMIO_D(SPRSIZE(PIPE_B), D_ALL);
1480 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
1481 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
622 MMIO_D(SPRSURF(PIPE_B), D_ALL);
1482 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
623 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
624 MMIO_D(SPROFFSET(PIPE_B), D_ALL);
625 MMIO_D(SPRSCALE(PIPE_B), D_ALL);
626 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
627
628 MMIO_D(SPRCTL(PIPE_C), D_ALL);
629 MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
630 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
631 MMIO_D(SPRPOS(PIPE_C), D_ALL);
632 MMIO_D(SPRSIZE(PIPE_C), D_ALL);
633 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
634 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
1483 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
1484 MMIO_D(SPROFFSET(PIPE_B), D_ALL);
1485 MMIO_D(SPRSCALE(PIPE_B), D_ALL);
1486 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
1487
1488 MMIO_D(SPRCTL(PIPE_C), D_ALL);
1489 MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
1490 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
1491 MMIO_D(SPRPOS(PIPE_C), D_ALL);
1492 MMIO_D(SPRSIZE(PIPE_C), D_ALL);
1493 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
1494 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
635 MMIO_D(SPRSURF(PIPE_C), D_ALL);
1495 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
636 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
637 MMIO_D(SPROFFSET(PIPE_C), D_ALL);
638 MMIO_D(SPRSCALE(PIPE_C), D_ALL);
639 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
640
641 MMIO_F(LGC_PALETTE(PIPE_A, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL);
642 MMIO_F(LGC_PALETTE(PIPE_B, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL);
643 MMIO_F(LGC_PALETTE(PIPE_C, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL);

--- 103 unchanged lines hidden (view full) ---

747
748 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
749 MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
750 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
751 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
752
753 MMIO_D(0x48268, D_ALL);
754
1496 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
1497 MMIO_D(SPROFFSET(PIPE_C), D_ALL);
1498 MMIO_D(SPRSCALE(PIPE_C), D_ALL);
1499 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
1500
1501 MMIO_F(LGC_PALETTE(PIPE_A, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL);
1502 MMIO_F(LGC_PALETTE(PIPE_B, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL);
1503 MMIO_F(LGC_PALETTE(PIPE_C, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL);

--- 103 unchanged lines hidden (view full) ---

1607
1608 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
1609 MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
1610 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
1611 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
1612
1613 MMIO_D(0x48268, D_ALL);
1614
755 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, NULL, NULL);
756 MMIO_F(PCH_GPIOA, 6 * 4, 0, 0, 0, D_ALL, NULL, NULL);
1615 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
1616 gmbus_mmio_write);
1617 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
757 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL);
758
1618 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL);
1619
759 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, NULL);
760 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, NULL);
761 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, NULL);
1620 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1621 dp_aux_ch_ctl_mmio_write);
1622 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1623 dp_aux_ch_ctl_mmio_write);
1624 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1625 dp_aux_ch_ctl_mmio_write);
762
1626
763 MMIO_RO(PCH_ADPA, D_ALL, 0,
764 ADPA_CRT_HOTPLUG_MONITOR_MASK, NULL, NULL);
1627 MMIO_RO(PCH_ADPA, D_ALL, 0, ADPA_CRT_HOTPLUG_MONITOR_MASK, NULL, pch_adpa_mmio_write);
765
1628
766 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, NULL);
767 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, NULL);
1629 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write);
1630 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write);
768
1631
769 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, NULL);
770 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, NULL);
771 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, NULL);
772 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, NULL);
773 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, NULL);
774 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, NULL);
775 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, NULL);
776 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, NULL);
777 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, NULL);
1632 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
1633 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
1634 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
1635 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
1636 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
1637 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
1638 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
1639 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
1640 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
778
779 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL);
780 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL);
781 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL);
782 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL);
783 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL);
784 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL);
785 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL);

--- 33 unchanged lines hidden (view full) ---

819
820 MMIO_D(_FDI_RXA_MISC, D_ALL);
821 MMIO_D(_FDI_RXB_MISC, D_ALL);
822 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL);
823 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL);
824 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL);
825 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL);
826
1641
1642 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL);
1643 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL);
1644 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL);
1645 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL);
1646 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL);
1647 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL);
1648 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL);

--- 33 unchanged lines hidden (view full) ---

1682
1683 MMIO_D(_FDI_RXA_MISC, D_ALL);
1684 MMIO_D(_FDI_RXB_MISC, D_ALL);
1685 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL);
1686 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL);
1687 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL);
1688 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL);
1689
827 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, NULL);
1690 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
828 MMIO_D(PCH_PP_DIVISOR, D_ALL);
829 MMIO_D(PCH_PP_STATUS, D_ALL);
830 MMIO_D(PCH_LVDS, D_ALL);
831 MMIO_D(_PCH_DPLL_A, D_ALL);
832 MMIO_D(_PCH_DPLL_B, D_ALL);
833 MMIO_D(_PCH_FPA0, D_ALL);
834 MMIO_D(_PCH_FPA1, D_ALL);
835 MMIO_D(_PCH_FPB0, D_ALL);
836 MMIO_D(_PCH_FPB1, D_ALL);
837 MMIO_D(PCH_DREF_CONTROL, D_ALL);
838 MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
839 MMIO_D(PCH_DPLL_SEL, D_ALL);
840
841 MMIO_D(0x61208, D_ALL);
842 MMIO_D(0x6120c, D_ALL);
843 MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
844 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
845
1691 MMIO_D(PCH_PP_DIVISOR, D_ALL);
1692 MMIO_D(PCH_PP_STATUS, D_ALL);
1693 MMIO_D(PCH_LVDS, D_ALL);
1694 MMIO_D(_PCH_DPLL_A, D_ALL);
1695 MMIO_D(_PCH_DPLL_B, D_ALL);
1696 MMIO_D(_PCH_FPA0, D_ALL);
1697 MMIO_D(_PCH_FPA1, D_ALL);
1698 MMIO_D(_PCH_FPB0, D_ALL);
1699 MMIO_D(_PCH_FPB1, D_ALL);
1700 MMIO_D(PCH_DREF_CONTROL, D_ALL);
1701 MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
1702 MMIO_D(PCH_DPLL_SEL, D_ALL);
1703
1704 MMIO_D(0x61208, D_ALL);
1705 MMIO_D(0x6120c, D_ALL);
1706 MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
1707 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
1708
846 MMIO_DH(0xe651c, D_ALL, NULL, NULL);
847 MMIO_DH(0xe661c, D_ALL, NULL, NULL);
848 MMIO_DH(0xe671c, D_ALL, NULL, NULL);
849 MMIO_DH(0xe681c, D_ALL, NULL, NULL);
850 MMIO_DH(0xe6c04, D_ALL, NULL, NULL);
851 MMIO_DH(0xe6e1c, D_ALL, NULL, NULL);
1709 MMIO_DH(0xe651c, D_ALL, dpy_reg_mmio_read, NULL);
1710 MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL);
1711 MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL);
1712 MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL);
1713 MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read_2, NULL);
1714 MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read_3, NULL);
852
853 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
854 PORTA_HOTPLUG_STATUS_MASK
855 | PORTB_HOTPLUG_STATUS_MASK
856 | PORTC_HOTPLUG_STATUS_MASK
857 | PORTD_HOTPLUG_STATUS_MASK,
858 NULL, NULL);
859
1715
1716 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
1717 PORTA_HOTPLUG_STATUS_MASK
1718 | PORTB_HOTPLUG_STATUS_MASK
1719 | PORTC_HOTPLUG_STATUS_MASK
1720 | PORTD_HOTPLUG_STATUS_MASK,
1721 NULL, NULL);
1722
860 MMIO_DH(LCPLL_CTL, D_ALL, NULL, NULL);
1723 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
861 MMIO_D(FUSE_STRAP, D_ALL);
862 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
863
864 MMIO_D(DISP_ARB_CTL, D_ALL);
865 MMIO_D(DISP_ARB_CTL2, D_ALL);
866
867 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
868 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
869 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
870
871 MMIO_D(SOUTH_CHICKEN1, D_ALL);
1724 MMIO_D(FUSE_STRAP, D_ALL);
1725 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
1726
1727 MMIO_D(DISP_ARB_CTL, D_ALL);
1728 MMIO_D(DISP_ARB_CTL2, D_ALL);
1729
1730 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
1731 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
1732 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
1733
1734 MMIO_D(SOUTH_CHICKEN1, D_ALL);
872 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, NULL);
1735 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
873 MMIO_D(_TRANSA_CHICKEN1, D_ALL);
874 MMIO_D(_TRANSB_CHICKEN1, D_ALL);
875 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
876 MMIO_D(_TRANSA_CHICKEN2, D_ALL);
877 MMIO_D(_TRANSB_CHICKEN2, D_ALL);
878
879 MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
880 MMIO_D(ILK_DPFC_CONTROL, D_ALL);

--- 42 unchanged lines hidden (view full) ---

923 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
924 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
925 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
926 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
927 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
928 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
929 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
930
1736 MMIO_D(_TRANSA_CHICKEN1, D_ALL);
1737 MMIO_D(_TRANSB_CHICKEN1, D_ALL);
1738 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
1739 MMIO_D(_TRANSA_CHICKEN2, D_ALL);
1740 MMIO_D(_TRANSB_CHICKEN2, D_ALL);
1741
1742 MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
1743 MMIO_D(ILK_DPFC_CONTROL, D_ALL);

--- 42 unchanged lines hidden (view full) ---

1786 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
1787 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
1788 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
1789 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
1790 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
1791 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
1792 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
1793
1794 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
1795 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
1796 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
1797
1798 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
1799 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
1800 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
1801
1802 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
1803 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
1804 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
1805
931 MMIO_D(0x60110, D_ALL);
932 MMIO_D(0x61110, D_ALL);
933 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
934 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
935 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
936 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
937 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
938 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);

--- 26 unchanged lines hidden (view full) ---

965 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
966 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
967 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
968
969 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
970 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
971 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
972
1806 MMIO_D(0x60110, D_ALL);
1807 MMIO_D(0x61110, D_ALL);
1808 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
1809 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
1810 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
1811 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
1812 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
1813 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);

--- 26 unchanged lines hidden (view full) ---

1840 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
1841 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
1842 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
1843
1844 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
1845 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
1846 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
1847
973 MMIO_D(0x4a400, D_ALL);
974 MMIO_D(0x4ac00, D_ALL);
975 MMIO_D(0x4b400, D_ALL);
976
977 MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
978 MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
979 MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
980
981 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
982 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
983 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
984
985 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
986 MMIO_D(SBI_ADDR, D_ALL);
1848 MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
1849 MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
1850 MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
1851
1852 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
1853 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
1854 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
1855
1856 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
1857 MMIO_D(SBI_ADDR, D_ALL);
987 MMIO_DH(SBI_DATA, D_ALL, NULL, NULL);
988 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, NULL);
1858 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
1859 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
989 MMIO_D(PIXCLK_GATE, D_ALL);
990
1860 MMIO_D(PIXCLK_GATE, D_ALL);
1861
991 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL, NULL);
1862 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL,
1863 dp_aux_ch_ctl_mmio_write);
992
1864
993 MMIO_RO(DDI_BUF_CTL(PORT_A), D_ALL, 0,
994 DDI_INIT_DISPLAY_DETECTED, NULL, NULL);
995 MMIO_RO(DDI_BUF_CTL(PORT_B), D_ALL, 0,
996 DDI_INIT_DISPLAY_DETECTED, NULL, NULL);
997 MMIO_RO(DDI_BUF_CTL(PORT_C), D_ALL, 0,
998 DDI_INIT_DISPLAY_DETECTED, NULL, NULL);
999 MMIO_RO(DDI_BUF_CTL(PORT_D), D_ALL, 0,
1000 DDI_INIT_DISPLAY_DETECTED, NULL, NULL);
1001 MMIO_RO(DDI_BUF_CTL(PORT_E), D_ALL, 0,
1002 DDI_INIT_DISPLAY_DETECTED, NULL, NULL);
1865 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
1866 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
1867 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
1868 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
1869 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
1003
1870
1004 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, NULL);
1005 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, NULL);
1006 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, NULL);
1007 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, NULL);
1008 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, NULL);
1871 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
1872 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
1873 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
1874 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
1875 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
1009
1876
1010 MMIO_RO(DP_TP_STATUS(PORT_A), D_ALL, 0,
1011 (1 << 27) | (1 << 26) | (1 << 24), NULL, NULL);
1012 MMIO_RO(DP_TP_STATUS(PORT_B), D_ALL, 0,
1013 (1 << 27) | (1 << 26) | (1 << 24), NULL, NULL);
1014 MMIO_RO(DP_TP_STATUS(PORT_C), D_ALL, 0,
1015 (1 << 27) | (1 << 26) | (1 << 24), NULL, NULL);
1016 MMIO_RO(DP_TP_STATUS(PORT_D), D_ALL, 0,
1017 (1 << 27) | (1 << 26) | (1 << 24), NULL, NULL);
1018 MMIO_RO(DP_TP_STATUS(PORT_E), D_ALL, 0,
1019 (1 << 27) | (1 << 26) | (1 << 24), NULL, NULL);
1877 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
1878 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
1879 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
1880 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
1881 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
1020
1021 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
1022 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
1023 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
1024 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
1025 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
1026
1027 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);

--- 43 unchanged lines hidden (view full) ---

1071 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
1072 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
1073 MMIO_D(GEN6_RC_SLEEP, D_ALL);
1074 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
1075 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
1076 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
1077 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
1078 MMIO_D(GEN6_PMINTRMSK, D_ALL);
1882
1883 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
1884 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
1885 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
1886 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
1887 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
1888
1889 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);

--- 43 unchanged lines hidden (view full) ---

1933 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
1934 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
1935 MMIO_D(GEN6_RC_SLEEP, D_ALL);
1936 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
1937 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
1938 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
1939 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
1940 MMIO_D(GEN6_PMINTRMSK, D_ALL);
1079 MMIO_DH(HSW_PWR_WELL_BIOS, D_HSW | D_BDW, NULL, NULL);
1080 MMIO_DH(HSW_PWR_WELL_DRIVER, D_HSW | D_BDW, NULL, NULL);
1081 MMIO_DH(HSW_PWR_WELL_KVMR, D_HSW | D_BDW, NULL, NULL);
1082 MMIO_DH(HSW_PWR_WELL_DEBUG, D_HSW | D_BDW, NULL, NULL);
1083 MMIO_DH(HSW_PWR_WELL_CTL5, D_HSW | D_BDW, NULL, NULL);
1084 MMIO_DH(HSW_PWR_WELL_CTL6, D_HSW | D_BDW, NULL, NULL);
1941 MMIO_DH(HSW_PWR_WELL_BIOS, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
1942 MMIO_DH(HSW_PWR_WELL_DRIVER, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
1943 MMIO_DH(HSW_PWR_WELL_KVMR, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
1944 MMIO_DH(HSW_PWR_WELL_DEBUG, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
1945 MMIO_DH(HSW_PWR_WELL_CTL5, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
1946 MMIO_DH(HSW_PWR_WELL_CTL6, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
1085
1086 MMIO_D(RSTDBYCTL, D_ALL);
1087
1088 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
1089 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
1090 MMIO_F(VGT_PVINFO_PAGE, VGT_PVINFO_SIZE, F_UNALIGN, 0, 0, D_ALL, pvinfo_mmio_read, pvinfo_mmio_write);
1947
1948 MMIO_D(RSTDBYCTL, D_ALL);
1949
1950 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
1951 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
1952 MMIO_F(VGT_PVINFO_PAGE, VGT_PVINFO_SIZE, F_UNALIGN, 0, 0, D_ALL, pvinfo_mmio_read, pvinfo_mmio_write);
1091 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, NULL);
1953 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
1092
1093 MMIO_F(MCHBAR_MIRROR_BASE_SNB, 0x40000, 0, 0, 0, D_ALL, NULL, NULL);
1094
1095 MMIO_D(TILECTL, D_ALL);
1096
1097 MMIO_D(GEN6_UCGCTL1, D_ALL);
1098 MMIO_D(GEN6_UCGCTL2, D_ALL);
1099

--- 196 unchanged lines hidden (view full) ---

1296 MMIO_D(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS);
1297 MMIO_D(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS);
1298 MMIO_D(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS);
1299 MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
1300 MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK,
1301 NULL, NULL);
1302 MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK,
1303 NULL, NULL);
1954
1955 MMIO_F(MCHBAR_MIRROR_BASE_SNB, 0x40000, 0, 0, 0, D_ALL, NULL, NULL);
1956
1957 MMIO_D(TILECTL, D_ALL);
1958
1959 MMIO_D(GEN6_UCGCTL1, D_ALL);
1960 MMIO_D(GEN6_UCGCTL2, D_ALL);
1961

--- 196 unchanged lines hidden (view full) ---

2158 MMIO_D(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS);
2159 MMIO_D(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS);
2160 MMIO_D(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS);
2161 MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2162 MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK,
2163 NULL, NULL);
2164 MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK,
2165 NULL, NULL);
1304 MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK,
1305 NULL, NULL);
2166 MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2167 ring_timestamp_mmio_read, NULL);
1306
1307 MMIO_RING_D(RING_ACTHD_UDW, D_BDW_PLUS);
1308
1309#define RING_REG(base) (base + 0x230)
1310 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, NULL);
1311 MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL);
1312#undef RING_REG
1313

--- 103 unchanged lines hidden (view full) ---

1417
1418 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
1419 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
1420 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
1421 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL);
1422 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
1423 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
1424
2168
2169 MMIO_RING_D(RING_ACTHD_UDW, D_BDW_PLUS);
2170
2171#define RING_REG(base) (base + 0x230)
2172 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, NULL);
2173 MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL);
2174#undef RING_REG
2175

--- 103 unchanged lines hidden (view full) ---

2279
2280 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2281 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
2282 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2283 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL);
2284 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2285 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
2286
1425 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, NULL);
1426 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, NULL);
1427 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, NULL);
2287 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write);
2288 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write);
2289 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write);
1428
1429 MMIO_D(HSW_PWR_WELL_BIOS, D_SKL);
2290
2291 MMIO_D(HSW_PWR_WELL_BIOS, D_SKL);
1430 MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL, NULL, NULL);
2292 MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL, NULL, skl_power_well_ctl_write);
1431
2293
1432 MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL, NULL, NULL);
2294 MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL, NULL, mailbox_write);
1433 MMIO_D(0xa210, D_SKL_PLUS);
1434 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
1435 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2295 MMIO_D(0xa210, D_SKL_PLUS);
2296 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2297 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
1436 MMIO_DH(0x4ddc, D_SKL, NULL, NULL);
1437 MMIO_DH(0x42080, D_SKL, NULL, NULL);
2298 MMIO_DH(0x4ddc, D_SKL, NULL, skl_misc_ctl_write);
2299 MMIO_DH(0x42080, D_SKL, NULL, skl_misc_ctl_write);
1438 MMIO_D(0x45504, D_SKL);
1439 MMIO_D(0x45520, D_SKL);
1440 MMIO_D(0x46000, D_SKL);
2300 MMIO_D(0x45504, D_SKL);
2301 MMIO_D(0x45520, D_SKL);
2302 MMIO_D(0x46000, D_SKL);
1441 MMIO_DH(0x46010, D_SKL, NULL, NULL);
1442 MMIO_DH(0x46014, D_SKL, NULL, NULL);
2303 MMIO_DH(0x46010, D_SKL, NULL, skl_lcpll_write);
2304 MMIO_DH(0x46014, D_SKL, NULL, skl_lcpll_write);
1443 MMIO_D(0x6C040, D_SKL);
1444 MMIO_D(0x6C048, D_SKL);
1445 MMIO_D(0x6C050, D_SKL);
1446 MMIO_D(0x6C044, D_SKL);
1447 MMIO_D(0x6C04C, D_SKL);
1448 MMIO_D(0x6C054, D_SKL);
1449 MMIO_D(0x6c058, D_SKL);
1450 MMIO_D(0x6c05c, D_SKL);
2305 MMIO_D(0x6C040, D_SKL);
2306 MMIO_D(0x6C048, D_SKL);
2307 MMIO_D(0x6C050, D_SKL);
2308 MMIO_D(0x6C044, D_SKL);
2309 MMIO_D(0x6C04C, D_SKL);
2310 MMIO_D(0x6C054, D_SKL);
2311 MMIO_D(0x6c058, D_SKL);
2312 MMIO_D(0x6c05c, D_SKL);
1451 MMIO_DH(0x6c060, D_SKL, NULL, NULL);
2313 MMIO_DH(0X6c060, D_SKL, dpll_status_read, NULL);
1452
2314
1453 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL, NULL, NULL);
1454 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL, NULL, NULL);
1455 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL, NULL, NULL);
1456 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL, NULL, NULL);
1457 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL, NULL, NULL);
1458 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL, NULL, NULL);
2315 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL, NULL, pf_write);
2316 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL, NULL, pf_write);
2317 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL, NULL, pf_write);
2318 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL, NULL, pf_write);
2319 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL, NULL, pf_write);
2320 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL, NULL, pf_write);
1459
2321
1460 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL, NULL, NULL);
1461 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL, NULL, NULL);
1462 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL, NULL, NULL);
1463 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL, NULL, NULL);
1464 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL, NULL, NULL);
1465 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL, NULL, NULL);
2322 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL, NULL, pf_write);
2323 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL, NULL, pf_write);
2324 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL, NULL, pf_write);
2325 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL, NULL, pf_write);
2326 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL, NULL, pf_write);
2327 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL, NULL, pf_write);
1466
2328
1467 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL, NULL, NULL);
1468 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL, NULL, NULL);
1469 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL, NULL, NULL);
1470 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL, NULL, NULL);
1471 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL, NULL, NULL);
1472 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL, NULL, NULL);
2329 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL, NULL, pf_write);
2330 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL, NULL, pf_write);
2331 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL, NULL, pf_write);
2332 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL, NULL, pf_write);
2333 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL, NULL, pf_write);
2334 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL, NULL, pf_write);
1473
1474 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL);
1475 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL);
1476 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL);
1477 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL);
1478
1479 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL);
1480 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL);

--- 148 unchanged lines hidden (view full) ---

1629 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL);
1630 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL);
1631 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL);
1632 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL);
1633
1634 MMIO_D(0x44500, D_SKL);
1635 return 0;
1636}
2335
2336 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL);
2337 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL);
2338 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL);
2339 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL);
2340
2341 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL);
2342 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL);

--- 148 unchanged lines hidden (view full) ---

2491 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL);
2492 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL);
2493 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL);
2494 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL);
2495
2496 MMIO_D(0x44500, D_SKL);
2497 return 0;
2498}
2499
1637/**
1638 * intel_gvt_find_mmio_info - find MMIO information entry by aligned offset
1639 * @gvt: GVT device
1640 * @offset: register offset
1641 *
1642 * This function is used to find the MMIO information entry from hash table
1643 *
1644 * Returns:

--- 178 unchanged lines hidden --- 		2500/**
2501 * intel_gvt_find_mmio_info - find MMIO information entry by aligned offset
2502 * @gvt: GVT device
2503 * @offset: register offset
2504 *
2505 * This function is used to find the MMIO information entry from hash table
2506 *
2507 * Returns:

--- 178 unchanged lines hidden ---