handlers.c (62a6a53786fc4b4e7543cc63b704dbb3f7df4c0f) handlers.c (a2ae95af9646316aaf86e2d18f46de1a5f746f1a)
1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

--- 1366 unchanged lines hidden (view full) ---

1375 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we
1376 * always emulate as pcode read/write success and ready for access
1377 * anytime, since we don't touch real physical registers here.
1378 */
1379 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK);
1380 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1381}
1382
1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

--- 1366 unchanged lines hidden (view full) ---

1375 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we
1376 * always emulate as pcode read/write success and ready for access
1377 * anytime, since we don't touch real physical registers here.
1378 */
1379 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK);
1380 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1381}
1382
1383static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
1384 void *p_data, unsigned int bytes)
1385{
1386 u32 value = *(u32 *)p_data;
1387 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
1388
1389 if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
1390 gvt_vgpu_err("VM(%d) write invalid HWSP address, reg:0x%x, value:0x%x\n",
1391 vgpu->id, offset, value);
1392 return -EINVAL;
1393 }
1394 /*
1395 * Need to emulate all the HWSP register write to ensure host can
1396 * update the VM CSB status correctly. Here listed registers can
1397 * support BDW, SKL or other platforms with same HWSP registers.
1398 */
1399 if (unlikely(ring_id < 0 || ring_id > I915_NUM_ENGINES)) {
1400 gvt_vgpu_err("VM(%d) access unknown hardware status page register:0x%x\n",
1401 vgpu->id, offset);
1402 return -EINVAL;
1403 }
1404 vgpu->hws_pga[ring_id] = value;
1405 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n",
1406 vgpu->id, value, offset);
1407
1408 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1409}
1410
1383static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1384 unsigned int offset, void *p_data, unsigned int bytes)
1385{
1386 u32 v = *(u32 *)p_data;
1387
1388 v &= (1 << 31) | (1 << 29) | (1 << 9) |
1389 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
1390 v |= (v >> 1);

--- 1139 unchanged lines hidden (view full) ---

2530 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
2531
2532 MMIO_D(GAMTARBMODE, D_BDW_PLUS);
2533
2534#define RING_REG(base) (base + 0x270)
2535 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2536#undef RING_REG
2537
1411static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1412 unsigned int offset, void *p_data, unsigned int bytes)
1413{
1414 u32 v = *(u32 *)p_data;
1415
1416 v &= (1 << 31) | (1 << 29) | (1 << 9) |
1417 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
1418 v |= (v >> 1);

--- 1139 unchanged lines hidden (view full) ---

2558 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
2559
2560 MMIO_D(GAMTARBMODE, D_BDW_PLUS);
2561
2562#define RING_REG(base) (base + 0x270)
2563 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2564#undef RING_REG
2565
2538 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL);
2566 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
2539
2540 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2541
2542 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
2543 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
2544 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
2545
2546 MMIO_D(WM_MISC, D_BDW);

--- 538 unchanged lines hidden --- 		2567
2568 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2569
2570 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
2571 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
2572 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
2573
2574 MMIO_D(WM_MISC, D_BDW);

--- 538 unchanged lines hidden ---