gvt.h (e39c5add322184de3be052d438dfd24375bfeaea) gvt.h (04d348ae3f0aea6523bc3b0688b5fc90c1c60d0e)
1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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34#define _GVT_H_
35
36#include "debug.h"
37#include "hypercall.h"
38#include "mmio.h"
39#include "reg.h"
40#include "interrupt.h"
41#include "gtt.h"
1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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34#define _GVT_H_
35
36#include "debug.h"
37#include "hypercall.h"
38#include "mmio.h"
39#include "reg.h"
40#include "interrupt.h"
41#include "gtt.h"
42#include "display.h"
43#include "edid.h"
42
43#define GVT_MAX_VGPU 8
44
45enum {
46 INTEL_GVT_HYPERVISOR_XEN = 0,
47 INTEL_GVT_HYPERVISOR_KVM,
48};
49

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100
101struct intel_vgpu_cfg_space {
102 unsigned char virtual_cfg_space[INTEL_GVT_MAX_CFG_SPACE_SZ];
103 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM];
104};
105
106#define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)
107
44
45#define GVT_MAX_VGPU 8
46
47enum {
48 INTEL_GVT_HYPERVISOR_XEN = 0,
49 INTEL_GVT_HYPERVISOR_KVM,
50};
51

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102
103struct intel_vgpu_cfg_space {
104 unsigned char virtual_cfg_space[INTEL_GVT_MAX_CFG_SPACE_SZ];
105 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM];
106};
107
108#define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)
109
110#define INTEL_GVT_MAX_PIPE 4
111
108struct intel_vgpu_irq {
109 bool irq_warn_once[INTEL_GVT_EVENT_MAX];
112struct intel_vgpu_irq {
113 bool irq_warn_once[INTEL_GVT_EVENT_MAX];
114 DECLARE_BITMAP(flip_done_event[INTEL_GVT_MAX_PIPE],
115 INTEL_GVT_EVENT_MAX);
110};
111
112struct intel_vgpu_opregion {
113 void *va;
114 u32 gfn[INTEL_GVT_OPREGION_PAGES];
115 struct page *pages[INTEL_GVT_OPREGION_PAGES];
116};
117
118#define vgpu_opregion(vgpu) (&(vgpu->opregion))
119
116};
117
118struct intel_vgpu_opregion {
119 void *va;
120 u32 gfn[INTEL_GVT_OPREGION_PAGES];
121 struct page *pages[INTEL_GVT_OPREGION_PAGES];
122};
123
124#define vgpu_opregion(vgpu) (&(vgpu->opregion))
125
126#define INTEL_GVT_MAX_PORT 5
127
128struct intel_vgpu_display {
129 struct intel_vgpu_i2c_edid i2c_edid;
130 struct intel_vgpu_port ports[INTEL_GVT_MAX_PORT];
131 struct intel_vgpu_sbi sbi;
132};
133
120struct intel_vgpu {
121 struct intel_gvt *gvt;
122 int id;
123 unsigned long handle; /* vGPU handle used by hypervisor MPT modules */
124 bool active;
125 bool resetting;
126
127 struct intel_vgpu_fence fence;
128 struct intel_vgpu_gm gm;
129 struct intel_vgpu_cfg_space cfg_space;
130 struct intel_vgpu_mmio mmio;
131 struct intel_vgpu_irq irq;
132 struct intel_vgpu_gtt gtt;
133 struct intel_vgpu_opregion opregion;
134struct intel_vgpu {
135 struct intel_gvt *gvt;
136 int id;
137 unsigned long handle; /* vGPU handle used by hypervisor MPT modules */
138 bool active;
139 bool resetting;
140
141 struct intel_vgpu_fence fence;
142 struct intel_vgpu_gm gm;
143 struct intel_vgpu_cfg_space cfg_space;
144 struct intel_vgpu_mmio mmio;
145 struct intel_vgpu_irq irq;
146 struct intel_vgpu_gtt gtt;
147 struct intel_vgpu_opregion opregion;
148 struct intel_vgpu_display display;
134};
135
136struct intel_gvt_gm {
137 unsigned long vgpu_allocated_low_gm_size;
138 unsigned long vgpu_allocated_high_gm_size;
139};
140
141struct intel_gvt_fence {

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170 struct intel_gvt_device_info device_info;
171 struct intel_gvt_gm gm;
172 struct intel_gvt_fence fence;
173 struct intel_gvt_mmio mmio;
174 struct intel_gvt_firmware firmware;
175 struct intel_gvt_irq irq;
176 struct intel_gvt_gtt gtt;
177 struct intel_gvt_opregion opregion;
149};
150
151struct intel_gvt_gm {
152 unsigned long vgpu_allocated_low_gm_size;
153 unsigned long vgpu_allocated_high_gm_size;
154};
155
156struct intel_gvt_fence {

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185 struct intel_gvt_device_info device_info;
186 struct intel_gvt_gm gm;
187 struct intel_gvt_fence fence;
188 struct intel_gvt_mmio mmio;
189 struct intel_gvt_firmware firmware;
190 struct intel_gvt_irq irq;
191 struct intel_gvt_gtt gtt;
192 struct intel_gvt_opregion opregion;
193
194 struct task_struct *service_thread;
195 wait_queue_head_t service_thread_wq;
196 unsigned long service_request;
178};
179
197};
198
199enum {
200 INTEL_GVT_REQUEST_EMULATE_VBLANK = 0,
201};
202
203static inline void intel_gvt_request_service(struct intel_gvt *gvt,
204 int service)
205{
206 set_bit(service, (void *)&gvt->service_request);
207 wake_up(&gvt->service_thread_wq);
208}
209
180void intel_gvt_free_firmware(struct intel_gvt *gvt);
181int intel_gvt_load_firmware(struct intel_gvt *gvt);
182
183/* Aperture/GM space definitions for GVT device */
184#define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end)
185#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base)
186
187#define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.base.total)

--- 151 unchanged lines hidden --- 		210void intel_gvt_free_firmware(struct intel_gvt *gvt);
211int intel_gvt_load_firmware(struct intel_gvt *gvt);
212
213/* Aperture/GM space definitions for GVT device */
214#define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end)
215#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base)
216
217#define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.base.total)

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