tc358767.c (385c59c7baaa4626f5c01888d50e86e5636e655e) tc358767.c (63f8f3badf799c8b63ff33a489886bc138ce5d09)
1/*
2 * tc358767 eDP bridge driver
3 *
4 * Copyright (C) 2016 CogentEmbedded Inc
5 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
6 *
7 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
8 *

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93
94/* Main Channel */
95#define DP0_SECSAMPLE 0x0640
96#define DP0_VIDSYNCDELAY 0x0644
97#define DP0_TOTALVAL 0x0648
98#define DP0_STARTVAL 0x064c
99#define DP0_ACTIVEVAL 0x0650
100#define DP0_SYNCVAL 0x0654
1/*
2 * tc358767 eDP bridge driver
3 *
4 * Copyright (C) 2016 CogentEmbedded Inc
5 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
6 *
7 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
8 *

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93
94/* Main Channel */
95#define DP0_SECSAMPLE 0x0640
96#define DP0_VIDSYNCDELAY 0x0644
97#define DP0_TOTALVAL 0x0648
98#define DP0_STARTVAL 0x064c
99#define DP0_ACTIVEVAL 0x0650
100#define DP0_SYNCVAL 0x0654
101#define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15)
102#define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31)
103#define DP0_MISC 0x0658
104#define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */
105#define BPC_6 (0 << 5)
106#define BPC_8 (1 << 5)
107
108/* AUX channel */
109#define DP0_AUXCFG0 0x0660
110#define DP0_AUXCFG1 0x0664

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139#define LT_STATUS_MASK (0x1f << 8)
140#define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4)
141#define LT_INTERLANE_ALIGN_DONE BIT(3)
142#define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS)
143#define DP0_SNKLTCHGREQ 0x06d4
144#define DP0_LTLOOPCTRL 0x06d8
145#define DP0_SNKLTCTRL 0x06e4
146
101#define DP0_MISC 0x0658
102#define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */
103#define BPC_6 (0 << 5)
104#define BPC_8 (1 << 5)
105
106/* AUX channel */
107#define DP0_AUXCFG0 0x0660
108#define DP0_AUXCFG1 0x0664

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137#define LT_STATUS_MASK (0x1f << 8)
138#define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4)
139#define LT_INTERLANE_ALIGN_DONE BIT(3)
140#define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS)
141#define DP0_SNKLTCHGREQ 0x06d4
142#define DP0_LTLOOPCTRL 0x06d8
143#define DP0_SNKLTCTRL 0x06e4
144
147#define DP1_SRCCTRL 0x07a0
148
149/* PHY */
150#define DP_PHY_CTRL 0x0800
151#define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
152#define BGREN BIT(25) /* AUX PHY BGR Enable */
153#define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */
154#define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */
155#define PHY_RDY BIT(16) /* PHY Main Channels Ready */
156#define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */
145/* PHY */
146#define DP_PHY_CTRL 0x0800
147#define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
148#define BGREN BIT(25) /* AUX PHY BGR Enable */
149#define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */
150#define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */
151#define PHY_RDY BIT(16) /* PHY Main Channels Ready */
152#define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */
157#define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */
158#define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */
159#define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */
160
161/* PLL */
162#define DP0_PLLCTRL 0x0900
163#define DP1_PLLCTRL 0x0904 /* not defined in DS */
164#define PXL_PLLCTRL 0x0908
165#define PLLUPDATE BIT(2)

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203 struct drm_panel *panel;
204
205 /* link settings */
206 struct tc_edp_link link;
207
208 /* display edid */
209 struct edid *edid;
210 /* current mode */
153#define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */
154#define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */
155
156/* PLL */
157#define DP0_PLLCTRL 0x0900
158#define DP1_PLLCTRL 0x0904 /* not defined in DS */
159#define PXL_PLLCTRL 0x0908
160#define PLLUPDATE BIT(2)

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198 struct drm_panel *panel;
199
200 /* link settings */
201 struct tc_edp_link link;
202
203 /* display edid */
204 struct edid *edid;
205 /* current mode */
211 struct drm_display_mode *mode;
206 const struct drm_display_mode *mode;
212
213 u32 rev;
214 u8 assr;
215
216 struct gpio_desc *sd_gpio;
217 struct gpio_desc *reset_gpio;
218 struct clk *refclk;
219};

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540 return ret;
541}
542
543static int tc_aux_link_setup(struct tc_data *tc)
544{
545 unsigned long rate;
546 u32 value;
547 int ret;
207
208 u32 rev;
209 u8 assr;
210
211 struct gpio_desc *sd_gpio;
212 struct gpio_desc *reset_gpio;
213 struct clk *refclk;
214};

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535 return ret;
536}
537
538static int tc_aux_link_setup(struct tc_data *tc)
539{
540 unsigned long rate;
541 u32 value;
542 int ret;
548 u32 dp_phy_ctrl;
549
550 rate = clk_get_rate(tc->refclk);
551 switch (rate) {
552 case 38400000:
553 value = REF_FREQ_38M4;
554 break;
555 case 26000000:
556 value = REF_FREQ_26M;

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565 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
566 return -EINVAL;
567 }
568
569 /* Setup DP-PHY / PLL */
570 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
571 tc_write(SYS_PLLPARAM, value);
572
543
544 rate = clk_get_rate(tc->refclk);
545 switch (rate) {
546 case 38400000:
547 value = REF_FREQ_38M4;
548 break;
549 case 26000000:
550 value = REF_FREQ_26M;

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559 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
560 return -EINVAL;
561 }
562
563 /* Setup DP-PHY / PLL */
564 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
565 tc_write(SYS_PLLPARAM, value);
566
573 dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN;
574 if (tc->link.base.num_lanes == 2)
575 dp_phy_ctrl |= PHY_2LANE;
576 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
567 tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | BIT(2) | PHY_A0_EN);
577
578 /*
579 * Initially PLLs are in bypass. Force PLL parameter update,
580 * disable PLL bypass, enable PLL
581 */
582 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
583 tc_wait_pll_lock(tc);
584

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652
653 return 0;
654
655err_dpcd_read:
656 dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
657 return ret;
658}
659
568
569 /*
570 * Initially PLLs are in bypass. Force PLL parameter update,
571 * disable PLL bypass, enable PLL
572 */
573 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
574 tc_wait_pll_lock(tc);
575

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643
644 return 0;
645
646err_dpcd_read:
647 dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
648 return ret;
649}
650
660static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode)
651static int tc_set_video_mode(struct tc_data *tc,
652 const struct drm_display_mode *mode)
661{
662 int ret;
663 int vid_sync_dly;
664 int max_tu_symbol;
665
666 int left_margin = mode->htotal - mode->hsync_end;
667 int right_margin = mode->hsync_start - mode->hdisplay;
668 int hsync_len = mode->hsync_end - mode->hsync_start;

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723 tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal));
724
725 tc_write(DP0_STARTVAL,
726 ((upper_margin + vsync_len) << 16) |
727 ((left_margin + hsync_len) << 0));
728
729 tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay));
730
653{
654 int ret;
655 int vid_sync_dly;
656 int max_tu_symbol;
657
658 int left_margin = mode->htotal - mode->hsync_end;
659 int right_margin = mode->hsync_start - mode->hdisplay;
660 int hsync_len = mode->hsync_end - mode->hsync_start;

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715 tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal));
716
717 tc_write(DP0_STARTVAL,
718 ((upper_margin + vsync_len) << 16) |
719 ((left_margin + hsync_len) << 0));
720
721 tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay));
722
731 tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0) |
732 ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? SYNCVAL_HS_POL_ACTIVE_LOW : 0) |
733 ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? SYNCVAL_VS_POL_ACTIVE_LOW : 0));
723 tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0));
734
735 tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
736 DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888);
737
738 tc_write(DP0_MISC, (max_tu_symbol << 23) | (TU_SIZE_RECOMMENDED << 16) |
739 BPC_8);
740
741 return 0;

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835 u32 value;
836 int ret;
837 u8 tmp[8];
838
839 /* display mode should be set at this point */
840 if (!tc->mode)
841 return -EINVAL;
842
724
725 tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
726 DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888);
727
728 tc_write(DP0_MISC, (max_tu_symbol << 23) | (TU_SIZE_RECOMMENDED << 16) |
729 BPC_8);
730
731 return 0;

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825 u32 value;
826 int ret;
827 u8 tmp[8];
828
829 /* display mode should be set at this point */
830 if (!tc->mode)
831 return -EINVAL;
832
843 tc_write(DP0_SRCCTRL, tc_srcctrl(tc));
844 /* SSCG and BW27 on DP1 must be set to the same as on DP0 */
845 tc_write(DP1_SRCCTRL,
846 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
847 ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
833 /* from excel file - DP0_SrcCtrl */
834 tc_write(DP0_SRCCTRL, DP0_SRCCTRL_SCRMBLDIS | DP0_SRCCTRL_EN810B |
835 DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_LANES_2 |
836 DP0_SRCCTRL_BW27 | DP0_SRCCTRL_AUTOCORRECT);
837 /* from excel file - DP1_SrcCtrl */
838 tc_write(0x07a0, 0x00003083);
848
849 rate = clk_get_rate(tc->refclk);
850 switch (rate) {
851 case 38400000:
852 value = REF_FREQ_38M4;
853 break;
854 case 26000000:
855 value = REF_FREQ_26M;

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860 case 13000000:
861 value = REF_FREQ_13M;
862 break;
863 default:
864 return -EINVAL;
865 }
866 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
867 tc_write(SYS_PLLPARAM, value);
839
840 rate = clk_get_rate(tc->refclk);
841 switch (rate) {
842 case 38400000:
843 value = REF_FREQ_38M4;
844 break;
845 case 26000000:
846 value = REF_FREQ_26M;

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851 case 13000000:
852 value = REF_FREQ_13M;
853 break;
854 default:
855 return -EINVAL;
856 }
857 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
858 tc_write(SYS_PLLPARAM, value);
868
869 /* Setup Main Link */
859 /* Setup Main Link */
870 dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
871 if (tc->link.base.num_lanes == 2)
872 dp_phy_ctrl |= PHY_2LANE;
860 dp_phy_ctrl = BGREN | PWR_SW_EN | BIT(2) | PHY_A0_EN | PHY_M0_EN;
873 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
874 msleep(100);
875
876 /* PLL setup */
877 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
878 tc_wait_pll_lock(tc);
879
880 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);

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1113 adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1114
1115 return true;
1116}
1117
1118static enum drm_mode_status tc_connector_mode_valid(struct drm_connector *connector,
1119 struct drm_display_mode *mode)
1120{
861 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
862 msleep(100);
863
864 /* PLL setup */
865 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
866 tc_wait_pll_lock(tc);
867
868 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);

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1101 adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1102
1103 return true;
1104}
1105
1106static enum drm_mode_status tc_connector_mode_valid(struct drm_connector *connector,
1107 struct drm_display_mode *mode)
1108{
1121 struct tc_data *tc = connector_to_tc(connector);
1122 u32 req, avail;
1123 u32 bits_per_pixel = 24;
1124
1125 /* DPI interface clock limitation: upto 154 MHz */
1126 if (mode->clock > 154000)
1127 return MODE_CLOCK_HIGH;
1128
1109 /* DPI interface clock limitation: upto 154 MHz */
1110 if (mode->clock > 154000)
1111 return MODE_CLOCK_HIGH;
1112
1129 req = mode->clock * bits_per_pixel / 8;
1130 avail = tc->link.base.num_lanes * tc->link.base.rate;
1131
1132 if (req > avail)
1133 return MODE_BAD;
1134
1135 return MODE_OK;
1136}
1137
1138static void tc_bridge_mode_set(struct drm_bridge *bridge,
1113 return MODE_OK;
1114}
1115
1116static void tc_bridge_mode_set(struct drm_bridge *bridge,
1139 struct drm_display_mode *mode,
1140 struct drm_display_mode *adj)
1117 const struct drm_display_mode *mode,
1118 const struct drm_display_mode *adj)
1141{
1142 struct tc_data *tc = bridge_to_tc(bridge);
1143
1144 tc->mode = mode;
1145}
1146
1147static int tc_connector_get_modes(struct drm_connector *connector)
1148{

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1204 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1205 struct tc_data *tc = bridge_to_tc(bridge);
1206 struct drm_device *drm = bridge->dev;
1207 int ret;
1208
1209 /* Create eDP connector */
1210 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1211 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs,
1119{
1120 struct tc_data *tc = bridge_to_tc(bridge);
1121
1122 tc->mode = mode;
1123}
1124
1125static int tc_connector_get_modes(struct drm_connector *connector)
1126{

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1182 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1183 struct tc_data *tc = bridge_to_tc(bridge);
1184 struct drm_device *drm = bridge->dev;
1185 int ret;
1186
1187 /* Create eDP connector */
1188 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1189 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs,
1212 tc->panel ? DRM_MODE_CONNECTOR_eDP :
1213 DRM_MODE_CONNECTOR_DisplayPort);
1190 DRM_MODE_CONNECTOR_eDP);
1214 if (ret)
1215 return ret;
1216
1217 if (tc->panel)
1218 drm_panel_attach(tc->panel, &tc->connector);
1219
1220 drm_display_info_set_bus_formats(&tc->connector.display_info,
1221 &bus_format, 1);
1191 if (ret)
1192 return ret;
1193
1194 if (tc->panel)
1195 drm_panel_attach(tc->panel, &tc->connector);
1196
1197 drm_display_info_set_bus_formats(&tc->connector.display_info,
1198 &bus_format, 1);
1222 tc->connector.display_info.bus_flags =
1223 DRM_BUS_FLAG_DE_HIGH |
1224 DRM_BUS_FLAG_PIXDATA_NEGEDGE |
1225 DRM_BUS_FLAG_SYNC_NEGEDGE;
1226 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1227
1228 return 0;
1229}
1230
1231static const struct drm_bridge_funcs tc_bridge_funcs = {
1232 .attach = tc_bridge_attach,
1233 .mode_set = tc_bridge_mode_set,

--- 178 unchanged lines hidden --- 		1199 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1200
1201 return 0;
1202}
1203
1204static const struct drm_bridge_funcs tc_bridge_funcs = {
1205 .attach = tc_bridge_attach,
1206 .mode_set = tc_bridge_mode_set,

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