soc15.h (f5500f385ba344d24468c086eb9c50f5ef4f1419) | soc15.h (44f1bb1fed2596330ab55192ddb280865ebc79d2) |
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1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the --- 34 unchanged lines hidden (view full) --- 43}; 44 45struct soc15_reg_entry { 46 uint32_t hwip; 47 uint32_t inst; 48 uint32_t seg; 49 uint32_t reg_offset; 50 uint32_t reg_value; | 1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the --- 34 unchanged lines hidden (view full) --- 43}; 44 45struct soc15_reg_entry { 46 uint32_t hwip; 47 uint32_t inst; 48 uint32_t seg; 49 uint32_t reg_offset; 50 uint32_t reg_value; |
51 uint32_t se_num; 52 uint32_t instance; |
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51}; 52 | 53}; 54 |
55struct soc15_allowed_register_entry { 56 uint32_t hwip; 57 uint32_t inst; 58 uint32_t seg; 59 uint32_t reg_offset; 60 bool grbm_indexed; 61}; 62 |
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53#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg 54 55#define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset) 56 57#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \ 58 { ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask } 59 60void soc15_grbm_select(struct amdgpu_device *adev, --- 13 unchanged lines hidden --- | 63#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg 64 65#define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset) 66 67#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \ 68 { ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask } 69 70void soc15_grbm_select(struct amdgpu_device *adev, --- 13 unchanged lines hidden --- |