soc15.h (9f4813b531a0b8cc502fcfb142937fe4e9104d77) | soc15.h (46f719696ee62a7637116791bb4f571d030569cd) |
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1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the --- 46 unchanged lines hidden (view full) --- 55struct soc15_allowed_register_entry { 56 uint32_t hwip; 57 uint32_t inst; 58 uint32_t seg; 59 uint32_t reg_offset; 60 bool grbm_indexed; 61}; 62 | 1/* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the --- 46 unchanged lines hidden (view full) --- 55struct soc15_allowed_register_entry { 56 uint32_t hwip; 57 uint32_t inst; 58 uint32_t seg; 59 uint32_t reg_offset; 60 bool grbm_indexed; 61}; 62 |
63struct soc15_ras_field_entry { 64 const char *name; 65 uint32_t hwip; 66 uint32_t inst; 67 uint32_t seg; 68 uint32_t reg_offset; 69 uint32_t sec_count_mask; 70 uint32_t sec_count_shift; 71 uint32_t ded_count_mask; 72 uint32_t ded_count_shift; 73}; 74 |
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63#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg 64 65#define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset) 66 67#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \ 68 { ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask } 69 | 75#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg 76 77#define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset) 78 79#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \ 80 { ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask } 81 |
82#define SOC15_REG_FIELD(reg, field) reg##__##field##_MASK, reg##__##field##__SHIFT 83 |
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70void soc15_grbm_select(struct amdgpu_device *adev, 71 u32 me, u32 pipe, u32 queue, u32 vmid); 72int soc15_set_ip_blocks(struct amdgpu_device *adev); 73 74void soc15_program_register_sequence(struct amdgpu_device *adev, 75 const struct soc15_reg_golden *registers, 76 const u32 array_size); 77 78int vega10_reg_base_init(struct amdgpu_device *adev); 79int vega20_reg_base_init(struct amdgpu_device *adev); 80int arct_reg_base_init(struct amdgpu_device *adev); 81 82void vega10_doorbell_index_init(struct amdgpu_device *adev); 83void vega20_doorbell_index_init(struct amdgpu_device *adev); 84#endif | 84void soc15_grbm_select(struct amdgpu_device *adev, 85 u32 me, u32 pipe, u32 queue, u32 vmid); 86int soc15_set_ip_blocks(struct amdgpu_device *adev); 87 88void soc15_program_register_sequence(struct amdgpu_device *adev, 89 const struct soc15_reg_golden *registers, 90 const u32 array_size); 91 92int vega10_reg_base_init(struct amdgpu_device *adev); 93int vega20_reg_base_init(struct amdgpu_device *adev); 94int arct_reg_base_init(struct amdgpu_device *adev); 95 96void vega10_doorbell_index_init(struct amdgpu_device *adev); 97void vega20_doorbell_index_init(struct amdgpu_device *adev); 98#endif |