soc15.h (2a267e7c41aa88215de2b542de797d03d16ecdfd) soc15.h (5326ad54c5ef01a828cf5a942f6fdbf204ef7d3f)
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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37 u32 hwip;
38 u32 instance;
39 u32 segment;
40 u32 reg;
41 u32 and_mask;
42 u32 or_mask;
43};
44
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

--- 28 unchanged lines hidden (view full) ---

37 u32 hwip;
38 u32 instance;
39 u32 segment;
40 u32 reg;
41 u32 and_mask;
42 u32 or_mask;
43};
44
45struct soc15_reg_entry {
46 uint32_t hwip;
47 uint32_t inst;
48 uint32_t seg;
49 uint32_t reg_offset;
50 uint32_t reg_value;
51};
52
45#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg
46
53#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg
54
55#define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
56
47#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \
48 { ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }
49
50void soc15_grbm_select(struct amdgpu_device *adev,
51 u32 me, u32 pipe, u32 queue, u32 vmid);
52int soc15_set_ip_blocks(struct amdgpu_device *adev);
53
54void soc15_program_register_sequence(struct amdgpu_device *adev,
55 const struct soc15_reg_golden *registers,
56 const u32 array_size);
57
58int vega10_reg_base_init(struct amdgpu_device *adev);
59int vega20_reg_base_init(struct amdgpu_device *adev);
60
61void vega10_doorbell_index_init(struct amdgpu_device *adev);
62void vega20_doorbell_index_init(struct amdgpu_device *adev);
63#endif
57#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \
58 { ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }
59
60void soc15_grbm_select(struct amdgpu_device *adev,
61 u32 me, u32 pipe, u32 queue, u32 vmid);
62int soc15_set_ip_blocks(struct amdgpu_device *adev);
63
64void soc15_program_register_sequence(struct amdgpu_device *adev,
65 const struct soc15_reg_golden *registers,
66 const u32 array_size);
67
68int vega10_reg_base_init(struct amdgpu_device *adev);
69int vega20_reg_base_init(struct amdgpu_device *adev);
70
71void vega10_doorbell_index_init(struct amdgpu_device *adev);
72void vega20_doorbell_index_init(struct amdgpu_device *adev);
73#endif