soc15.h (03ab8e6297acd1bc0eedaa050e2a1635c576fd11) soc15.h (5aa998baab3360d0f1b93d6aff3df924045f956c)
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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95
96#define SOC15_REG_FIELD(reg, field) reg##__##field##_MASK, reg##__##field##__SHIFT
97
98#define SOC15_REG_FIELD_VAL(val, mask, shift) (((val) & mask) >> shift)
99
100#define SOC15_RAS_REG_FIELD_VAL(val, entry, field) SOC15_REG_FIELD_VAL((val), (entry).field##_count_mask, (entry).field##_count_shift)
101
102void soc15_grbm_select(struct amdgpu_device *adev,
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

--- 86 unchanged lines hidden (view full) ---

95
96#define SOC15_REG_FIELD(reg, field) reg##__##field##_MASK, reg##__##field##__SHIFT
97
98#define SOC15_REG_FIELD_VAL(val, mask, shift) (((val) & mask) >> shift)
99
100#define SOC15_RAS_REG_FIELD_VAL(val, entry, field) SOC15_REG_FIELD_VAL((val), (entry).field##_count_mask, (entry).field##_count_shift)
101
102void soc15_grbm_select(struct amdgpu_device *adev,
103 u32 me, u32 pipe, u32 queue, u32 vmid);
103 u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id);
104void soc15_set_virt_ops(struct amdgpu_device *adev);
105
106void soc15_program_register_sequence(struct amdgpu_device *adev,
107 const struct soc15_reg_golden *registers,
108 const u32 array_size);
109
110int vega10_reg_base_init(struct amdgpu_device *adev);
111int vega20_reg_base_init(struct amdgpu_device *adev);
112int arct_reg_base_init(struct amdgpu_device *adev);
113int aldebaran_reg_base_init(struct amdgpu_device *adev);
114
115void vega10_doorbell_index_init(struct amdgpu_device *adev);
116void vega20_doorbell_index_init(struct amdgpu_device *adev);
117#endif
104void soc15_set_virt_ops(struct amdgpu_device *adev);
105
106void soc15_program_register_sequence(struct amdgpu_device *adev,
107 const struct soc15_reg_golden *registers,
108 const u32 array_size);
109
110int vega10_reg_base_init(struct amdgpu_device *adev);
111int vega20_reg_base_init(struct amdgpu_device *adev);
112int arct_reg_base_init(struct amdgpu_device *adev);
113int aldebaran_reg_base_init(struct amdgpu_device *adev);
114
115void vega10_doorbell_index_init(struct amdgpu_device *adev);
116void vega20_doorbell_index_init(struct amdgpu_device *adev);
117#endif