soc15.c (dc93967b8094b64ea3fd85bf933561d89b6951af) soc15.c (062f380725376efab279956b5441071684c2a7ff)
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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60#include "dce_virtual.h"
61#include "mxgpu_ai.h"
62
63#define mmMP0_MISC_CGTT_CTRL0 0x01b9
64#define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
65#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
66#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
67
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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60#include "dce_virtual.h"
61#include "mxgpu_ai.h"
62
63#define mmMP0_MISC_CGTT_CTRL0 0x01b9
64#define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
65#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
66#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
67
68/* for Vega20 register name change */
69#define mmHDP_MEM_POWER_CTRL 0x00d4
70#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
71#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
72#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
73#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
74#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
75/*
76 * Indirect registers accessor
77 */
78static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
79{
80 unsigned long flags, address, data;
81 u32 r;
82 address = adev->nbio_funcs->get_pcie_index_offset(adev);

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608 .set_vga_state = &soc15_vga_set_state,
609 .get_xclk = &soc15_get_xclk,
610 .set_uvd_clocks = &soc15_set_uvd_clocks,
611 .set_vce_clocks = &soc15_set_vce_clocks,
612 .get_config_memsize = &soc15_get_config_memsize,
613 .flush_hdp = &soc15_flush_hdp,
614 .invalidate_hdp = &soc15_invalidate_hdp,
615 .need_full_reset = &soc15_need_full_reset,
68/*
69 * Indirect registers accessor
70 */
71static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
72{
73 unsigned long flags, address, data;
74 u32 r;
75 address = adev->nbio_funcs->get_pcie_index_offset(adev);

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601 .set_vga_state = &soc15_vga_set_state,
602 .get_xclk = &soc15_get_xclk,
603 .set_uvd_clocks = &soc15_set_uvd_clocks,
604 .set_vce_clocks = &soc15_set_vce_clocks,
605 .get_config_memsize = &soc15_get_config_memsize,
606 .flush_hdp = &soc15_flush_hdp,
607 .invalidate_hdp = &soc15_invalidate_hdp,
608 .need_full_reset = &soc15_need_full_reset,
609 .init_doorbell_index = &vega10_doorbell_index_init,
616};
617
618static int soc15_common_early_init(void *handle)
619{
620 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
621
622 adev->smc_rreg = NULL;
623 adev->smc_wreg = NULL;

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872{
873 return 0;
874}
875
876static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
877{
878 uint32_t def, data;
879
610};
611
612static int soc15_common_early_init(void *handle)
613{
614 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
615
616 adev->smc_rreg = NULL;
617 adev->smc_wreg = NULL;

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866{
867 return 0;
868}
869
870static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
871{
872 uint32_t def, data;
873
880 if (adev->asic_type == CHIP_VEGA20) {
881 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
874 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
882
875
883 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
884 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
885 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
886 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
887 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
888 else
889 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
890 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
891 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
892 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
876 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
877 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
878 else
879 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
893
880
894 if (def != data)
895 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
896 } else {
897 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
898
899 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
900 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
901 else
902 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
903
904 if (def != data)
905 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
906 }
881 if (def != data)
882 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
907}
908
909static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
910{
911 uint32_t def, data;
912
913 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
914

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884
885static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
886{
887 uint32_t def, data;
888
889 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
890

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