soc15.c (75a07bcd1d3005bf1560d4756cb98e393269572c) soc15.c (1d789535a03679e5ce0b56a0d32a5e44596dfcdb)
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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151{
152 .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array),
153 .codec_array = rn_video_codecs_decode_array,
154};
155
156static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
157 const struct amdgpu_video_codecs **codecs)
158{
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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151{
152 .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array),
153 .codec_array = rn_video_codecs_decode_array,
154};
155
156static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
157 const struct amdgpu_video_codecs **codecs)
158{
159 if (adev->ip_versions[VCE_HWIP]) {
160 switch (adev->ip_versions[VCE_HWIP]) {
159 if (adev->ip_versions[VCE_HWIP][0]) {
160 switch (adev->ip_versions[VCE_HWIP][0]) {
161 case IP_VERSION(4, 0, 0):
162 case IP_VERSION(4, 1, 0):
163 if (encode)
164 *codecs = &vega_video_codecs_encode;
165 else
166 *codecs = &vega_video_codecs_decode;
167 return 0;
168 default:
169 return -EINVAL;
170 }
171 } else {
161 case IP_VERSION(4, 0, 0):
162 case IP_VERSION(4, 1, 0):
163 if (encode)
164 *codecs = &vega_video_codecs_encode;
165 else
166 *codecs = &vega_video_codecs_decode;
167 return 0;
168 default:
169 return -EINVAL;
170 }
171 } else {
172 switch (adev->ip_versions[UVD_HWIP]) {
172 switch (adev->ip_versions[UVD_HWIP][0]) {
173 case IP_VERSION(1, 0, 0):
174 case IP_VERSION(1, 0, 1):
175 if (encode)
176 *codecs = &vega_video_codecs_encode;
177 else
178 *codecs = &rv_video_codecs_decode;
179 return 0;
180 case IP_VERSION(2, 5, 0):

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336{
337 return adev->nbio.funcs->get_memsize(adev);
338}
339
340static u32 soc15_get_xclk(struct amdgpu_device *adev)
341{
342 u32 reference_clock = adev->clock.spll.reference_freq;
343
173 case IP_VERSION(1, 0, 0):
174 case IP_VERSION(1, 0, 1):
175 if (encode)
176 *codecs = &vega_video_codecs_encode;
177 else
178 *codecs = &rv_video_codecs_decode;
179 return 0;
180 case IP_VERSION(2, 5, 0):

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336{
337 return adev->nbio.funcs->get_memsize(adev);
338}
339
340static u32 soc15_get_xclk(struct amdgpu_device *adev)
341{
342 u32 reference_clock = adev->clock.spll.reference_freq;
343
344 if (adev->ip_versions[MP1_HWIP] == IP_VERSION(12, 0, 0) ||
345 adev->ip_versions[MP1_HWIP] == IP_VERSION(12, 0, 1))
344 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) ||
345 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1))
346 return 10000;
346 return 10000;
347 if (adev->ip_versions[MP1_HWIP] == IP_VERSION(10, 0, 0) ||
348 adev->ip_versions[MP1_HWIP] == IP_VERSION(10, 0, 1))
347 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) ||
348 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1))
349 return reference_clock / 4;
350
351 return reference_clock;
352}
353
354
355void soc15_grbm_select(struct amdgpu_device *adev,
356 u32 me, u32 pipe, u32 queue, u32 vmid)

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571 return AMD_RESET_METHOD_MODE2;
572 return amdgpu_reset_method;
573 }
574
575 if (amdgpu_reset_method != -1)
576 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
577 amdgpu_reset_method);
578
349 return reference_clock / 4;
350
351 return reference_clock;
352}
353
354
355void soc15_grbm_select(struct amdgpu_device *adev,
356 u32 me, u32 pipe, u32 queue, u32 vmid)

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571 return AMD_RESET_METHOD_MODE2;
572 return amdgpu_reset_method;
573 }
574
575 if (amdgpu_reset_method != -1)
576 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
577 amdgpu_reset_method);
578
579 switch (adev->ip_versions[MP1_HWIP]) {
579 switch (adev->ip_versions[MP1_HWIP][0]) {
580 case IP_VERSION(10, 0, 0):
581 case IP_VERSION(10, 0, 1):
582 case IP_VERSION(12, 0, 0):
583 case IP_VERSION(12, 0, 1):
584 return AMD_RESET_METHOD_MODE2;
585 case IP_VERSION(9, 0, 0):
586 case IP_VERSION(11, 0, 2):
587 if (adev->asic_type == CHIP_VEGA20) {

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636 default:
637 dev_info(adev->dev, "MODE1 reset\n");
638 return amdgpu_device_mode1_reset(adev);
639 }
640}
641
642static bool soc15_supports_baco(struct amdgpu_device *adev)
643{
580 case IP_VERSION(10, 0, 0):
581 case IP_VERSION(10, 0, 1):
582 case IP_VERSION(12, 0, 0):
583 case IP_VERSION(12, 0, 1):
584 return AMD_RESET_METHOD_MODE2;
585 case IP_VERSION(9, 0, 0):
586 case IP_VERSION(11, 0, 2):
587 if (adev->asic_type == CHIP_VEGA20) {

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636 default:
637 dev_info(adev->dev, "MODE1 reset\n");
638 return amdgpu_device_mode1_reset(adev);
639 }
640}
641
642static bool soc15_supports_baco(struct amdgpu_device *adev)
643{
644 switch (adev->ip_versions[MP1_HWIP]) {
644 switch (adev->ip_versions[MP1_HWIP][0]) {
645 case IP_VERSION(9, 0, 0):
646 case IP_VERSION(11, 0, 2):
647 if (adev->asic_type == CHIP_VEGA20) {
648 if (adev->psp.sos.fw_version >= 0x80067)
649 return amdgpu_dpm_is_baco_supported(adev);
650 return false;
651 } else {
652 return amdgpu_dpm_is_baco_supported(adev);

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1167 adev->se_cac_rreg = &soc15_se_cac_rreg;
1168 adev->se_cac_wreg = &soc15_se_cac_wreg;
1169
1170 adev->rev_id = soc15_get_rev_id(adev);
1171 adev->external_rev_id = 0xFF;
1172 /* TODO: split the GC and PG flags based on the relevant IP version for which
1173 * they are relevant.
1174 */
645 case IP_VERSION(9, 0, 0):
646 case IP_VERSION(11, 0, 2):
647 if (adev->asic_type == CHIP_VEGA20) {
648 if (adev->psp.sos.fw_version >= 0x80067)
649 return amdgpu_dpm_is_baco_supported(adev);
650 return false;
651 } else {
652 return amdgpu_dpm_is_baco_supported(adev);

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1167 adev->se_cac_rreg = &soc15_se_cac_rreg;
1168 adev->se_cac_wreg = &soc15_se_cac_wreg;
1169
1170 adev->rev_id = soc15_get_rev_id(adev);
1171 adev->external_rev_id = 0xFF;
1172 /* TODO: split the GC and PG flags based on the relevant IP version for which
1173 * they are relevant.
1174 */
1175 switch (adev->ip_versions[GC_HWIP]) {
1175 switch (adev->ip_versions[GC_HWIP][0]) {
1176 case IP_VERSION(9, 0, 1):
1177 adev->asic_funcs = &soc15_asic_funcs;
1178 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1179 AMD_CG_SUPPORT_GFX_MGLS |
1180 AMD_CG_SUPPORT_GFX_RLC_LS |
1181 AMD_CG_SUPPORT_GFX_CP_LS |
1182 AMD_CG_SUPPORT_GFX_3D_CGCG |
1183 AMD_CG_SUPPORT_GFX_3D_CGLS |

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1577static int soc15_common_set_clockgating_state(void *handle,
1578 enum amd_clockgating_state state)
1579{
1580 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1581
1582 if (amdgpu_sriov_vf(adev))
1583 return 0;
1584
1176 case IP_VERSION(9, 0, 1):
1177 adev->asic_funcs = &soc15_asic_funcs;
1178 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1179 AMD_CG_SUPPORT_GFX_MGLS |
1180 AMD_CG_SUPPORT_GFX_RLC_LS |
1181 AMD_CG_SUPPORT_GFX_CP_LS |
1182 AMD_CG_SUPPORT_GFX_3D_CGCG |
1183 AMD_CG_SUPPORT_GFX_3D_CGLS |

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1577static int soc15_common_set_clockgating_state(void *handle,
1578 enum amd_clockgating_state state)
1579{
1580 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1581
1582 if (amdgpu_sriov_vf(adev))
1583 return 0;
1584
1585 switch (adev->ip_versions[NBIO_HWIP]) {
1585 switch (adev->ip_versions[NBIO_HWIP][0]) {
1586 case IP_VERSION(6, 1, 0):
1587 case IP_VERSION(6, 2, 0):
1588 case IP_VERSION(7, 4, 0):
1589 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1590 state == AMD_CG_STATE_GATE);
1591 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1592 state == AMD_CG_STATE_GATE);
1593 adev->hdp.funcs->update_clock_gating(adev,

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1633
1634 if (amdgpu_sriov_vf(adev))
1635 *flags = 0;
1636
1637 adev->nbio.funcs->get_clockgating_state(adev, flags);
1638
1639 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1640
1586 case IP_VERSION(6, 1, 0):
1587 case IP_VERSION(6, 2, 0):
1588 case IP_VERSION(7, 4, 0):
1589 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1590 state == AMD_CG_STATE_GATE);
1591 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1592 state == AMD_CG_STATE_GATE);
1593 adev->hdp.funcs->update_clock_gating(adev,

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1633
1634 if (amdgpu_sriov_vf(adev))
1635 *flags = 0;
1636
1637 adev->nbio.funcs->get_clockgating_state(adev, flags);
1638
1639 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1640
1641 if (adev->ip_versions[MP0_HWIP] != IP_VERSION(13, 0, 2)) {
1641 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2)) {
1642
1643 /* AMD_CG_SUPPORT_DRM_MGCG */
1644 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1645 if (!(data & 0x01000000))
1646 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1647
1648 /* AMD_CG_SUPPORT_DRM_LS */
1649 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));

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1643 /* AMD_CG_SUPPORT_DRM_MGCG */
1644 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1645 if (!(data & 0x01000000))
1646 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1647
1648 /* AMD_CG_SUPPORT_DRM_LS */
1649 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));

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