nv.c (933c8a93e2416c615e45438a0e58a656aec5902f) nv.c (157e72e831cb8f323108b5df6d0b148aef9507fb)
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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48#include "gmc_v10_0.h"
49#include "gfxhub_v2_0.h"
50#include "mmhub_v2_0.h"
51#include "nbio_v2_3.h"
52#include "nv.h"
53#include "navi10_ih.h"
54#include "gfx_v10_0.h"
55#include "sdma_v5_0.h"
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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48#include "gmc_v10_0.h"
49#include "gfxhub_v2_0.h"
50#include "mmhub_v2_0.h"
51#include "nbio_v2_3.h"
52#include "nv.h"
53#include "navi10_ih.h"
54#include "gfx_v10_0.h"
55#include "sdma_v5_0.h"
56#include "sdma_v5_2.h"
56#include "vcn_v2_0.h"
57#include "jpeg_v2_0.h"
58#include "dce_virtual.h"
59#include "mes_v10_1.h"
60#include "mxgpu_nv.h"
61
62static const struct amd_ip_funcs nv_common_ip_funcs;
63

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483 if (!amdgpu_sriov_vf(adev))
484 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
485 break;
486 case CHIP_SIENNA_CICHLID:
487 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
488 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
489 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
490 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
57#include "vcn_v2_0.h"
58#include "jpeg_v2_0.h"
59#include "dce_virtual.h"
60#include "mes_v10_1.h"
61#include "mxgpu_nv.h"
62
63static const struct amd_ip_funcs nv_common_ip_funcs;
64

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484 if (!amdgpu_sriov_vf(adev))
485 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
486 break;
487 case CHIP_SIENNA_CICHLID:
488 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
489 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
490 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
491 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
492 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
491 break;
492 default:
493 return -EINVAL;
494 }
495
496 return 0;
497}
498

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561 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
562 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
563 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
564 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
565 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
566 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
567 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
568 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
493 break;
494 default:
495 return -EINVAL;
496 }
497
498 return 0;
499}
500

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563 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
564 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
565 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
566 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
567 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
568 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
569 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
570 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
571 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
572 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
569 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
570 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
571 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
572 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
573 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
574 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
575 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
576

--- 413 unchanged lines hidden --- 		573 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
574 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
575 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
576 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
577 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
578 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
579 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
580

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