amdgpu.h (bd607166af7fe31f8d8e9c575f4561a4b56b9f24) amdgpu.h (c8e42d57859d5055bfe3313cfd5dc025097b753e)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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383 unsigned soffset;
384 unsigned eoffset;
385 struct dma_fence *fence;
386};
387
388int amdgpu_fence_slab_init(void);
389void amdgpu_fence_slab_fini(void);
390
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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383 unsigned soffset;
384 unsigned eoffset;
385 struct dma_fence *fence;
386};
387
388int amdgpu_fence_slab_init(void);
389void amdgpu_fence_slab_fini(void);
390
391enum amdgpu_ib_pool_type {
392 AMDGPU_IB_POOL_NORMAL = 0,
393 AMDGPU_IB_POOL_VM,
394 AMDGPU_IB_POOL_DIRECT,
395
396 AMDGPU_IB_POOL_MAX
397};
391/*
392 * IRQS.
393 */
394
395struct amdgpu_flip_work {
396 struct delayed_work flip_work;
397 struct work_struct unpin_work;
398 struct amdgpu_device *adev;

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434 struct mutex bo_list_lock;
435 struct idr bo_list_handles;
436 struct amdgpu_ctx_mgr ctx_mgr;
437};
438
439int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
440
441int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
398/*
399 * IRQS.
400 */
401
402struct amdgpu_flip_work {
403 struct delayed_work flip_work;
404 struct work_struct unpin_work;
405 struct amdgpu_device *adev;

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441 struct mutex bo_list_lock;
442 struct idr bo_list_handles;
443 struct amdgpu_ctx_mgr ctx_mgr;
444};
445
446int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
447
448int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
442 unsigned size, struct amdgpu_ib *ib);
449 unsigned size,
450 enum amdgpu_ib_pool_type pool,
451 struct amdgpu_ib *ib);
443void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
444 struct dma_fence *f);
445int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
446 struct amdgpu_ib *ibs, struct amdgpu_job *job,
447 struct dma_fence **f);
448int amdgpu_ib_pool_init(struct amdgpu_device *adev);
449void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
450int amdgpu_ib_ring_tests(struct amdgpu_device *adev);

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838 struct amdgpu_irq_src pageflip_irq;
839 struct amdgpu_irq_src hpd_irq;
840
841 /* rings */
842 u64 fence_context;
843 unsigned num_rings;
844 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
845 bool ib_pool_ready;
452void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
453 struct dma_fence *f);
454int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
455 struct amdgpu_ib *ibs, struct amdgpu_job *job,
456 struct dma_fence **f);
457int amdgpu_ib_pool_init(struct amdgpu_device *adev);
458void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
459int amdgpu_ib_ring_tests(struct amdgpu_device *adev);

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847 struct amdgpu_irq_src pageflip_irq;
848 struct amdgpu_irq_src hpd_irq;
849
850 /* rings */
851 u64 fence_context;
852 unsigned num_rings;
853 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
854 bool ib_pool_ready;
846 struct amdgpu_sa_manager ring_tmp_bo;
855 struct amdgpu_sa_manager ring_tmp_bo[AMDGPU_IB_POOL_MAX];
847
848 /* interrupts */
849 struct amdgpu_irq irq;
850
851 /* powerplay */
852 struct amd_powerplay powerplay;
853 bool pp_force_state_enabled;
854

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857 /* interrupts */
858 struct amdgpu_irq irq;
859
860 /* powerplay */
861 struct amd_powerplay powerplay;
862 bool pp_force_state_enabled;
863

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