amdgpu.h (770d13b19fdf365a99e559f1d47f1380910a947d) amdgpu.h (132f34e4b558488cc8d153a1d18833054a76e44c)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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328
329 /* for linear pte/pde updates without addr mapping */
330 void (*set_pte_pde)(struct amdgpu_ib *ib,
331 uint64_t pe,
332 uint64_t addr, unsigned count,
333 uint32_t incr, uint64_t flags);
334};
335
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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328
329 /* for linear pte/pde updates without addr mapping */
330 void (*set_pte_pde)(struct amdgpu_ib *ib,
331 uint64_t pe,
332 uint64_t addr, unsigned count,
333 uint32_t incr, uint64_t flags);
334};
335
336/* provided by the gmc block */
337struct amdgpu_gart_funcs {
338 /* flush the vm tlb via mmio */
339 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
340 uint32_t vmid);
341 /* write pte/pde updates using the cpu */
342 int (*set_pte_pde)(struct amdgpu_device *adev,
343 void *cpu_pt_addr, /* cpu addr of page table */
344 uint32_t gpu_page_idx, /* pte/pde to update */
345 uint64_t addr, /* addr to write into pte/pde */
346 uint64_t flags); /* access flags */
347 /* enable/disable PRT support */
348 void (*set_prt)(struct amdgpu_device *adev, bool enable);
349 /* set pte flags based per asic */
350 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
351 uint32_t flags);
352 /* get the pde for a given mc addr */
353 void (*get_vm_pde)(struct amdgpu_device *adev, int level,
354 u64 *dst, u64 *flags);
355 uint32_t (*get_invalidate_req)(unsigned int vmid);
356};
357
358/* provided by the ih block */
359struct amdgpu_ih_funcs {
360 /* ring read/write ptr handling, called from interrupt context */
361 u32 (*get_wptr)(struct amdgpu_device *adev);
362 bool (*prescreen_iv)(struct amdgpu_device *adev);
363 void (*decode_iv)(struct amdgpu_device *adev,
364 struct amdgpu_iv_entry *entry);
365 void (*set_rptr)(struct amdgpu_device *adev);

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1792#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1793#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1794#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1795#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1796#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1797#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1798#define amdgpu_asic_flush_hdp(adev) (adev)->asic_funcs->flush_hdp((adev))
1799#define amdgpu_asic_invalidate_hdp(adev) (adev)->asic_funcs->invalidate_hdp((adev))
336/* provided by the ih block */
337struct amdgpu_ih_funcs {
338 /* ring read/write ptr handling, called from interrupt context */
339 u32 (*get_wptr)(struct amdgpu_device *adev);
340 bool (*prescreen_iv)(struct amdgpu_device *adev);
341 void (*decode_iv)(struct amdgpu_device *adev,
342 struct amdgpu_iv_entry *entry);
343 void (*set_rptr)(struct amdgpu_device *adev);

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1770#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1771#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1772#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1773#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1774#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1775#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1776#define amdgpu_asic_flush_hdp(adev) (adev)->asic_funcs->flush_hdp((adev))
1777#define amdgpu_asic_invalidate_hdp(adev) (adev)->asic_funcs->invalidate_hdp((adev))
1800#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
1801#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
1802#define amdgpu_gart_get_vm_pde(adev, level, dst, flags) (adev)->gart.gart_funcs->get_vm_pde((adev), (level), (dst), (flags))
1778#define amdgpu_gmc_flush_gpu_tlb(adev, vmid) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid))
1779#define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
1780#define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
1781#define amdgpu_gmc_get_pte_flags(adev, flags) (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags))
1803#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
1804#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
1805#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
1782#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
1783#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
1784#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
1806#define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
1807#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1808#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
1809#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
1810#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1811#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1812#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
1813#define amdgpu_ring_emit_ib(r, ib, vmid, c) (r)->funcs->emit_ib((r), (ib), (vmid), (c))
1814#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))

--- 142 unchanged lines hidden --- 		1785#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1786#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
1787#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
1788#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1789#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1790#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
1791#define amdgpu_ring_emit_ib(r, ib, vmid, c) (r)->funcs->emit_ib((r), (ib), (vmid), (c))
1792#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))

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