| amdgpu.h (6670ee2ef219ac9e1c836a277dda0c949ad8b1ff) | amdgpu.h (8a791dabea181607f27aacb89c5e75a2eaaf0586) |
|---|---|
| 1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation --- 14 unchanged lines hidden (view full) --- 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#ifndef __AMDGPU_H__ 29#define __AMDGPU_H__ 30 | 1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation --- 14 unchanged lines hidden (view full) --- 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#ifndef __AMDGPU_H__ 29#define __AMDGPU_H__ 30 |
| 31#ifdef pr_fmt 32#undef pr_fmt 33#endif 34 35#define pr_fmt(fmt) "amdgpu: " fmt 36 37#ifdef dev_fmt 38#undef dev_fmt 39#endif 40 41#define dev_fmt(fmt) "amdgpu: " fmt 42 |
|
| 31#include "amdgpu_ctx.h" 32 33#include <linux/atomic.h> 34#include <linux/wait.h> 35#include <linux/list.h> 36#include <linux/kref.h> 37#include <linux/rbtree.h> 38#include <linux/hashtable.h> --- 117 unchanged lines hidden (view full) --- 156extern uint amdgpu_force_long_training; 157extern int amdgpu_job_hang_limit; 158extern int amdgpu_lbpw; 159extern int amdgpu_compute_multipipe; 160extern int amdgpu_gpu_recovery; 161extern int amdgpu_emu_mode; 162extern uint amdgpu_smu_memory_pool_size; 163extern uint amdgpu_dc_feature_mask; | 43#include "amdgpu_ctx.h" 44 45#include <linux/atomic.h> 46#include <linux/wait.h> 47#include <linux/list.h> 48#include <linux/kref.h> 49#include <linux/rbtree.h> 50#include <linux/hashtable.h> --- 117 unchanged lines hidden (view full) --- 168extern uint amdgpu_force_long_training; 169extern int amdgpu_job_hang_limit; 170extern int amdgpu_lbpw; 171extern int amdgpu_compute_multipipe; 172extern int amdgpu_gpu_recovery; 173extern int amdgpu_emu_mode; 174extern uint amdgpu_smu_memory_pool_size; 175extern uint amdgpu_dc_feature_mask; |
| 176extern uint amdgpu_dc_debug_mask; |
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| 164extern uint amdgpu_dm_abm_level; 165extern struct amdgpu_mgpu_info mgpu_info; 166extern int amdgpu_ras_enable; 167extern uint amdgpu_ras_mask; 168extern int amdgpu_async_gfx_ring; 169extern int amdgpu_mcbp; 170extern int amdgpu_discovery; 171extern int amdgpu_mes; 172extern int amdgpu_noretry; 173extern int amdgpu_force_asic_type; 174#ifdef CONFIG_HSA_AMD 175extern int sched_policy; 176#else 177static const int sched_policy = KFD_SCHED_POLICY_HWS; 178#endif 179 | 177extern uint amdgpu_dm_abm_level; 178extern struct amdgpu_mgpu_info mgpu_info; 179extern int amdgpu_ras_enable; 180extern uint amdgpu_ras_mask; 181extern int amdgpu_async_gfx_ring; 182extern int amdgpu_mcbp; 183extern int amdgpu_discovery; 184extern int amdgpu_mes; 185extern int amdgpu_noretry; 186extern int amdgpu_force_asic_type; 187#ifdef CONFIG_HSA_AMD 188extern int sched_policy; 189#else 190static const int sched_policy = KFD_SCHED_POLICY_HWS; 191#endif 192 |
| 193extern int amdgpu_tmz; 194 |
|
| 180#ifdef CONFIG_DRM_AMDGPU_SI 181extern int amdgpu_si_support; 182#endif 183#ifdef CONFIG_DRM_AMDGPU_CIK 184extern int amdgpu_cik_support; 185#endif 186 187#define AMDGPU_VM_MAX_NUM_CTX 4096 188#define AMDGPU_SG_THRESHOLD (256*1024*1024) 189#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 190#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 191#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 192#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) | 195#ifdef CONFIG_DRM_AMDGPU_SI 196extern int amdgpu_si_support; 197#endif 198#ifdef CONFIG_DRM_AMDGPU_CIK 199extern int amdgpu_cik_support; 200#endif 201 202#define AMDGPU_VM_MAX_NUM_CTX 4096 203#define AMDGPU_SG_THRESHOLD (256*1024*1024) 204#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 205#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 206#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 207#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
| 193/* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 194#define AMDGPU_IB_POOL_SIZE 16 | |
| 195#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 196#define AMDGPUFB_CONN_LIMIT 4 197#define AMDGPU_BIOS_NUM_SCRATCH 16 198 199/* hard reset data */ 200#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 201 202/* reset flags */ --- 231 unchanged lines hidden (view full) --- 434 struct mutex bo_list_lock; 435 struct idr bo_list_handles; 436 struct amdgpu_ctx_mgr ctx_mgr; 437}; 438 439int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 440 441int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, | 208#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 209#define AMDGPUFB_CONN_LIMIT 4 210#define AMDGPU_BIOS_NUM_SCRATCH 16 211 212/* hard reset data */ 213#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 214 215/* reset flags */ --- 231 unchanged lines hidden (view full) --- 447 struct mutex bo_list_lock; 448 struct idr bo_list_handles; 449 struct amdgpu_ctx_mgr ctx_mgr; 450}; 451 452int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 453 454int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
| 442 unsigned size, struct amdgpu_ib *ib); | 455 unsigned size, 456 enum amdgpu_ib_pool_type pool, 457 struct amdgpu_ib *ib); |
| 443void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 444 struct dma_fence *f); 445int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 446 struct amdgpu_ib *ibs, struct amdgpu_job *job, 447 struct dma_fence **f); 448int amdgpu_ib_pool_init(struct amdgpu_device *adev); 449void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 450int amdgpu_ib_ring_tests(struct amdgpu_device *adev); --- 56 unchanged lines hidden (view full) --- 507 uint32_t value) 508{ 509 p->job->ibs[ib_idx].ptr[idx] = value; 510} 511 512/* 513 * Writeback 514 */ | 458void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 459 struct dma_fence *f); 460int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 461 struct amdgpu_ib *ibs, struct amdgpu_job *job, 462 struct dma_fence **f); 463int amdgpu_ib_pool_init(struct amdgpu_device *adev); 464void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 465int amdgpu_ib_ring_tests(struct amdgpu_device *adev); --- 56 unchanged lines hidden (view full) --- 522 uint32_t value) 523{ 524 p->job->ibs[ib_idx].ptr[idx] = value; 525} 526 527/* 528 * Writeback 529 */ |
| 515#define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ | 530#define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ |
| 516 517struct amdgpu_wb { 518 struct amdgpu_bo *wb_obj; 519 volatile uint32_t *wb; 520 uint64_t gpu_addr; 521 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 522 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 523}; --- 222 unchanged lines hidden (view full) --- 746 bool have_disp_power_ref; 747 bool have_atomics_support; 748 749 /* BIOS */ 750 bool is_atom_fw; 751 uint8_t *bios; 752 uint32_t bios_size; 753 struct amdgpu_bo *stolen_vga_memory; | 531 532struct amdgpu_wb { 533 struct amdgpu_bo *wb_obj; 534 volatile uint32_t *wb; 535 uint64_t gpu_addr; 536 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 537 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 538}; --- 222 unchanged lines hidden (view full) --- 761 bool have_disp_power_ref; 762 bool have_atomics_support; 763 764 /* BIOS */ 765 bool is_atom_fw; 766 uint8_t *bios; 767 uint32_t bios_size; 768 struct amdgpu_bo *stolen_vga_memory; |
| 754 struct amdgpu_bo *discovery_memory; | |
| 755 uint32_t bios_scratch_reg_offset; 756 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 757 758 /* Register/doorbell mmio */ 759 resource_size_t rmmio_base; 760 resource_size_t rmmio_size; 761 void __iomem *rmmio; 762 /* protects concurrent MM_INDEX/DATA based register access */ --- 75 unchanged lines hidden (view full) --- 838 struct amdgpu_irq_src pageflip_irq; 839 struct amdgpu_irq_src hpd_irq; 840 841 /* rings */ 842 u64 fence_context; 843 unsigned num_rings; 844 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 845 bool ib_pool_ready; | 769 uint32_t bios_scratch_reg_offset; 770 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 771 772 /* Register/doorbell mmio */ 773 resource_size_t rmmio_base; 774 resource_size_t rmmio_size; 775 void __iomem *rmmio; 776 /* protects concurrent MM_INDEX/DATA based register access */ --- 75 unchanged lines hidden (view full) --- 852 struct amdgpu_irq_src pageflip_irq; 853 struct amdgpu_irq_src hpd_irq; 854 855 /* rings */ 856 u64 fence_context; 857 unsigned num_rings; 858 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 859 bool ib_pool_ready; |
| 846 struct amdgpu_sa_manager ring_tmp_bo; | 860 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 861 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; |
| 847 848 /* interrupts */ 849 struct amdgpu_irq irq; 850 851 /* powerplay */ 852 struct amd_powerplay powerplay; 853 bool pp_force_state_enabled; 854 --- 43 unchanged lines hidden (view full) --- 898 899 /* UMC */ 900 struct amdgpu_umc umc; 901 902 /* display related functionality */ 903 struct amdgpu_display_manager dm; 904 905 /* discovery */ | 862 863 /* interrupts */ 864 struct amdgpu_irq irq; 865 866 /* powerplay */ 867 struct amd_powerplay powerplay; 868 bool pp_force_state_enabled; 869 --- 43 unchanged lines hidden (view full) --- 913 914 /* UMC */ 915 struct amdgpu_umc umc; 916 917 /* display related functionality */ 918 struct amdgpu_display_manager dm; 919 920 /* discovery */ |
| 906 uint8_t *discovery; | 921 uint8_t *discovery_bin; 922 uint32_t discovery_tmr_size; 923 struct amdgpu_bo *discovery_memory; |
| 907 908 /* mes */ 909 bool enable_mes; 910 struct amdgpu_mes mes; 911 912 /* df */ 913 struct amdgpu_df df; 914 915 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 916 int num_ip_blocks; 917 struct mutex mn_lock; 918 DECLARE_HASHTABLE(mn_hash, 7); 919 920 /* tracking pinned memory */ 921 atomic64_t vram_pin_size; 922 atomic64_t visible_pin_size; 923 atomic64_t gart_pin_size; 924 925 /* soc15 register offset based on ip, instance and segment */ | 924 925 /* mes */ 926 bool enable_mes; 927 struct amdgpu_mes mes; 928 929 /* df */ 930 struct amdgpu_df df; 931 932 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 933 int num_ip_blocks; 934 struct mutex mn_lock; 935 DECLARE_HASHTABLE(mn_hash, 7); 936 937 /* tracking pinned memory */ 938 atomic64_t vram_pin_size; 939 atomic64_t visible_pin_size; 940 atomic64_t gart_pin_size; 941 942 /* soc15 register offset based on ip, instance and segment */ |
| 926 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; | 943 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; |
| 927 928 /* delayed work_func for deferring clockgating during resume */ 929 struct delayed_work delayed_init_work; 930 931 struct amdgpu_virt virt; 932 /* firmware VRAM reservation */ 933 struct amdgpu_fw_vram_usage fw_vram_usage; 934 935 /* link all shadow bo */ 936 struct list_head shadow_list; 937 struct mutex shadow_list_lock; | 944 945 /* delayed work_func for deferring clockgating during resume */ 946 struct delayed_work delayed_init_work; 947 948 struct amdgpu_virt virt; 949 /* firmware VRAM reservation */ 950 struct amdgpu_fw_vram_usage fw_vram_usage; 951 952 /* link all shadow bo */ 953 struct list_head shadow_list; 954 struct mutex shadow_list_lock; |
| 938 /* keep an lru list of rings by HW IP */ 939 struct list_head ring_lru_list; 940 spinlock_t ring_lru_list_lock; | |
| 941 942 /* record hw reset is performed */ 943 bool has_hw_reset; 944 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 945 946 /* s3/s4 mask */ 947 bool in_suspend; 948 bool in_hibernate; 949 | 955 956 /* record hw reset is performed */ 957 bool has_hw_reset; 958 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 959 960 /* s3/s4 mask */ 961 bool in_suspend; 962 bool in_hibernate; 963 |
| 950 /* record last mm index being written through WREG32*/ 951 unsigned long last_mm_index; | |
| 952 bool in_gpu_reset; 953 enum pp_mp1_state mp1_state; 954 struct mutex lock_reset; 955 struct amdgpu_doorbell_index doorbell_index; 956 957 struct mutex notifier_lock; 958 959 int asic_reset_res; 960 struct work_struct xgmi_reset_work; 961 962 long gfx_timeout; 963 long sdma_timeout; 964 long video_timeout; 965 long compute_timeout; 966 967 uint64_t unique_id; 968 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 969 | 964 bool in_gpu_reset; 965 enum pp_mp1_state mp1_state; 966 struct mutex lock_reset; 967 struct amdgpu_doorbell_index doorbell_index; 968 969 struct mutex notifier_lock; 970 971 int asic_reset_res; 972 struct work_struct xgmi_reset_work; 973 974 long gfx_timeout; 975 long sdma_timeout; 976 long video_timeout; 977 long compute_timeout; 978 979 uint64_t unique_id; 980 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 981 |
| 970 /* device pstate */ 971 int pstate; | |
| 972 /* enable runtime pm on the device */ 973 bool runpm; 974 bool in_runpm; 975 976 bool pm_sysfs_en; 977 bool ucode_sysfs_en; | 982 /* enable runtime pm on the device */ 983 bool runpm; 984 bool in_runpm; 985 986 bool pm_sysfs_en; 987 bool ucode_sysfs_en; |
| 988 989 /* Chip product information */ 990 char product_number[16]; 991 char product_name[32]; 992 char serial[16]; 993 994 struct amdgpu_autodump autodump; |
|
| 978}; 979 980static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 981{ 982 return container_of(bdev, struct amdgpu_device, mman.bdev); 983} 984 985int amdgpu_device_init(struct amdgpu_device *adev, 986 struct drm_device *ddev, 987 struct pci_dev *pdev, 988 uint32_t flags); 989void amdgpu_device_fini(struct amdgpu_device *adev); 990int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 991 992void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 993 uint32_t *buf, size_t size, bool write); | 995}; 996 997static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 998{ 999 return container_of(bdev, struct amdgpu_device, mman.bdev); 1000} 1001 1002int amdgpu_device_init(struct amdgpu_device *adev, 1003 struct drm_device *ddev, 1004 struct pci_dev *pdev, 1005 uint32_t flags); 1006void amdgpu_device_fini(struct amdgpu_device *adev); 1007int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1008 1009void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1010 uint32_t *buf, size_t size, bool write); |
| 994uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, | 1011uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg, 1012 uint32_t acc_flags); 1013void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, |
| 995 uint32_t acc_flags); | 1014 uint32_t acc_flags); |
| 996void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 997 uint32_t acc_flags); | |
| 998void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 999 uint32_t acc_flags); 1000void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1001uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1002 1003u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1004void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1005 1006bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1007bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1008 1009int emu_soc_asic_init(struct amdgpu_device *adev); 1010 1011/* 1012 * Registers read & write functions. 1013 */ | 1015void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1016 uint32_t acc_flags); 1017void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1018uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1019 1020u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1021void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1022 1023bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1024bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1025 1026int emu_soc_asic_init(struct amdgpu_device *adev); 1027 1028/* 1029 * Registers read & write functions. 1030 */ |
| 1014 1015#define AMDGPU_REGS_IDX (1<<0) | |
| 1016#define AMDGPU_REGS_NO_KIQ (1<<1) | 1031#define AMDGPU_REGS_NO_KIQ (1<<1) |
| 1017#define AMDGPU_REGS_KIQ (1<<2) | |
| 1018 | 1032 |
| 1019#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1020#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) | 1033#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1034#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) |
| 1021 | 1035 |
| 1022#define RREG32_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_KIQ) 1023#define WREG32_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_KIQ) | 1036#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1037#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) |
| 1024 1025#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1026#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1027 | 1038 1039#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1040#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1041 |
| 1028#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1029#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1030#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1031#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1032#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) | 1042#define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1043#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1044#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) |
| 1033#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1034#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1035#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1036#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1037#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1038#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1039#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1040#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) --- 20 unchanged lines hidden (view full) --- 1061#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1062#define WREG32_PLL_P(reg, val, mask) \ 1063 do { \ 1064 uint32_t tmp_ = RREG32_PLL(reg); \ 1065 tmp_ &= (mask); \ 1066 tmp_ |= ((val) & ~(mask)); \ 1067 WREG32_PLL(reg, tmp_); \ 1068 } while (0) | 1045#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1046#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1047#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1048#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1049#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1050#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1051#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1052#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) --- 20 unchanged lines hidden (view full) --- 1073#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1074#define WREG32_PLL_P(reg, val, mask) \ 1075 do { \ 1076 uint32_t tmp_ = RREG32_PLL(reg); \ 1077 tmp_ &= (mask); \ 1078 tmp_ |= ((val) & ~(mask)); \ 1079 WREG32_PLL(reg, tmp_); \ 1080 } while (0) |
| 1069#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) | 1081#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) |
| 1070#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1071#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1072 1073#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1074#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1075 1076#define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1077 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ --- 166 unchanged lines hidden (view full) --- 1244 char *page) \ 1245{ \ 1246 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ 1247 return sprintf(page, _object "\n"); \ 1248} \ 1249 \ 1250static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) 1251 | 1082#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1083#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1084 1085#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1086#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1087 1088#define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1089 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ --- 166 unchanged lines hidden (view full) --- 1256 char *page) \ 1257{ \ 1258 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ 1259 return sprintf(page, _object "\n"); \ 1260} \ 1261 \ 1262static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) 1263 |
| 1252#endif | 1264static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1265{ 1266 return adev->gmc.tmz_enabled; 1267} |
| 1253 | 1268 |
| 1269#endif |
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