| amdgpu.h (5253163a11fba4ad0a0fafc2f7486ca02e56f295) | amdgpu.h (062f380725376efab279956b5441071684c2a7ff) |
|---|---|
| 1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation --- 420 unchanged lines hidden (view full) --- 429 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 430 431 /* 432 * Other graphics doorbells can be allocated here: from 0x8c to 0xdf 433 * Graphics voltage island aperture 1 434 * default non-graphics QWORD index is 0xe0 - 0xFF inclusive 435 */ 436 | 1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation --- 420 unchanged lines hidden (view full) --- 429 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 430 431 /* 432 * Other graphics doorbells can be allocated here: from 0x8c to 0xdf 433 * Graphics voltage island aperture 1 434 * default non-graphics QWORD index is 0xe0 - 0xFF inclusive 435 */ 436 |
| 437 /* sDMA engines reserved from 0xe0 -0xef */ 438 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xE0, 439 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xE1, 440 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xE8, 441 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xE9, 442 | |
| 443 /* For vega10 sriov, the sdma doorbell must be fixed as follow 444 * to keep the same setting with host driver, or it will 445 * happen conflicts 446 */ | 437 /* For vega10 sriov, the sdma doorbell must be fixed as follow 438 * to keep the same setting with host driver, or it will 439 * happen conflicts 440 */ |
| 447 AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE0 = 0xF0, 448 AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 449 AMDGPU_VEGA10_DOORBELL64_sDMA_ENGINE1 = 0xF2, 450 AMDGPU_VEGA10_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, | 441 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 442 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 443 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 444 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, |
| 451 452 /* Interrupt handler */ 453 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 454 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 455 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 456 457 /* VCN engine use 32 bits doorbell */ 458 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ --- 869 unchanged lines hidden --- | 445 446 /* Interrupt handler */ 447 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 448 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 449 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 450 451 /* VCN engine use 32 bits doorbell */ 452 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ --- 869 unchanged lines hidden --- |