gpio-stmpe.c (58383c78425e4ee1c077253cf297b641c861c02e) gpio-stmpe.c (b03c04a0aab1715ca8c501d41f9175a9047ef79f)
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#include <linux/module.h>

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31 struct device *dev;
32 struct mutex irq_lock;
33 u32 norequest_mask;
34 /* Caches of interrupt control registers for bus_lock */
35 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
36 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
37};
38
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#include <linux/module.h>

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31 struct device *dev;
32 struct mutex irq_lock;
33 u32 norequest_mask;
34 /* Caches of interrupt control registers for bus_lock */
35 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
36 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
37};
38
39static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
40{
41 return container_of(chip, struct stmpe_gpio, chip);
42}
43
44static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
45{
39static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
40{
46 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
41 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
47 struct stmpe *stmpe = stmpe_gpio->stmpe;
48 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
49 u8 mask = 1 << (offset % 8);
50 int ret;
51
52 ret = stmpe_reg_read(stmpe, reg);
53 if (ret < 0)
54 return ret;
55
56 return !!(ret & mask);
57}
58
59static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
60{
42 struct stmpe *stmpe = stmpe_gpio->stmpe;
43 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
44 u8 mask = 1 << (offset % 8);
45 int ret;
46
47 ret = stmpe_reg_read(stmpe, reg);
48 if (ret < 0)
49 return ret;
50
51 return !!(ret & mask);
52}
53
54static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
55{
61 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
56 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
62 struct stmpe *stmpe = stmpe_gpio->stmpe;
63 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
64 u8 reg = stmpe->regs[which] - (offset / 8);
65 u8 mask = 1 << (offset % 8);
66
67 /*
68 * Some variants have single register for gpio set/clear functionality.
69 * For them we need to write 0 to clear and 1 to set.
70 */
71 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
72 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
73 else
74 stmpe_reg_write(stmpe, reg, mask);
75}
76
77static int stmpe_gpio_direction_output(struct gpio_chip *chip,
78 unsigned offset, int val)
79{
57 struct stmpe *stmpe = stmpe_gpio->stmpe;
58 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
59 u8 reg = stmpe->regs[which] - (offset / 8);
60 u8 mask = 1 << (offset % 8);
61
62 /*
63 * Some variants have single register for gpio set/clear functionality.
64 * For them we need to write 0 to clear and 1 to set.
65 */
66 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
67 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
68 else
69 stmpe_reg_write(stmpe, reg, mask);
70}
71
72static int stmpe_gpio_direction_output(struct gpio_chip *chip,
73 unsigned offset, int val)
74{
80 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
75 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
81 struct stmpe *stmpe = stmpe_gpio->stmpe;
82 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
83 u8 mask = 1 << (offset % 8);
84
85 stmpe_gpio_set(chip, offset, val);
86
87 return stmpe_set_bits(stmpe, reg, mask, mask);
88}
89
90static int stmpe_gpio_direction_input(struct gpio_chip *chip,
91 unsigned offset)
92{
76 struct stmpe *stmpe = stmpe_gpio->stmpe;
77 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
78 u8 mask = 1 << (offset % 8);
79
80 stmpe_gpio_set(chip, offset, val);
81
82 return stmpe_set_bits(stmpe, reg, mask, mask);
83}
84
85static int stmpe_gpio_direction_input(struct gpio_chip *chip,
86 unsigned offset)
87{
93 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
88 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
94 struct stmpe *stmpe = stmpe_gpio->stmpe;
95 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
96 u8 mask = 1 << (offset % 8);
97
98 return stmpe_set_bits(stmpe, reg, mask, 0);
99}
100
101static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
102{
89 struct stmpe *stmpe = stmpe_gpio->stmpe;
90 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
91 u8 mask = 1 << (offset % 8);
92
93 return stmpe_set_bits(stmpe, reg, mask, 0);
94}
95
96static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
97{
103 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
98 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
104 struct stmpe *stmpe = stmpe_gpio->stmpe;
105
106 if (stmpe_gpio->norequest_mask & (1 << offset))
107 return -EINVAL;
108
109 return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
110}
111

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118 .set = stmpe_gpio_set,
119 .request = stmpe_gpio_request,
120 .can_sleep = true,
121};
122
123static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
124{
125 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
99 struct stmpe *stmpe = stmpe_gpio->stmpe;
100
101 if (stmpe_gpio->norequest_mask & (1 << offset))
102 return -EINVAL;
103
104 return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
105}
106

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113 .set = stmpe_gpio_set,
114 .request = stmpe_gpio_request,
115 .can_sleep = true,
116};
117
118static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
119{
120 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
126 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
121 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
127 int offset = d->hwirq;
128 int regoffset = offset / 8;
129 int mask = 1 << (offset % 8);
130
131 if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
132 return -EINVAL;
133
134 /* STMPE801 doesn't have RE and FE registers */

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146 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
147
148 return 0;
149}
150
151static void stmpe_gpio_irq_lock(struct irq_data *d)
152{
153 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
122 int offset = d->hwirq;
123 int regoffset = offset / 8;
124 int mask = 1 << (offset % 8);
125
126 if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
127 return -EINVAL;
128
129 /* STMPE801 doesn't have RE and FE registers */

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141 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
142
143 return 0;
144}
145
146static void stmpe_gpio_irq_lock(struct irq_data *d)
147{
148 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
154 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
149 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
155
156 mutex_lock(&stmpe_gpio->irq_lock);
157}
158
159static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
160{
161 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
150
151 mutex_lock(&stmpe_gpio->irq_lock);
152}
153
154static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
155{
156 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
162 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
157 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
163 struct stmpe *stmpe = stmpe_gpio->stmpe;
164 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
165 static const u8 regmap[] = {
166 [REG_RE] = STMPE_IDX_GPRER_LSB,
167 [REG_FE] = STMPE_IDX_GPFER_LSB,
168 [REG_IE] = STMPE_IDX_IEGPIOR_LSB,
169 };
170 int i, j;

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188 }
189
190 mutex_unlock(&stmpe_gpio->irq_lock);
191}
192
193static void stmpe_gpio_irq_mask(struct irq_data *d)
194{
195 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
158 struct stmpe *stmpe = stmpe_gpio->stmpe;
159 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
160 static const u8 regmap[] = {
161 [REG_RE] = STMPE_IDX_GPRER_LSB,
162 [REG_FE] = STMPE_IDX_GPFER_LSB,
163 [REG_IE] = STMPE_IDX_IEGPIOR_LSB,
164 };
165 int i, j;

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183 }
184
185 mutex_unlock(&stmpe_gpio->irq_lock);
186}
187
188static void stmpe_gpio_irq_mask(struct irq_data *d)
189{
190 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
196 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
191 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
197 int offset = d->hwirq;
198 int regoffset = offset / 8;
199 int mask = 1 << (offset % 8);
200
201 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
202}
203
204static void stmpe_gpio_irq_unmask(struct irq_data *d)
205{
206 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
192 int offset = d->hwirq;
193 int regoffset = offset / 8;
194 int mask = 1 << (offset % 8);
195
196 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
197}
198
199static void stmpe_gpio_irq_unmask(struct irq_data *d)
200{
201 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
207 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
202 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
208 int offset = d->hwirq;
209 int regoffset = offset / 8;
210 int mask = 1 << (offset % 8);
211
212 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
213}
214
215static void stmpe_dbg_show_one(struct seq_file *s,
216 struct gpio_chip *gc,
217 unsigned offset, unsigned gpio)
218{
203 int offset = d->hwirq;
204 int regoffset = offset / 8;
205 int mask = 1 << (offset % 8);
206
207 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
208}
209
210static void stmpe_dbg_show_one(struct seq_file *s,
211 struct gpio_chip *gc,
212 unsigned offset, unsigned gpio)
213{
219 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
214 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
220 struct stmpe *stmpe = stmpe_gpio->stmpe;
221 const char *label = gpiochip_is_requested(gc, offset);
222 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
223 bool val = !!stmpe_gpio_get(gc, offset);
224 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
225 u8 mask = 1 << (offset % 8);
226 int ret;
227 u8 dir;

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370 dev_info(&pdev->dev,
371 "device configured in no-irq mode: "
372 "irqs are not available\n");
373
374 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
375 if (ret)
376 goto out_free;
377
215 struct stmpe *stmpe = stmpe_gpio->stmpe;
216 const char *label = gpiochip_is_requested(gc, offset);
217 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
218 bool val = !!stmpe_gpio_get(gc, offset);
219 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
220 u8 mask = 1 << (offset % 8);
221 int ret;
222 u8 dir;

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365 dev_info(&pdev->dev,
366 "device configured in no-irq mode: "
367 "irqs are not available\n");
368
369 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
370 if (ret)
371 goto out_free;
372
378 ret = gpiochip_add(&stmpe_gpio->chip);
373 ret = gpiochip_add_data(&stmpe_gpio->chip, stmpe_gpio);
379 if (ret) {
380 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
381 goto out_disable;
382 }
383
384 if (irq > 0) {
385 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
386 stmpe_gpio_irq, IRQF_ONESHOT,

--- 68 unchanged lines hidden --- 		374 if (ret) {
375 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
376 goto out_disable;
377 }
378
379 if (irq > 0) {
380 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
381 stmpe_gpio_irq, IRQF_ONESHOT,

--- 68 unchanged lines hidden ---