| shdmac.c (4ba24fef3eb3b142197135223b90ced2f319cd53) | shdmac.c (82bf90c62834842249c4f94535079f5cbec9014c) |
|---|---|
| 1/* 2 * Renesas SuperH DMA Engine support 3 * 4 * base is drivers/dma/flsdma.c 5 * 6 * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de> 7 * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> 8 * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved. --- 574 unchanged lines hidden (view full) --- 583} 584 585static void sh_dmae_shutdown(struct platform_device *pdev) 586{ 587 struct sh_dmae_device *shdev = platform_get_drvdata(pdev); 588 sh_dmae_ctl_stop(shdev); 589} 590 | 1/* 2 * Renesas SuperH DMA Engine support 3 * 4 * base is drivers/dma/flsdma.c 5 * 6 * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de> 7 * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> 8 * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved. --- 574 unchanged lines hidden (view full) --- 583} 584 585static void sh_dmae_shutdown(struct platform_device *pdev) 586{ 587 struct sh_dmae_device *shdev = platform_get_drvdata(pdev); 588 sh_dmae_ctl_stop(shdev); 589} 590 |
| 591#ifdef CONFIG_PM |
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| 591static int sh_dmae_runtime_suspend(struct device *dev) 592{ 593 return 0; 594} 595 596static int sh_dmae_runtime_resume(struct device *dev) 597{ 598 struct sh_dmae_device *shdev = dev_get_drvdata(dev); 599 600 return sh_dmae_rst(shdev); 601} 602 | 592static int sh_dmae_runtime_suspend(struct device *dev) 593{ 594 return 0; 595} 596 597static int sh_dmae_runtime_resume(struct device *dev) 598{ 599 struct sh_dmae_device *shdev = dev_get_drvdata(dev); 600 601 return sh_dmae_rst(shdev); 602} 603 |
| 603#ifdef CONFIG_PM | |
| 604static int sh_dmae_suspend(struct device *dev) 605{ 606 return 0; 607} 608 609static int sh_dmae_resume(struct device *dev) 610{ 611 struct sh_dmae_device *shdev = dev_get_drvdata(dev); --- 23 unchanged lines hidden (view full) --- 635#else 636#define sh_dmae_suspend NULL 637#define sh_dmae_resume NULL 638#endif 639 640static const struct dev_pm_ops sh_dmae_pm = { 641 .suspend = sh_dmae_suspend, 642 .resume = sh_dmae_resume, | 604static int sh_dmae_suspend(struct device *dev) 605{ 606 return 0; 607} 608 609static int sh_dmae_resume(struct device *dev) 610{ 611 struct sh_dmae_device *shdev = dev_get_drvdata(dev); --- 23 unchanged lines hidden (view full) --- 635#else 636#define sh_dmae_suspend NULL 637#define sh_dmae_resume NULL 638#endif 639 640static const struct dev_pm_ops sh_dmae_pm = { 641 .suspend = sh_dmae_suspend, 642 .resume = sh_dmae_resume, |
| 643 .runtime_suspend = sh_dmae_runtime_suspend, 644 .runtime_resume = sh_dmae_runtime_resume, | 643 SET_RUNTIME_PM_OPS(sh_dmae_runtime_suspend, sh_dmae_runtime_resume, 644 NULL) |
| 645}; 646 647static dma_addr_t sh_dmae_slave_addr(struct shdma_chan *schan) 648{ 649 struct sh_dmae_chan *sh_chan = container_of(schan, 650 struct sh_dmae_chan, shdma_chan); 651 652 /* --- 26 unchanged lines hidden (view full) --- 679static const struct of_device_id sh_dmae_of_match[] = { 680 {.compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid,}, 681 {} 682}; 683MODULE_DEVICE_TABLE(of, sh_dmae_of_match); 684 685static int sh_dmae_probe(struct platform_device *pdev) 686{ | 645}; 646 647static dma_addr_t sh_dmae_slave_addr(struct shdma_chan *schan) 648{ 649 struct sh_dmae_chan *sh_chan = container_of(schan, 650 struct sh_dmae_chan, shdma_chan); 651 652 /* --- 26 unchanged lines hidden (view full) --- 679static const struct of_device_id sh_dmae_of_match[] = { 680 {.compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid,}, 681 {} 682}; 683MODULE_DEVICE_TABLE(of, sh_dmae_of_match); 684 685static int sh_dmae_probe(struct platform_device *pdev) 686{ |
| 687 const enum dma_slave_buswidth widths = 688 DMA_SLAVE_BUSWIDTH_1_BYTE | DMA_SLAVE_BUSWIDTH_2_BYTES | 689 DMA_SLAVE_BUSWIDTH_4_BYTES | DMA_SLAVE_BUSWIDTH_8_BYTES | 690 DMA_SLAVE_BUSWIDTH_16_BYTES | DMA_SLAVE_BUSWIDTH_32_BYTES; |
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| 687 const struct sh_dmae_pdata *pdata; 688 unsigned long chan_flag[SH_DMAE_MAX_CHANNELS] = {}; 689 int chan_irq[SH_DMAE_MAX_CHANNELS]; 690#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARM) 691 unsigned long irqflags = 0; 692 int errirq; 693#endif 694 int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0; --- 46 unchanged lines hidden (view full) --- 741 if (IS_ERR(shdev->chan_reg)) 742 return PTR_ERR(shdev->chan_reg); 743 if (dmars) { 744 shdev->dmars = devm_ioremap_resource(&pdev->dev, dmars); 745 if (IS_ERR(shdev->dmars)) 746 return PTR_ERR(shdev->dmars); 747 } 748 | 691 const struct sh_dmae_pdata *pdata; 692 unsigned long chan_flag[SH_DMAE_MAX_CHANNELS] = {}; 693 int chan_irq[SH_DMAE_MAX_CHANNELS]; 694#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARM) 695 unsigned long irqflags = 0; 696 int errirq; 697#endif 698 int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0; --- 46 unchanged lines hidden (view full) --- 745 if (IS_ERR(shdev->chan_reg)) 746 return PTR_ERR(shdev->chan_reg); 747 if (dmars) { 748 shdev->dmars = devm_ioremap_resource(&pdev->dev, dmars); 749 if (IS_ERR(shdev->dmars)) 750 return PTR_ERR(shdev->dmars); 751 } 752 |
| 753 dma_dev->src_addr_widths = widths; 754 dma_dev->dst_addr_widths = widths; 755 dma_dev->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); 756 dma_dev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; 757 |
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| 749 if (!pdata->slave_only) 750 dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask); 751 if (pdata->slave && pdata->slave_num) 752 dma_cap_set(DMA_SLAVE, dma_dev->cap_mask); 753 754 /* Default transfer size of 32 bytes requires 32-byte alignment */ 755 dma_dev->copy_align = LOG2_DEFAULT_XFER_SIZE; 756 --- 200 unchanged lines hidden --- | 758 if (!pdata->slave_only) 759 dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask); 760 if (pdata->slave && pdata->slave_num) 761 dma_cap_set(DMA_SLAVE, dma_dev->cap_mask); 762 763 /* Default transfer size of 32 bytes requires 32-byte alignment */ 764 dma_dev->copy_align = LOG2_DEFAULT_XFER_SIZE; 765 --- 200 unchanged lines hidden --- |