mmp_pdma.c (e3c55d406bd8df1a878546002c93db90c42be10c) mmp_pdma.c (174b537ac2b8fe1bac31039185b80f873716c5a1)
1/*
2 * Copyright 2012 Marvell International Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8#include <linux/err.h>

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793 /* submit pending list; callback for each desc; free desc */
794 spin_lock_irqsave(&chan->desc_lock, flags);
795
796 list_for_each_entry_safe(desc, _desc, &chan->chain_running, node) {
797 /*
798 * move the descriptors to a temporary list so we can drop
799 * the lock during the entire cleanup operation
800 */
1/*
2 * Copyright 2012 Marvell International Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8#include <linux/err.h>

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793 /* submit pending list; callback for each desc; free desc */
794 spin_lock_irqsave(&chan->desc_lock, flags);
795
796 list_for_each_entry_safe(desc, _desc, &chan->chain_running, node) {
797 /*
798 * move the descriptors to a temporary list so we can drop
799 * the lock during the entire cleanup operation
800 */
801 list_del(&desc->node);
802 list_add(&desc->node, &chain_cleanup);
801 list_move(&desc->node, &chain_cleanup);
803
804 /*
805 * Look for the first list entry which has the ENDIRQEN flag
806 * set. That is the descriptor we got an interrupt for, so
807 * complete that transaction and its cookie.
808 */
809 if (desc->desc.dcmd & DCMD_ENDIRQEN) {
810 dma_cookie_t cookie = desc->async_tx.cookie;

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858 if (chan == NULL)
859 return -ENOMEM;
860
861 phy->idx = idx;
862 phy->base = pdev->base;
863
864 if (irq) {
865 ret = devm_request_irq(pdev->dev, irq,
802
803 /*
804 * Look for the first list entry which has the ENDIRQEN flag
805 * set. That is the descriptor we got an interrupt for, so
806 * complete that transaction and its cookie.
807 */
808 if (desc->desc.dcmd & DCMD_ENDIRQEN) {
809 dma_cookie_t cookie = desc->async_tx.cookie;

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857 if (chan == NULL)
858 return -ENOMEM;
859
860 phy->idx = idx;
861 phy->base = pdev->base;
862
863 if (irq) {
864 ret = devm_request_irq(pdev->dev, irq,
866 mmp_pdma_chan_handler, IRQF_DISABLED, "pdma", phy);
865 mmp_pdma_chan_handler, 0, "pdma", phy);
867 if (ret) {
868 dev_err(pdev->dev, "channel request irq fail!\n");
869 return ret;
870 }
871 }
872
873 spin_lock_init(&chan->desc_lock);
874 chan->dev = pdev->dev;

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965 return -ENOMEM;
966
967 INIT_LIST_HEAD(&pdev->device.channels);
968
969 if (irq_num != dma_channels) {
970 /* all chan share one irq, demux inside */
971 irq = platform_get_irq(op, 0);
972 ret = devm_request_irq(pdev->dev, irq,
866 if (ret) {
867 dev_err(pdev->dev, "channel request irq fail!\n");
868 return ret;
869 }
870 }
871
872 spin_lock_init(&chan->desc_lock);
873 chan->dev = pdev->dev;

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964 return -ENOMEM;
965
966 INIT_LIST_HEAD(&pdev->device.channels);
967
968 if (irq_num != dma_channels) {
969 /* all chan share one irq, demux inside */
970 irq = platform_get_irq(op, 0);
971 ret = devm_request_irq(pdev->dev, irq,
973 mmp_pdma_int_handler, IRQF_DISABLED, "pdma", pdev);
972 mmp_pdma_int_handler, 0, "pdma", pdev);
974 if (ret)
975 return ret;
976 }
977
978 for (i = 0; i < dma_channels; i++) {
979 irq = (irq_num != dma_channels) ? 0 : platform_get_irq(op, i);
980 ret = mmp_pdma_chan_init(pdev, i, irq);
981 if (ret)

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974 return ret;
975 }
976
977 for (i = 0; i < dma_channels; i++) {
978 irq = (irq_num != dma_channels) ? 0 : platform_get_irq(op, i);
979 ret = mmp_pdma_chan_init(pdev, i, irq);
980 if (ret)

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