submit.c (0ea8a56de21be24cb79abb03dee79aabcd60a316) submit.c (8e50d392652f20616a136165dff516b86baf5e49)
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3#include <linux/init.h>
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/pci.h>
7#include <uapi/linux/idxd.h>
8#include "idxd.h"
9#include "registers.h"
10
11static struct idxd_desc *__get_desc(struct idxd_wq *wq, int idx, int cpu)
12{
13 struct idxd_desc *desc;
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3#include <linux/init.h>
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/pci.h>
7#include <uapi/linux/idxd.h>
8#include "idxd.h"
9#include "registers.h"
10
11static struct idxd_desc *__get_desc(struct idxd_wq *wq, int idx, int cpu)
12{
13 struct idxd_desc *desc;
14 struct idxd_device *idxd = wq->idxd;
14
15 desc = wq->descs[idx];
16 memset(desc->hw, 0, sizeof(struct dsa_hw_desc));
17 memset(desc->completion, 0, sizeof(struct dsa_completion_record));
18 desc->cpu = cpu;
15
16 desc = wq->descs[idx];
17 memset(desc->hw, 0, sizeof(struct dsa_hw_desc));
18 memset(desc->completion, 0, sizeof(struct dsa_completion_record));
19 desc->cpu = cpu;
20
21 if (device_pasid_enabled(idxd))
22 desc->hw->pasid = idxd->pasid;
23
24 /*
25 * Descriptor completion vectors are 1-8 for MSIX. We will round
26 * robin through the 8 vectors.
27 */
28 wq->vec_ptr = (wq->vec_ptr % idxd->num_wq_irqs) + 1;
29 desc->hw->int_handle = wq->vec_ptr;
19 return desc;
20}
21
22struct idxd_desc *idxd_alloc_desc(struct idxd_wq *wq, enum idxd_op_type optype)
23{
24 int cpu, idx;
25 struct idxd_device *idxd = wq->idxd;
26 DEFINE_SBQ_WAIT(wait);

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65 sbitmap_queue_clear(&wq->sbq, desc->id, cpu);
66}
67
68int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc)
69{
70 struct idxd_device *idxd = wq->idxd;
71 int vec = desc->hw->int_handle;
72 void __iomem *portal;
30 return desc;
31}
32
33struct idxd_desc *idxd_alloc_desc(struct idxd_wq *wq, enum idxd_op_type optype)
34{
35 int cpu, idx;
36 struct idxd_device *idxd = wq->idxd;
37 DEFINE_SBQ_WAIT(wait);

--- 38 unchanged lines hidden (view full) ---

76 sbitmap_queue_clear(&wq->sbq, desc->id, cpu);
77}
78
79int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc)
80{
81 struct idxd_device *idxd = wq->idxd;
82 int vec = desc->hw->int_handle;
83 void __iomem *portal;
84 int rc;
73
74 if (idxd->state != IDXD_DEV_ENABLED)
75 return -EIO;
76
85
86 if (idxd->state != IDXD_DEV_ENABLED)
87 return -EIO;
88
77 portal = wq->dportal + idxd_get_wq_portal_offset(IDXD_PORTAL_UNLIMITED);
89 portal = wq->portal + idxd_get_wq_portal_offset(IDXD_PORTAL_LIMITED);
90
78 /*
91 /*
79 * The wmb() flushes writes to coherent DMA data before possibly
80 * triggering a DMA read. The wmb() is necessary even on UP because
81 * the recipient is a device.
92 * The wmb() flushes writes to coherent DMA data before
93 * possibly triggering a DMA read. The wmb() is necessary
94 * even on UP because the recipient is a device.
82 */
83 wmb();
95 */
96 wmb();
84 iosubmit_cmds512(portal, desc->hw, 1);
97 if (wq_dedicated(wq)) {
98 iosubmit_cmds512(portal, desc->hw, 1);
99 } else {
100 /*
101 * It's not likely that we would receive queue full rejection
102 * since the descriptor allocation gates at wq size. If we
103 * receive a -EAGAIN, that means something went wrong such as the
104 * device is not accepting descriptor at all.
105 */
106 rc = enqcmds(portal, desc->hw);
107 if (rc < 0)
108 return rc;
109 }
85
86 /*
87 * Pending the descriptor to the lockless list for the irq_entry
88 * that we designated the descriptor to.
89 */
90 if (desc->hw->flags & IDXD_OP_FLAG_RCI)
91 llist_add(&desc->llnode,
92 &idxd->irq_entries[vec].pending_llist);
93
94 return 0;
95}
110
111 /*
112 * Pending the descriptor to the lockless list for the irq_entry
113 * that we designated the descriptor to.
114 */
115 if (desc->hw->flags & IDXD_OP_FLAG_RCI)
116 llist_add(&desc->llnode,
117 &idxd->irq_entries[vec].pending_llist);
118
119 return 0;
120}