| device.c (d98793b5d4256faae76177178456214f55bc7083) | device.c (8e50d392652f20616a136165dff516b86baf5e49) |
|---|---|
| 1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3#include <linux/init.h> 4#include <linux/kernel.h> 5#include <linux/module.h> 6#include <linux/pci.h> 7#include <linux/io-64-nonatomic-lo-hi.h> 8#include <linux/dmaengine.h> --- 259 unchanged lines hidden (view full) --- 268 struct idxd_device *idxd = wq->idxd; 269 struct pci_dev *pdev = idxd->pdev; 270 struct device *dev = &pdev->dev; 271 resource_size_t start; 272 273 start = pci_resource_start(pdev, IDXD_WQ_BAR); 274 start = start + wq->id * IDXD_PORTAL_SIZE; 275 | 1// SPDX-License-Identifier: GPL-2.0 2/* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3#include <linux/init.h> 4#include <linux/kernel.h> 5#include <linux/module.h> 6#include <linux/pci.h> 7#include <linux/io-64-nonatomic-lo-hi.h> 8#include <linux/dmaengine.h> --- 259 unchanged lines hidden (view full) --- 268 struct idxd_device *idxd = wq->idxd; 269 struct pci_dev *pdev = idxd->pdev; 270 struct device *dev = &pdev->dev; 271 resource_size_t start; 272 273 start = pci_resource_start(pdev, IDXD_WQ_BAR); 274 start = start + wq->id * IDXD_PORTAL_SIZE; 275 |
| 276 wq->dportal = devm_ioremap(dev, start, IDXD_PORTAL_SIZE); 277 if (!wq->dportal) | 276 wq->portal = devm_ioremap(dev, start, IDXD_PORTAL_SIZE); 277 if (!wq->portal) |
| 278 return -ENOMEM; | 278 return -ENOMEM; |
| 279 dev_dbg(dev, "wq %d portal mapped at %p\n", wq->id, wq->dportal); | |
| 280 281 return 0; 282} 283 284void idxd_wq_unmap_portal(struct idxd_wq *wq) 285{ 286 struct device *dev = &wq->idxd->pdev->dev; 287 | 279 280 return 0; 281} 282 283void idxd_wq_unmap_portal(struct idxd_wq *wq) 284{ 285 struct device *dev = &wq->idxd->pdev->dev; 286 |
| 288 devm_iounmap(dev, wq->dportal); | 287 devm_iounmap(dev, wq->portal); |
| 289} 290 | 288} 289 |
| 290int idxd_wq_set_pasid(struct idxd_wq *wq, int pasid) 291{ 292 struct idxd_device *idxd = wq->idxd; 293 int rc; 294 union wqcfg wqcfg; 295 unsigned int offset; 296 unsigned long flags; 297 298 rc = idxd_wq_disable(wq); 299 if (rc < 0) 300 return rc; 301 302 offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX); 303 spin_lock_irqsave(&idxd->dev_lock, flags); 304 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset); 305 wqcfg.pasid_en = 1; 306 wqcfg.pasid = pasid; 307 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset); 308 spin_unlock_irqrestore(&idxd->dev_lock, flags); 309 310 rc = idxd_wq_enable(wq); 311 if (rc < 0) 312 return rc; 313 314 return 0; 315} 316 317int idxd_wq_disable_pasid(struct idxd_wq *wq) 318{ 319 struct idxd_device *idxd = wq->idxd; 320 int rc; 321 union wqcfg wqcfg; 322 unsigned int offset; 323 unsigned long flags; 324 325 rc = idxd_wq_disable(wq); 326 if (rc < 0) 327 return rc; 328 329 offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX); 330 spin_lock_irqsave(&idxd->dev_lock, flags); 331 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset); 332 wqcfg.pasid_en = 0; 333 wqcfg.pasid = 0; 334 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset); 335 spin_unlock_irqrestore(&idxd->dev_lock, flags); 336 337 rc = idxd_wq_enable(wq); 338 if (rc < 0) 339 return rc; 340 341 return 0; 342} 343 |
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| 291void idxd_wq_disable_cleanup(struct idxd_wq *wq) 292{ 293 struct idxd_device *idxd = wq->idxd; 294 struct device *dev = &idxd->pdev->dev; 295 int i, wq_offset; 296 297 lockdep_assert_held(&idxd->dev_lock); 298 memset(wq->wqcfg, 0, idxd->wqcfg_size); --- 164 unchanged lines hidden (view full) --- 463 464 idxd_cmd_exec(idxd, IDXD_CMD_RESET_DEVICE, 0, NULL); 465 spin_lock_irqsave(&idxd->dev_lock, flags); 466 idxd_device_wqs_clear_state(idxd); 467 idxd->state = IDXD_DEV_CONF_READY; 468 spin_unlock_irqrestore(&idxd->dev_lock, flags); 469} 470 | 344void idxd_wq_disable_cleanup(struct idxd_wq *wq) 345{ 346 struct idxd_device *idxd = wq->idxd; 347 struct device *dev = &idxd->pdev->dev; 348 int i, wq_offset; 349 350 lockdep_assert_held(&idxd->dev_lock); 351 memset(wq->wqcfg, 0, idxd->wqcfg_size); --- 164 unchanged lines hidden (view full) --- 516 517 idxd_cmd_exec(idxd, IDXD_CMD_RESET_DEVICE, 0, NULL); 518 spin_lock_irqsave(&idxd->dev_lock, flags); 519 idxd_device_wqs_clear_state(idxd); 520 idxd->state = IDXD_DEV_CONF_READY; 521 spin_unlock_irqrestore(&idxd->dev_lock, flags); 522} 523 |
| 524void idxd_device_drain_pasid(struct idxd_device *idxd, int pasid) 525{ 526 struct device *dev = &idxd->pdev->dev; 527 u32 operand; 528 529 operand = pasid; 530 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_DRAIN_PASID, operand); 531 idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_PASID, operand, NULL); 532 dev_dbg(dev, "pasid %d drained\n", pasid); 533} 534 |
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| 471/* Device configuration bits */ 472static void idxd_group_config_write(struct idxd_group *group) 473{ 474 struct idxd_device *idxd = group->idxd; 475 struct device *dev = &idxd->pdev->dev; 476 int i; 477 u32 grpcfg_offset; 478 --- 70 unchanged lines hidden (view full) --- 549 return -EINVAL; 550 } 551 552 /* bytes 4-7 */ 553 wq->wqcfg->wq_thresh = wq->threshold; 554 555 /* byte 8-11 */ 556 wq->wqcfg->priv = !!(wq->type == IDXD_WQT_KERNEL); | 535/* Device configuration bits */ 536static void idxd_group_config_write(struct idxd_group *group) 537{ 538 struct idxd_device *idxd = group->idxd; 539 struct device *dev = &idxd->pdev->dev; 540 int i; 541 u32 grpcfg_offset; 542 --- 70 unchanged lines hidden (view full) --- 613 return -EINVAL; 614 } 615 616 /* bytes 4-7 */ 617 wq->wqcfg->wq_thresh = wq->threshold; 618 619 /* byte 8-11 */ 620 wq->wqcfg->priv = !!(wq->type == IDXD_WQT_KERNEL); |
| 557 wq->wqcfg->mode = 1; | 621 if (wq_dedicated(wq)) 622 wq->wqcfg->mode = 1; 623 624 if (device_pasid_enabled(idxd)) { 625 wq->wqcfg->pasid_en = 1; 626 if (wq->type == IDXD_WQT_KERNEL && wq_dedicated(wq)) 627 wq->wqcfg->pasid = idxd->pasid; 628 } 629 |
| 558 wq->wqcfg->priority = wq->priority; 559 | 630 wq->wqcfg->priority = wq->priority; 631 |
| 632 if (idxd->hw.gen_cap.block_on_fault && 633 test_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags)) 634 wq->wqcfg->bof = 1; 635 |
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| 560 /* bytes 12-15 */ 561 wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes); 562 wq->wqcfg->max_batch_shift = ilog2(wq->max_batch_size); 563 564 dev_dbg(dev, "WQ %d CFGs\n", wq->id); 565 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 566 wq_offset = WQCFG_OFFSET(idxd, wq->id, i); 567 iowrite32(wq->wqcfg->bits[i], idxd->reg_base + wq_offset); --- 91 unchanged lines hidden (view full) --- 659 wq = &idxd->wqs[i]; 660 group = wq->group; 661 662 if (!wq->group) 663 continue; 664 if (!wq->size) 665 continue; 666 | 636 /* bytes 12-15 */ 637 wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes); 638 wq->wqcfg->max_batch_shift = ilog2(wq->max_batch_size); 639 640 dev_dbg(dev, "WQ %d CFGs\n", wq->id); 641 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 642 wq_offset = WQCFG_OFFSET(idxd, wq->id, i); 643 iowrite32(wq->wqcfg->bits[i], idxd->reg_base + wq_offset); --- 91 unchanged lines hidden (view full) --- 735 wq = &idxd->wqs[i]; 736 group = wq->group; 737 738 if (!wq->group) 739 continue; 740 if (!wq->size) 741 continue; 742 |
| 667 if (!wq_dedicated(wq)) { 668 dev_warn(dev, "No shared workqueue support.\n"); | 743 if (wq_shared(wq) && !device_swq_supported(idxd)) { 744 dev_warn(dev, "No shared wq support but configured.\n"); |
| 669 return -EINVAL; 670 } 671 672 group->grpcfg.wqs[wq->id / 64] |= BIT(wq->id % 64); 673 configured++; 674 } 675 676 if (configured == 0) --- 30 unchanged lines hidden --- | 745 return -EINVAL; 746 } 747 748 group->grpcfg.wqs[wq->id / 64] |= BIT(wq->id % 64); 749 configured++; 750 } 751 752 if (configured == 0) --- 30 unchanged lines hidden --- |