sp-pci.c (b3c9a04135bdbd3aabd5e9534bad0fe6df505f8a) sp-pci.c (22351239247b30978d06eb2ab5c258e6b344949f)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * AMD Secure Processor device driver
4 *
5 * Copyright (C) 2013,2019 Advanced Micro Devices, Inc.
6 *
7 * Author: Tom Lendacky <thomas.lendacky@amd.com>
8 * Author: Gary R Hook <gary.hook@amd.com>

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356static const struct tee_vdata teev1 = {
357 .cmdresp_reg = 0x10544, /* C2PMSG_17 */
358 .cmdbuff_addr_lo_reg = 0x10548, /* C2PMSG_18 */
359 .cmdbuff_addr_hi_reg = 0x1054c, /* C2PMSG_19 */
360 .ring_wptr_reg = 0x10550, /* C2PMSG_20 */
361 .ring_rptr_reg = 0x10554, /* C2PMSG_21 */
362};
363
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * AMD Secure Processor device driver
4 *
5 * Copyright (C) 2013,2019 Advanced Micro Devices, Inc.
6 *
7 * Author: Tom Lendacky <thomas.lendacky@amd.com>
8 * Author: Gary R Hook <gary.hook@amd.com>

--- 347 unchanged lines hidden (view full) ---

356static const struct tee_vdata teev1 = {
357 .cmdresp_reg = 0x10544, /* C2PMSG_17 */
358 .cmdbuff_addr_lo_reg = 0x10548, /* C2PMSG_18 */
359 .cmdbuff_addr_hi_reg = 0x1054c, /* C2PMSG_19 */
360 .ring_wptr_reg = 0x10550, /* C2PMSG_20 */
361 .ring_rptr_reg = 0x10554, /* C2PMSG_21 */
362};
363
364static const struct platform_access_vdata pa_v1 = {
365 .cmdresp_reg = 0x10570, /* C2PMSG_28 */
366 .cmdbuff_addr_lo_reg = 0x10574, /* C2PMSG_29 */
367 .cmdbuff_addr_hi_reg = 0x10578, /* C2PMSG_30 */
368};
369
364static const struct psp_vdata pspv1 = {
365 .sev = &sevv1,
366 .feature_reg = 0x105fc, /* C2PMSG_63 */
367 .inten_reg = 0x10610, /* P2CMSG_INTEN */
368 .intsts_reg = 0x10614, /* P2CMSG_INTSTS */
369};
370
371static const struct psp_vdata pspv2 = {
372 .sev = &sevv2,
373 .feature_reg = 0x109fc, /* C2PMSG_63 */
374 .inten_reg = 0x10690, /* P2CMSG_INTEN */
375 .intsts_reg = 0x10694, /* P2CMSG_INTSTS */
376};
377
378static const struct psp_vdata pspv3 = {
379 .tee = &teev1,
370static const struct psp_vdata pspv1 = {
371 .sev = &sevv1,
372 .feature_reg = 0x105fc, /* C2PMSG_63 */
373 .inten_reg = 0x10610, /* P2CMSG_INTEN */
374 .intsts_reg = 0x10614, /* P2CMSG_INTSTS */
375};
376
377static const struct psp_vdata pspv2 = {
378 .sev = &sevv2,
379 .feature_reg = 0x109fc, /* C2PMSG_63 */
380 .inten_reg = 0x10690, /* P2CMSG_INTEN */
381 .intsts_reg = 0x10694, /* P2CMSG_INTSTS */
382};
383
384static const struct psp_vdata pspv3 = {
385 .tee = &teev1,
386 .platform_access = &pa_v1,
380 .feature_reg = 0x109fc, /* C2PMSG_63 */
381 .inten_reg = 0x10690, /* P2CMSG_INTEN */
382 .intsts_reg = 0x10694, /* P2CMSG_INTSTS */
383};
384
385static const struct psp_vdata pspv4 = {
386 .sev = &sevv2,
387 .tee = &teev1,

--- 95 unchanged lines hidden --- 		387 .feature_reg = 0x109fc, /* C2PMSG_63 */
388 .inten_reg = 0x10690, /* P2CMSG_INTEN */
389 .intsts_reg = 0x10694, /* P2CMSG_INTSTS */
390};
391
392static const struct psp_vdata pspv4 = {
393 .sev = &sevv2,
394 .tee = &teev1,

--- 95 unchanged lines hidden ---