clk-zynqmp.h (c39f2d9db0fd81ea20bb5cce9b3f082ca63753e2) clk-zynqmp.h (e605fa9c4a0c1218e5604b42bef59de0a3a4f813)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2016-2018 Xilinx
4 */
5
6#ifndef __LINUX_CLK_ZYNQMP_H_
7#define __LINUX_CLK_ZYNQMP_H_
8

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25 * @type: Type of topology
26 * @flag: Topology flags
27 * @type_flag: Topology type specific flag
28 */
29struct clock_topology {
30 u32 type;
31 u32 flag;
32 u32 type_flag;
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2016-2018 Xilinx
4 */
5
6#ifndef __LINUX_CLK_ZYNQMP_H_
7#define __LINUX_CLK_ZYNQMP_H_
8

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25 * @type: Type of topology
26 * @flag: Topology flags
27 * @type_flag: Topology type specific flag
28 */
29struct clock_topology {
30 u32 type;
31 u32 flag;
32 u32 type_flag;
33 u8 custom_type_flag;
33};
34
35struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
36 const char * const *parents,
37 u8 num_parents,
38 const struct clock_topology *nodes);
39
40struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,

--- 22 unchanged lines hidden --- 		34};
35
36struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
37 const char * const *parents,
38 u8 num_parents,
39 const struct clock_topology *nodes);
40
41struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,

--- 22 unchanged lines hidden ---