clk-zynqmp.h (1b09c308e64969f545f4b9474b786ad90dddf9a2) clk-zynqmp.h (54530ed17d1cc096f9ab0319001c96a63f772c62)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2016-2018 Xilinx
4 */
5
6#ifndef __LINUX_CLK_ZYNQMP_H_
7#define __LINUX_CLK_ZYNQMP_H_
8

--- 19 unchanged lines hidden (view full) ---

28#define ZYNQMP_CLK_DIVIDER_ONE_BASED BIT(0)
29#define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO BIT(1)
30#define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO BIT(2)
31#define ZYNQMP_CLK_DIVIDER_HIWORD_MASK BIT(3)
32#define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST BIT(4)
33#define ZYNQMP_CLK_DIVIDER_READ_ONLY BIT(5)
34#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO BIT(6)
35
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2016-2018 Xilinx
4 */
5
6#ifndef __LINUX_CLK_ZYNQMP_H_
7#define __LINUX_CLK_ZYNQMP_H_
8

--- 19 unchanged lines hidden (view full) ---

28#define ZYNQMP_CLK_DIVIDER_ONE_BASED BIT(0)
29#define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO BIT(1)
30#define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO BIT(2)
31#define ZYNQMP_CLK_DIVIDER_HIWORD_MASK BIT(3)
32#define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST BIT(4)
33#define ZYNQMP_CLK_DIVIDER_READ_ONLY BIT(5)
34#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO BIT(6)
35
36/* Type Flags for mux clock */
37#define ZYNQMP_CLK_MUX_INDEX_ONE BIT(0)
38#define ZYNQMP_CLK_MUX_INDEX_BIT BIT(1)
39#define ZYNQMP_CLK_MUX_HIWORD_MASK BIT(2)
40#define ZYNQMP_CLK_MUX_READ_ONLY BIT(3)
41#define ZYNQMP_CLK_MUX_ROUND_CLOSEST BIT(4)
42#define ZYNQMP_CLK_MUX_BIG_ENDIAN BIT(5)
43
36enum topology_type {
37 TYPE_INVALID,
38 TYPE_MUX,
39 TYPE_PLL,
40 TYPE_FIXEDFACTOR,
41 TYPE_DIV1,
42 TYPE_DIV2,
43 TYPE_GATE,

--- 45 unchanged lines hidden --- 		44enum topology_type {
45 TYPE_INVALID,
46 TYPE_MUX,
47 TYPE_PLL,
48 TYPE_FIXEDFACTOR,
49 TYPE_DIV1,
50 TYPE_DIV2,
51 TYPE_GATE,

--- 45 unchanged lines hidden ---